Low Skew Zero Delay Buffer

PL123E-09
(Preliminary)
Low Skew Zero Delay Buffer
FEATURES
DESCRIPTION
Frequency Range 10MHz to 220MHz
Zero input - output delay.
Low Output to Output Skew
Optional Drive Strength:
Standard (8mA) PL123E-09
High (12mA) PL123E-09H
2.5V or 3.3V, ±10% operation.
Available in 16-Pin SOP or TSSOP packages
The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed
to distribute high speed clocks. It has two low-skew
output banks, of 4 outputs each, that are synchronized
with the input. Control of the two banks of outputs is
achieved by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant applications.
BLOCK DIAGRAM
PLL
REF
Mux
CLKOUT
CLKA2
CLKA3
Bank A
CLKA1
CLKA4
S2
Selector
Inputs
CLKB2
CLKB3
Bank B
S1
CLKB1
REF
1
16
CLKOUT
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
11
CLKB4
CLKB2
7
10
CLKB3
S2
8
9
S1
CLKB4
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 1
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
PIN DESCRIPTIONS
Package Type
Name
Type
Description
TSSOP-16L
SOP-16L
REF [1]
1
1
I
Input reference frequency.
CLKA1 [2]
2
2
O
Buffered clock output, Bank A
CLKA2 [2]
3
3
O
Buffered clock output, Bank A
VDD
4,13
4,13
P
VDD connection
GND
5,12
5,12
P
GND connection
CLKB1 [2]
6
6
O
Buffered clock output, Bank B
CLKB2 [2]
7
7
O
Buffered clock output, Bank B
S2 [3]
8
8
I
Selector input
S1 [3]
9
9
I
Selector input
CLKB3 [2]
10
10
O
Buffered clock output, Bank B
CLKB4 [2]
11
11
O
Buffered clock output, Bank B
CLKA3 [2]
14
14
O
Buffered clock output, Bank A
CLKA4 [2]
15
15
O
Buffered clock output, Bank A
CLKOUT [2]
16
16
O
Buffered clock output. Internal feedback on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION
S2
S1
CLOCK A1–A4
(Bank A)
CLOCK B1–B4
(Bank B)
CLKOUT
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
INPUT / OUTPUT SKEW CONTROL
The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjustments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact PhaseLink for more information.
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 2
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1 F for designs
using frequencies < 50MHz and 0.01 F for designs
using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
To CMOS Input
( Typical buffer impedance 20
50
line
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 3
PL123E-09
(Preliminary)
Low Skew Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ........................... V SS – 0.5V to 4.6V
Storage Temperature ........................ –65°C to 150°C
Junction Temperature ................................... 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)……………..> 2000V
OPERATING CONDITIONS
Description
Parameter
Min
Max
Unit
Supply Voltage
V DD
2.25
3.63
V
Load Capacitance, <100 MHz, 3.3V
CL
–
30
pF
Load Capacitance, <100 MHz, 2.5V with High Drive
–
30
pF
Load Capacitance, <133.3 MHz, 3.3V
–
22
pF
Load Capacitance, <133.3 MHz, 2.5V with High Drive
–
22
pF
Load Capacitance, <133.3 MHz, 2.5V with Standard Drive
–
15
pF
Load Capacitance, >133.3 MHz, 3.3V
–
15
pF
Load Capacitance, >133.3 MHz, 2.5V with High Drive
–
15
pF
–
5
pF
[4]
Input Capacitance [5]
C IN
Closed-loop bandwidth (typical), 3.3V
BW
1
MHz
0.5
MHz
23
Ω
Output Impedance (typical), 3.3V Standard Drive
33
Ω
Output Impedance (typical), 2.5V High Drive
26
Ω
Output Impedance (typical), 2.5V Standard Drive
39
Ω
Closed-loop bandwidth (typical), 2.5V
Output Impedance (typical), 3.3V High Drive
Power-up time for all V DD ’s to reach minimum specified
voltage (power ramps must be monotonic)
R OUT
t PU
0.01
250
ms
Notes:
4.
5.
6.
Applies to Test Circuit #1.
Applies to both REF Clock and internal feedback path on CLKOUT.
Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil -Spec 883E Method 1012.1.
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 4
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
3.3V DC ELECTRICAL SPECIFICATIONS
Description
Parameter
Test Conditions
Min
Max
Unit
Supply Voltage
V DD
2.97
3.63
V
Input LOW Voltage
V IL
–
0.8
V
Input HIGH Voltage
V IH
2.5
V DD + 0.3
V
Input Leakage Current
I IL
0 < V IN < V IL
–
±10
µA
Input HIGH Current
I IH
V IN = V DD
–
100
µA
Output LOW Voltage
V OL
Output HIGH Voltage
V OH
–
–
2.4
2.4
0.4
0.4
–
–
V
V
V
V
Supply Current
I DD
–
45
mA
Min
Max
Unit
I OL = 8 mA (Standard Drive)
I OL = 12 mA (High Drive)
I OH = –8 mA (Standard Drive)
I OH = –12 mA (High Drive)
Unloaded outputs, 66-MHz REF
2.5V DC ELECTRICAL SPECIFICATIONS
Description
Parameter
Test Conditions
Supply Voltage
V DD
2.25
2.75
V
Input LOW Voltage
V IL
–
0.7
V
Input HIGH Voltage
V IH
1.7
V DD + 0.3
V
Input Leakage Current
I IL
0<V IN < V IL
–
±10
µA
Input HIGH Current
I IH
V IN = V DD
–
100
µA
Output LOW Voltage
V OL
Output HIGH Voltage
V OH
–
–
V DD – 0.6
V DD – 0.6
0.5
0.5
–
–
Supply Current
I DD
–
30
I OL = 8 mA (Standard Drive)
I OL = 12 mA (High Drive)
I OH = –8 mA (Standard Drive)
I OH = –12 mA (High Drive)
Unloaded outputs, 66-MHz REF
V
V
mA
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 5
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS
Description
Parameter Test Conditions
Maximum Frequency [7]
(Input/Output)
1/t 1
Input Duty Cycle
(PLL Mode only)
T IDC
Output Duty Cycle [8]
t2 ÷ t1
Rise, Fall Time (3.3V) [8]
Rise, Fall Time (2.5V) [8]
Output to Output Skew
[8]
Delay, REF Rising Edge
to CLKOUT Rising Edge [8]
Part to Part
Skew [8]
PLL Lock Time [8]
Cycle-to-Cycle Jitter,
Peak [8, 9]
t 3 ,t 4
t3, t 4
t5
t6
t7
t LOCK
T JCC
Min
Typ
Max
Unit
3.3V High Drive
10
–
220
MHz
3.3V Standard Drive
10
–
167
MHz
2.5V High Drive
10
–
200
MHz
2.5V Standard Drive
10
–
134
MHz
<133.3 MHz
25
–
75
%
>133.3 MHz
40
–
60
%
<133.3 MHz
47
–
53
%
>133.3 MHz
45
–
55
%
Standard Drive, CL = 30 pF, <100 MHz
–
1.6
–
ns
Standard Drive, CL = 22 pF, <133.3 MHz
–
1.6
–
ns
Standard Drive, CL = 15 pF, <167 MHz
–
0.6
–
ns
High Drive, CL = 30 pF, <100 MHz
–
1.2
–
ns
High Drive, CL = 22 pF, <133.3 MHz
–
1.2
–
ns
High Drive, CL = 15 pF, >133.3 MHz
–
0.5
–
ns
Standard Drive, CL = 15 pF, <133.33 MHz
–
1.5
–
ns
High Drive, CL = 30 pF, <100 MHz
–
2.1
–
ns
High Drive, CL = 22 pF, <133.3 MHz
–
1.3
–
ns
High Drive, CL = 15 pF, >133.3 MHz
–
1.2
–
ns
All outputs equally loaded
–
–
100
ps
PLL enabled @ 3.3V
–100
–
100
ps
PLL enabled @2.5V
–200
–
200
ps
Measured at V DD /2.
Any output to any output, 3.3V supply
–
–
±150
ps
Measured at V DD /2.
Any output to any output, 2.5V supply
–
–
±300
ps
Stable power supply, valid clocks presented on REF and CLKOUT pins
–
–
1.0
ms
3.3V, >66 MHz, <15 pF
–
–
55
ps
3.3V, >66 MHz, <30 pF, Standard. Drive
–
–
125
ps
3.3V, >66 MHz, <30 pF, High Drive
–
–
100
ps
2.5V, >66 MHz, <15 pF, Standard. Drive
–
–
95
ps
2.5V, >66 MHz, <15 pF, High Drive
–
–
65
ps
2.5V, >66 MHz, <30 pF, High Drive
–
–
145
ps
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 6
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS (continued)
Description
Period Jitter, Peak [8,9]
Parameter
T PER
Test Conditions
Min
Typ
Max
Unit
3.3V, 66–100 MHz, <15 pF
–
–
75
ps
3.3V, >100 MHz, <15 pF
–
–
45
ps
3.3V, >66 MHz, <30 pF, Standard Drive
–
–
100
ps
3.3V, >66 MHz, <30 pF, High Drive
–
–
70
ps
2.5V, >66 MHz, <15 pF, Standard. Drive
–
–
60
ps
2.5V, 66–100 MHz, <15 pF, High Drive
–
–
60
ps
2.5V, >100 MHz, <15 pF, High Drive
–
–
45
ps
Notes:
7. For the given maximum loading conditions. See C L in Operating Conditions Table.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
9. Typical jitter is measured at 3.3V or 2.5V, 29 °C, with all outputs driven into the maximum specified load.
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 7
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
All Outputs Rise/Fall Time
OUTPUT
2.0V(1.8V)
2.0V(1.8V)
0.8V(0.6V)
0.8V(0.6V)
t3
3.3V (2.5V)
0V
t4
Output-Output Skew
OUTPUT
VDD/2
OUTPUT
VDD/2
t5
Input-Output Propagation Delay
INPUT
VDD/2
CLKOUT
VDD/2
t6
Device-Device Skew
Any Output, Part 1 or 2
1
Any Output, Part 1 or 2
1
VDD/2
VDD/2
t7
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(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
TEST CIRCUITS
Test Circuit #1
VDD
0.1 F
CLK
OUTPUTS
C LOAD
VDD
0.1 F
GND
GND
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
16 PIN Narrow SOP, TSSOP ( mm )
SOP
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
5.80
6.20
0.40
1.27
1.27 BSC
TSSOP
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
B
L
e
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 9
(Preliminary)
PL123E-09
Low Skew Zero Delay Buffer
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
2880 Zanker Road, Suite 103 San Jose CA95134 USA
Tel (408) 571-1668 Fax (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL123E-09(H) X X - X
Part Number
H=High Drive
None = Standard Drive
None=Tubes
R=Tape & Reel
Package Type
O=TSSOP
S=SOP
Part/Order Number
PL123E-09OC
PL123E-09OC-R
PL123E-09HOC
PL123E-09HOC-R
PL123E-09SC
PL123E-09SC-R
PL123E-09HSC
PL123E-09HSC-R
PL123E-09OI
PL123E-09OI-R
PL123E-09HOI
PL123E-09HOI-R
PL123E-09SI
PL123E-09SI-R
PL123E-09HSI
PL123E-09HSI-R
*Note:
Temperature Range
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Marking
P123E09
OC
LLLLL
P123E09H
OC
LLLLL
P123E09
SC
LLLLL
P123E09H
SC
LLLLL
P123E09
OI
LLLLL
P123E09H
OI
LLLLL
P123E09
SI
LLLLL
P123E09H
SI
LLLLL
Package Option
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin SOP Tube
16-Pin SOP (Tape and Reel)
16-Pin SOP Tube
16-Pin SOP (Tape and Reel)
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin TSSOP Tube
16-Pin TSSOP (Tape and Reel)
16-Pin SOP Tube
16-Pin SOP (Tape and Reel)
16-Pin SOP Tube
16-Pin SOP (Tape and Reel)
LLLLL designates lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fu rnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning th e accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
2880 Zanker Road, Suite 103 San Jose CA95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 12/13/11 Page 10