PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) DIE CONFIGURATION FEATURES XIN VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF GNDBUF (0,0) 2 GND Y X Pad #9 OUTSEL Value 0 LVDS Size 62 x 65 mil 1 PECL (default) Reverse side Pad dimensions Thickness GND 80 micron x 80 micron 10 mil X- Pad #9 OUTSEL 0 X+ Q GNDBUF N/C 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS OUTSEL^ Selected Output Name OE 17 16 OUTPUT SELECTION AND ENABLE DIE SPECIFICATIONS BLOCK DIAGRAM (1550,1475) 9 1 GND The PLL620-20 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies. 25 GND DESCRIPTION VDD 100MHz to 200MHz Fund. or 3 rd OT Crystal. Output range: 100 – 200MHz (no multiplication). Available outputs: PECL, or LVDS. OESEL/OECTRL for both PECL & LVDS. Supports 2.5V or 3.3V-Power Supply. Available in die form. Die thickness 10 mil. 62 mil • • • • • • • N/C 65 mil 1 Pad #30 OE_CTRL 0 1 0 1 State Tri-state Output enabled (default) Output enabled (default) Tri-state Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OUTSEL is “1” Logical states defined by CMOS levels if OUTSEL is “0” Q Oscillator Amplifier PLL620-20 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 1 PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc V DD VI Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model VO TS TA TJ MIN. MAX. UNITS -0.5 4.6 V DD +0.5 V V V DD +0.5 150 85 125 260 2 V -0.5 -65 -40 °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Recommended ESR SYMBOL CONDITIONS Fundamental or 3 rd overtone* Die only F XIN C L (xtal) C0 MIN. TYP. 100 UNITS 200 MHz 3 pF pF 30 25 30 Ω Ω Ω 3.0 F XIN <160MHz and C0<3.0pF F XIN <200MHz and C0<3.0pF F XIN <200MHz and C0<2.5pF RE MAX. * Note: 3 rd overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating. 3. General Electrical Specifications PARAMETERS Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL I DD CONDITIONS MIN. TYP. PECL/LVDS V DD @ 1.25V (LVDS) @ V DD – 1.3V (PECL) 2.97 45 45 50 50 ±50 MAX. UNITS 100/80 mA 3.63 55 55 V % mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 2 PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) 4. Jitter Specifications PARAMETERS Period jitter RMS at 155MHz Period jitter peak-to-peak at 155MHz Accumulated jitter RMS at 155MHz Accumulated jitter peak-to-peak at 155MHz Random Jitter Integrated jitter RMS at 155MHz CONDITIONS MIN. At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz TYP. MAX. UNITS 2.5 18.5 20 ps 2.5 24 27 2.5 0.3 ps ps 0.4 ps Note: Higher Q factor of 3 rd overtone crystals will result in even better jitter performance. 5. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz -75 -95 -125 -140 -145 dBc/Hz Note: Higher Q factor of 3 rd overtone crystals will result in even better phase noise performance. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 3 PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) 6 . LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 7. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 4 PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) 8. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 9. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns PECL Levels Test Circuit OUT PECL Output Skew VDD 50Ω OUT 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 5 PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) PAD ASSIGNMENT Pad # Name X (µ µ m) Y (µ µ m) Description 1 2 Optional GND Optional GND 248 361 109 109 Optional Ground. Optional Ground. 3 4 5 6 7 8 Optional GND Optional GND GND Reserved Optional GNDBUF GNDBUF 473 587 702 874 1042 1171 109 109 109 109 109 109 9 OUTSEL 1400 125 10 11 12 13 14 15 LVDS PECL VDDBUF Optional VDDBUF PECLB LVDSB 1400 1400 1400 1400 1400 1400 259 476 616 716 871 1089 Optional Ground. Optional Ground. Ground. Reserved for future use. Optional Ground, buffer circuitry. Ground, buffer circuitry. Output type selector. Internal pull up. See Output Selection and Enable table on page 1. Internal pull up. LVDS output. PECL output. 3.3V power supply, buffer circuitry. Optional 3.3V power supply, buffer circuitry. Complementary PECL output. Complementary LVDS output. 16 17 18 19 20 21 Not connected GNDBUF Reserved Reserved Not connected Optional VDD 1400 1389 1232 1042 854 659 1227 1365 1365 1365 1365 1365 Not Connected. Ground, buffer circuitry. Reserved for future use. Reserved for future use. Not Connected. Optional 3.3V power supply. 22 23 24 25 26 27 Optional VDD VDD Optional VDD Not connected XIN XOUT 559 459 358 194 109 109 1365 1365 1365 1365 1223 1017 Optional 3.3V power supply. 3.3V power supply. Optional 3.3V power supply. Not Connected. Crystal input. See Crystal Specifications on page 2. Crystal output. See Crystal Specifications on page 2. 28 29 Not connected Not connected 109 109 858 646 30 OE_CTRL 109 397 31 Not connected 109 181 Not Connected. Not Connected. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Not Connected. Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 6 PLL620-20 Low Phase Noise XO (for HF Fund. and 3 rd O.T.) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-20 D C PART NUMBER TEMPERATURE C=COMMERCIAL PACKAGE TYPE D=DIE Order Number PLL620-20DC Marking P620-20DC Package Option Die – Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 05/08/07 Page 7