PL611-30 Programmable Quick Turn Clock FEATURES PIN CONFIGURATION XIN, FIN 1 GND 2 CLK0 3 CLK1 4 PL611-30 • Advanced programmable PLL design • Very low Jitter and Phase Noise (< 40ps Pk-Pk typ.) • Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs. • Output Frequencies: o < 400MHz at 3.3V o < 350MHz at 2.5V • Input Frequencies: o Fundamental Crystal: 10MHz - 30MHz o 3 RD overtone Crystal: Up to 75MHz o Reference Input: Up to 200MHz • Accepts <1.0V reference signal input voltage • One programmable I/O pin can be configured as Output Enable (OE) input, Frequency Selection (FSEL) input or Reference Clock (CLK2) output. • Single 2.5V or 3.3V ± 10% power supply • Operating temperature range from -40°C to 85°C • Available in 8-pin MSOP/SOP Green/RoHS compliant packages. 8 XOUT 7 OE, FSEL, CLK2 6 DNC 5 VDD (M)SOP-8L DESCRIPTION The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-30 product family can generate any output frequency up to 400MHz from fundamental crystal input between 10MHz - 30MHz, a 3rd overtone crystal of up to 75MHz (3.3V Only) or a Reference Clock from 1MHz to 200MHz. The PL611-30 produces complementary LVCMOS outputs to support LVPECL, LVDS, and LVCMOS inputs. BLOCK DIAGRAM Programming Logic 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev. 01/12/12 Page 1 PL611-30 Programmable Quick Turn Clock KEY PROGRAMMING PARAMETERS CLK[0:2] Output Frequency Output Drive Strength F OUT = F IN * M / (R * P) where M= 11 bit R= 8 bit P= 5 bit 1. CLK[0:1]= F VCO / (4 * P) or F VCO /2 2. CLK[2]= F REF Std: 10mA (default) High: 24mA Crystal Load Programmable Input/Output (pin #7) # of Register Banks ± 200ppm One output pin can be tuning. configured as 1. CLK2 - output 2. FSEL - input 3. OE - input Charge-Pump Current 2 8 levels of charge-pump current setting PIN DESCRIPTION Name Pin # (M)SOP-8L Type Description XIN, FIN 1 I Crystal or Reference input pin GND 2 P GND connection CLK[0:1] 3,4 O Programmable Clock Output [note:CLK0=~CLK1] VDD 5 P VDD connection DNC 6 - Do No Connect This programmable I/O pin can be configured as Output Enable (OE) input, Frequency Select (FSEL) input or CLK2 (F REF ) output. This pin has an internal 60KΩ pull up resistor when used as OE or FSEL. OE, FSEL, CLK2 XOUT 7 8 2880 Zanker Rd., San Jose, California 95134 B O State OE FSEL 0 Tristate CLK[0:1] Select Bank ’0’ 1 (default) Normal mode Select Bank ‘1’ Crystal output pin. Do Not Connect when using F IN Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev. 01/12/12 Page 2 PL611-30 Programmable Quick Turn Clock ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V Supply Voltage Range Data Retention @ 85º C 10 Years Soldering Temperature Storage Temperature TS Ambient Operating Temperature* 240 °C -65 150 °C -40 +85 °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS Crystal Input Frequency CONDITIONS Fundamental Crystal MIN. TYP. 10 MAX. 30 3 rd Overtone Crystal (3.3V Operation Only) 75 Input (F IN ) Frequency UNITS MHz 200 MHz 0.9 V DD Vpp At 3.3V V DD , 15pF Load 3 400 3 350 Settling Time At 2.5V V DD , 15pF Load OE Function; Ta=25º C, 15pF Load. Add one clock period to this measurement for a usable clock output. At power-up (V DD > 2.25V) VDD Sensitivity Frequency vs. V DD +/-10% -2 Input (F IN ) Signal Amplitude Output Frequency OE Enable Time Output Rise Time Output Fall Time Internally AC coupled MHz 10 ns 10 ms 2 ppm 15pF Load, 10/90%V DD , Standard Drive 2.5 3.5 15pF Load, 10/90%V DD , High Drive 1.0 1.5 15pF Load, 90/10%V DD , Standard Drive 2.5 3.5 15pF Load, 90/10%V DD , High Drive 1.0 1.5 50 55 % 500 ps Duty Cycle At V DD /2 Max. output skew between same frequency clocks Equal loading (15pF). Equal frequency & drive strength Period Jitter, peak-to-peak* (10,000 samples measured) With capacitive decoupling between V DD and GND. Operating only CLK[0:1] outputs. 45 40 ns ns ps * Note: Jitter performance depends on the programming parameters. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev. 01/12/12 Page 3 PL611-30 Programmable Quick Turn Clock DC SPECIFICATIONS PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs I DD Operating Voltage V DD Output Low Voltage V OL I OL = +4mA (Standard Drive) Output High Voltage V OH I OH = -4mA (Standard Drive) I OSD I OHD Output Current CONDITIONS MIN. TYP. MAX. UNITS 15 mA 3.63 V 0.4 V At 10MHz, load=15pF 2.25 V DD -0.4 V V OL = 0.4V, V OH = 2.4V (Standard Drive) 10 mA V OL = 0.4V, V OH = 2.4V (High Drive) 24 mA CRYSTAL SPECIFICATIONS PARAMETERS SYMBOL MIN. Fundamental Crystal Resonator Frequency F XIN 10 3 rd Overtone Crystal Resonator Frequency (3.3V Only) F XIN Crystal Loading Rating (The IC can be programmed for any value in this range.) C L (xtal) TYP. 5 Maximum Sustainable Drive Level Operating Drive Level MAX. UNITS 30 MHz 75 MHz 20 pF 500 µW 100 Crystal Shunt Capacitance Effective Series Resistance, Fundamental, 10MHz - 30MHz Effective Series Resistance, 3 rd Overtone, 30MHz - 50MHz [CO< 4pF, C L =5pF/8pF] µW C0 6 pF ESR 30 Ω ESR 100/70 Ω Effective Series Resistance, 3 rd Overtone, 50MHz - 65MHz, [CO< 4pF, C L =5pF/8pF] ESR 60/40 Ω Effective Series Resistance, 3 rd Overtone, 65MHz - 75MHz [CO< 4pF, C L =5pF/8pF] ESR 45/30 Ω 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev. 01/12/12 Page 4 PL611-30 Programmable Quick Turn Clock TERMINATING COMPLEMENTARY LVCMOS OUTPUTS Figure 1 below describes how to terminate the complementary LVCMOS outputs of PhaseLink’s PL611-30 Programmable QTC clock for use with LVPECL or LVDS inputs. The unique feature of complementary LVCMOS outputs allows great flexibility for board designers. By standardizing on one termination scheme you can use the PL611-30 for all your LVDS and LVPECL clock requirements up to 400MHz. +3.3V LVCMOS Output R1 50 Ohm line R2 Input R3 Complementary LVCMOS Output R1 50 Ohm line 3.3V 0V R3 R2 +3.3V Complementary Input LVPECL LVDS 2.35V 1.40V 1.59V 1.10V Component selection For LVPECL input For LVDS input Notes: Place R1 as close to the LVCMOS outputs as possible. R1 = 130 Ohm R2 = 82 Ohm R3 = 130 Ohm Place R2 and R3 as close to the LVPECL/LVDS inputs as possible. R1 = 360 Ohm R2 = 130 Ohm R3 = 82 Ohm Figure 1 The above layout allows the PL611-30 to drive either LVPECL or LVDS inputs by simply changing the value of R1. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev. 01/12/12 Page 5 PL611-30 Programmable Quick Turn Clock PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) MSOP-8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. --1.10 0.05 0.15 0.81 0.91 0.25 0.40 0.13 0.23 2.90 3.10 2.90 3.10 4.90 BSC 0.445 0.648 0.65 BSC E H D A2 A A1 C e L b SOP-8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC 2880 Zanker Rd., San Jose, California 95134 E H D A2 A A1 C e b Tel (408) 517-1668 Fax (408) 517-1688 L www.phaselink.com Rev. 01/12/12 Page 6 PL611-30 Programmable Quick Turn Clock ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 517-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL611-30-XXX X X-R PART NUMBER 3 DIGIT ID Code * NONE= TUBE R=TAPE and REEL PACKAGE TYPE M=MSOP-8L S=SOP-8L TEMPERATURE C=COMMERCIAL (0°C to 70°C) I = INDUSTRIAL (-40°C to 85°C) * PhaseLink will assign a unique 3-digit ID code for each approved programmed part number. Part / Order Number PL611-30-XXXMC PL611-30-XXXMC-R PL611-30-XXXSC PL611-30-XXXSC-R Marking Part / Order Number Marking C3XXX LLL PL611-30-XXXMI C3XXX LLLI PL611-30-XXXMI-R P611-30 XXX LLLLL PL611-30-XXXSI PL611-30-XXXSI-R P611-30 XXXI LLLLL Package Option 8-Pin MSOP (Tube) 8-Pin MSOP (Tape and Reel) 8-Pin SOP (Tube) 8-Pin SOP (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 517-1668 Fax (408) 517-1688 www.phaselink.com Rev. 01/12/12 Page 7