Low Skew Output Buffer FEATURES PIN CONFIGURATION Frequency Range: − 15 to 170MHz @ 3.3V − 15 to 145MHz @ 2.5V Internal Phase Locked Loop Allows Spread Spectrum Modulation on Reference Clock to Pass to Outputs. Zero Input to Output Delay Less Than 700ps Device to Device Skew Less Than 200ps Skew Between Outputs Less Than 100ps Cycle to Cycle Jitter 2.5V or 3.3V Power Supply Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS Compliant Packages DESCRIPTION The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 350 ps, the device acts as a zero delay buffer. BLOCK DIAGRAM REFIN PLL CLKOUT CLK1 CLK2 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 1 Low Skew Output Buffer PIN DESCRIPTIONS Pin Number Pin Name SOP-8L SOT23-6L REFIN 1 3 I GND 2 2 P Input reference frequency. Spread spectrum modulation on this signal will be passed to the output (up to 100kHz SST modulation). Ground Connection. CLK1 3 1 O Buffered clock output. CLK2* 4 6 O Buffered clock output. VDD 5 5 P 2.5V or 3.3V Power Supply connection. DNC 6, 7 - - Do Not Connect CLKOUT 8 4 O Buffered clock output. Internal feed back on this pin. Type Description *Note: If CLK2 is pulled high during startup the device will enter test mode. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C 260 C Lead Temperature (soldering, 10s) Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2. Electrical Characteristics PARAMETERS SYMBOL CONDITIONS Supply Voltage V DD Input Low Voltage V IL Input High Voltage V IH Output Low Voltage V OL I OL = 24mA Output High Voltage V OH Supply Current I DD I OH = 24mA Unloaded outputs at 100MHz, V DD =3.3V. MIN. TYP. 2.25 MAX. UNITS 3.63 V 0.8 V 2.0 V 0.4 2.4 V V 22 30 mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 2 Low Skew Output Buffer 3. Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 145/170 MHz 50 55 % Input/Output Frequency t1 2.5V/3.3V 15 Duty Cycle DC Measured at V DD /2, C L =15pF, F out = 100MHz 45 Rise Time Tr Measured between 10% and 90%V DD , C L =15pF 1.2 1.5 ns Fall Time Tf Measured between 90% and 10%, C L =15pF 1.2 1.5 ns 200 ps Output to Output Skew T skew All outputs equally loaded, C L =15pF Delay, REF Rising Edge to CLKOUT Rising Edge T delay Measured at V DD /2 0 350 ps Device to Device Skew T dsk-dsk Measured at V DD /2 on the CLKOUT pins of devices 0 700 ps Cycle to Cycle Jitter T cyc-cyc Measured at 100MHz 60 ps 1.0 ms PLL Lock Time T lock Stable power supply, valid clock presented on REF pin Jitter; Absolute Jitter T jabs Measured 10,000 cycles, low jitter input signal 20 50 ps Jitter; 1-sigma T j1-s Measured 10,000 cycles, low jitter input signal 9 15 ps SWITCHING WAVEFORMS Duty Cycle Timing Output - Output Skew t1 VDD/2 t2 VDD/2 VDD/2 Output VDD/2 VDD/2 Output TSKEW 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 3 Low Skew Output Buffer SWITCHING WAVE FORMS All Outputs Rise/Fall Time 2.0V Output 3.3V 2.0V 0.8V 0.8V tr 0V tf Input to Output Propagation Delay VDD/2 Input VDD/2 Output Tdelay Device to Device Skew VDD/2 Device1 CLKOUT VDD/2 Device2 CLKOUT Tdsk - dsk 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 4 Low Skew Output Buffer Output-Output Skew The skew between CLKOUT and the CLK(1-2) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will be maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must be equally loaded. If the CLK(1-2) outputs are less loaded than CLKOUT, CLK(1-2) outputs will lead it; if the CLK(1-2) is more loaded than CLKOUT, CLK(1-2) will lag the CLKOUT. Since the CLKOUT and the CLK(1-2) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. REF REF CLKOUT CLKOUT CLK(1-2) CLK(1-2) Zero Delay REF input and all outputs are equally loaded Advanced REF input and CLK(1-2) outputs are equally loaded, with CLK(1-2) less loaded than CLKOUT. REF CLKOUT CLK(1-2) Delayed REF input and CLK(1-2) outputs loaded equally, withCLK(1-2) more loaded then CLKOUT. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 5 Low Skew Output Buffer PACKAGE INFORMATION (GREEN PACKAGE COMPLIANT) SOP-8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C L b e SOT23-6L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC E H D A2 A A1 C e b L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 6 Low Skew Output Buffer ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL102-10 X X - X PART NUMBER NONE= TUBE R=TAPE AND REEL TEMPERATURE C=COMMERCIAL (0°C to 70°C) I=INDUSTRIAL (-40°C to 85°C) PACKAGE TYPE S= SOP-8L T= SOT23-6L Part / Order Number Marking* Package Option PL102-10SC P102-10 SC LLL 8-Pin SOP (Tube) PL102-10SC-R P102-10 SC LLL 8-Pin SOP (Tape and Reel) PL102-10TC-R C10A0 LLL 6-Pin SOT (Tape and Reel) * Note: LLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 7