PL135-37 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer FEATURES DESCRIPTION The PL135-37 is an advanced oscillator fanout buffer design for high performance, low-power applications. The PL135-37 accepts a fundamental crystal input of 10MHz to 40MHz and produces three LVCMOS outputs of the same frequency. The Output Enable (OE) function can be used to tri-state the outputs. Advanced Oscillator Design for Wide Frequency Coverage 3 LVCMOS Outputs 12 mA Output Drive Strength Input/Output Frequency: o Fundamental Crystal: 10MHz to 40MHz Very Low Jitter and Phase Noise Low Current Consumption Single 1.62V to 3.63V Power Supply Available in SOP-8L GREEN/RoHS Compliant Package The PL135-27 offers the best phase noise and jitter performance and lowest power consumption of any comparable IC. PACKAGE PIN CONFIGURATION XIN 1 8 XOUT OE^ 2 7 CLK0 CLK1 3 6 VDD GND 4 5 CLK2 SOP-8L BLOCK DIAGRAM CLK0 XIN XOUT XTAL OSC CLK1 CLK2 OE 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 03/18/11 Page 1 PL135-37 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer PIN DESCRIPTION Name SOP-8L Type Description XIN 1 I Crystal input OE 2 I Output enable input. This pin has internal pull-up resistor. All outputs will be tri-stated when pulled low. CLK1 3 O Output clock GND 4 P Ground connection CLK2 5 O Output clock VDD 6 P Power supply CLK0 7 O Output clock XOUT 8 I Crystal output * Note: This pin includes an internal 60KΩ pull up. LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the V DD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections (looks like ringing). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Addition of a ferrite bead in series with V DD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical value to use is 0.1 F. Crystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer (Typical buffer impedance 20Ω) - Multiple V DD pins should be decoupled separately for best performance. Crystal To CMOS Input 50Ω line Cst Series Resistor Use value to match output buffer impedance to 50Ω trace. Typical value 30Ω XIN XOUT 1 Cpt 8 Cpt CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers frequency offset. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 03/18/11 Page 2 PL135-37 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C -40 85 C Supply Voltage Range Ambient Operating Temperature* Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permane nt damage to the device and affect product reliability. These conditions repr esent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specif ication is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS CONDITIONS MIN. TYP. 10 MAX. UNITS 40 MHz Crystal Input Frequency Fundamental Crystal Settling Time At power-up (V DD > 1.62V) 5 ms Output Enable Time OE Function; Ta=25º C, 10pF Load 10 ns V DD Sensitivity Frequency vs. V DD , ±10% 1 ppm Output Rise Time 15pF Load, 10/90% V DD , 3.3V 2 3 ns Output Fall Time 15pF Load, 90/10% V DD , 3.3V 2 3 ns Output to Output Skew Under all conditions 250 ps Duty Cycle Under all conditions -1 45 50 55 % MIN TYP MAX UNITS DC SPECIFICATIONS PARAMETERS Supply Current, Dynamic Supply Current, Standby SYMBOL I DD I DD_SB CONDITIONS V DD = 3.3V, 25MHz, No Load 4 mA V DD = 2.5V, 25MHz, No Load 3 mA V DD = 1.8V, 25MHz, No Load OE Pin Pulled Low, 25MHz, 3.3V 2 mA 1.62 0.6 mA 3.63 V 0.4 V Operating Voltage V DD Output Low Voltage V OL I OL = +12mA, 3.3V Output High Voltage V OH I OH = -12mA, 3.3V 2.4 V Output Current I OSD V OL = 0.4V, V OH = 2.4V 12 mA 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 03/18/11 Page 3 PL135-37 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating SYMBOL MIN. F XIN 10 TYP. C L (xtal) MAX. UNITS 40 MHz 8.5 Maximum Sustainable Drive Level pF 200 Operating Drive Level 50 W W Crystal Shunt Capacitance C0 3 pF Effective Series Resistance ESR 30 Ω PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOP-8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e b 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 L www.phaselink.com Rev 03/18/11 Page 4 PL135-37 Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:3 Oscillator Fanout Buffer ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL135-37 X X - X Part Number Shipping Option R=Tape and Reel Package Type S = SOP-8L Part/Order Number PL135-37SC-R Temperature Range C=Commercial (0°C to 70°C) Marking P135-37 SC LLLLL Package Option 8-Pin SOP-8L (Tape and Reel) *Note: LLLLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without noti ce. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resul ting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the e xpress written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 03/18/11 Page 5