PL602-XX HCSL Compatible Clock Generator for PCI Express FEATURES PIN CONFIGURATION Input Frequency: o Fundamental Crystal or Reference Input: 25MHz Output Frequency: o PL602-21: 100MHz differential outputs. o PL602-22: 125MHz differential outputs. o PL602-23: 200MHz differential outputs. o PL602-26: 25MHz differential outputs. o PL602-27: 250MHz differential outputs. o PL602-15: 156.25 MHz differential outputs. Very low Jitter: 28ps Pk-Pk typ. Very low Phase Noise: o -130 dBc at 10kHz offset at 100MHz No external loop filter is required Power supply range: 2.25V to 3.63V Operating temperature range from -40C to 85C Available in 6-pin SOT or 8-pin SOP Green/RoHS compliant package. XIN 1 8 XOUT GND 2 7 OE CLK0 3 6 DNC CLK1 4 5 VDD SOP-8L CLK1 1 6 CLK0 GND 2 5 VDD FIN 3 4 OE SOT23-6L DESCRIPTION The PL602-XX is the smallest, high performance, lowest power differential output clock IC available for HCSL timing applications. PhaseLink’s PL602-XX offers -130dBc at 10kHz offset at 100MHz, with a very low jitter (2 ps TIE RMS), making it ideal for HCSL applications requiring small size and low power. BLOCK DIAGRAM OE XIN, FIN Xtal Osc XOUT Q Phase Locked Loop QB PIN DESCRIPTION Name Pin # Description Type SOP SOT23 XIN 1 - I Crystal input (SOP package only) FIN - 3 I Reference clock input (SOT23 package only) GND 2 2 P GND connection CLK[0:1] 3,4 1,6 O Differential clock outputs [note:CLK0=~CLK1] VDD 5 5 P VDD connection DNC 6 - - Do not connect OE 7 4 I Output enable (OE) input. Internal 60KΩ pull up resistor. XOUT 8 - O Crystal output pin. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/08/11 Page 1 PL602-XX HCSL Compatible Clock Generator for PCI Express ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V 260 C -65 150 C -40 +85 C Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature* Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS Crystal Input Frequency CONDITIONS MIN. Fundamental Crystal Input (F IN ) Frequency TYP. MAX. UNITS 25 MHz 25 MHz Input (F IN ) Signal Amplitude Internally AC coupled 0.9 V DD Vpp Output Frequency 25 200 MHz Output Enable Time OE Function; Ta=25º C, Add one clock period to this measurement for a usable clock output. 10 ns Output Disable Time OE Function; Ta=25º C 10 ns Settling Time At power-up (V DD > 2.25V) 10 ms VDD Sensitivity Frequency vs. V DD , ±10% 2 ppm Output Rise Time 10/90%V OH 0.3 0.5 ns Output Fall Time 90/10%V OH 0.3 0.5 ns Skew Between Outputs Measured at 50% V OH 250 ps Duty Cycle At V DD /2 55 % Period Jitter, peak-to-peak Cycle-to-Cycle, RMS Cycle-to-Cycle, peak TIE, RMS - With capacitive decoupling between V DD and GND - At 100MHz - 20,000 samples measured 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 -2 45 50 28 ps 9 ps 25 ps 2 ps www.phaselink.com Rev 02/08/11 Page 2 PL602-XX HCSL Compatible Clock Generator for PCI Express DC SPECIFICATIONS PARAMETERS SYMBOL Supply Current, Dynamic I DD Operating Voltage V DD Output Low Voltage V OL Output High Voltage V OH Output Current I OSD CONDITIONS MIN. At 100MHz, No Load TYP. MAX. 25 2.25 HCSL termination, (RS = 150Ω, RT = 49.9Ω) 3.3V (RS = 100Ω, RT = 49.9Ω) 2.5V UNITS mA 3.63 V 0.05 V 0.65 0.75 0.85 V 13 15 17 mA MIN. TYP. MAX. UNITS CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating SYMBOL F XIN 25 MHz C L (xtal) 18 pF Maximum Sustainable Drive Level 500 Operating Drive Level Crystal Shunt Capacitance Effective Series Resistance, Fundamental 100 W W C0 6 pF ESR 45 Ω 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/08/11 Page 3 PL602-XX HCSL Compatible Clock Generator for PCI Express PCI EXPRESS/HCSL COMPATIBLE LAYOUT GUIDELINES Figure 1 below describes how to terminate the complementary LVCMOS outputs of PhaseLink’s PL602-XX for use with HCSL inputs. LVCMOS Output Rs 50 Ohm line Input Rt Complementary LVCMOS Output Rs Complementary Input 3.3V HCSL 0.75V 0V 0V Component Selection For 3.3V Operation Rs = 150 Ohm Rt = 50 Ohm Rt 50 Ohm line For 2.5V Operation Rs = 100 Ohm Rt = 50 Ohm Notes: Place Rs as close to the LVCMOS outputs as possible. Place Rt as close to the HCSL inputs as possible. Figure 1 PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL602-XX as short as possible, as well as keeping all other traces as far away from it as possible. - Place the crystal as close as possible to both crystal pins of the device. This will reduce the cross-talk between the crystal and the other signals. - Separate crystal pin traces from the other signals on the PCB, but allow ample distance between the two crystal pin traces. - Place a 0.01µF~0.1µF decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50Ω impedance and CMOS outputs usually have lower than 50Ω impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/08/11 Page 4 PL602-XX HCSL Compatible Clock Generator for PCI Express PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOP-8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C L b e SOT23-6L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC E H D A2 A A1 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 C e b www.phaselink.com L Rev 02/08/11 Page 5 PL602-XX HCSL Compatible Clock Generator for PCI Express ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range None=Tube R=Tape & Reel 21 = 100MHz 22 = 125MHz 23 = 200MHz 25 = 156.25MHz 26 = 25MHz 27 = 250MHz 15 = 156.25 Part / Order Number PL602-2XSC PL602-2XSC-R PL602-1XTC-R PL602-2XTC-R C=Commercial (0°C to 70°C) I=Industrial (-40°C to 85°C) S=SOP-8L T=SOT23-6L Marking P602-2X SC LLLLL F1X LLL F2X LLL Package Option 8-Pin SOP (Tube) 8-Pin SOP (Tape and Reel) 6-Pin SOT-23 (Tape and Reel) 6-Pin SOT-23 (Tape and Reel) Note: LLL / LLLLL designate Production Lot. PhaseLink Corporation, reserves the right to make changes in its products or specific ations, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 02/08/11 Page 6