(Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS FEATURES 65 mil User selectable output: Differential PECL, Differential LVDS or CMOS/TTL Single internally AC coupled input Accepts input signal swings as low as 100mV Input range from DC to 1.3 GHz. 3.3V operation. 25 24 23 21 22 (1550,1475) 20 19 18 15 27 14 28 Available in DIE (65 mil x 62 mil). 17 16 26 62 mil DIE CONFIGURATION 13 29 12 11 30 DESCRIPTIONS 10 31 The PL130-00 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.3GHz. It provides selectable user outputs, between differential PECL, differential LVDS or CMOS/TTL. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or LVDS to PECL, LVDS or CMOS . BLOCK DIAGRAM 9 1 2 3 4 5 6 7 8 (0,0) Y X DIE SPECIFICATIONS Name Value Size Reverse side 62 x 65 mil GND Pad dimensions 80 micron x 80 micron Thickness 10 mil OUTPUT SELECTION AND ENABLE REF_IN PECL_BAR Input Amplifier PECL Selector Logic OUTSEL0 LVDS_BAR LVDS OUTSEL1 CMOS OE_CTRL Pad #18 OUTSEL1 Pad #25 OUTSEL0 0 0 1 1 0 1 0 OE_SELECT (Pad #9) OE_CTRL (Pad #30) 0 1 (Default) 1 0 (Default) 1 0 1 (Default) Selected Output High Drive CMOS Standard CMOS PECL LVDS State Output enabled Tri-state Tri-state Output enabled Pad # 9: Bond to GND to se t to “0”, bond to VDD to set to “1” Pad # 30: Logical states defined by PECL levels if OE_ SEL ECT (pad # 9) is “0” Logical states defined by CMOS levels if OE_ SEL ECT is “1 ” 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 1 (Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. MAX. UNITS 7 V V DD Input Voltage, dc VI V SS -0.5 V DD +0.5 V Output Voltage, dc VO V SS -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C 260 C 2 kV Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended period s may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only. 2. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) I DD Operating Voltage V DD CONDITIONS MIN. TYP. PECL/LVDS/CMOS 3.13 Short Circuit Current MAX. UNITS 80/60/20 mA 3.47 V mA 50 3. AC Specification PARAMETERS CONDITIONS Input Frequency Input signal swing MIN. 0 REF_IN input Output Frequency TYP. MAX. UNITS 1300 MHz 100 0 mV 1300 MHz Output Rise Time 0.8V to 2.0V with no load 1.5 ns Output Fall Time 2.0V to 0.8V with no load 1.5 ns 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 2 (Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS 4. CMOS Output Electrical Specifications PARAMETERS SYMBOL CONDITIONS Output High Voltage V OH I OH = -12mA Output Low Voltage V OL I LO = 12mA Output High Voltage V OHC I OH = -4mA, at CMOS level Output Drive Current At TTL level MIN. TYP. MAX. 2.4 UNITS V 0.4 V DD – 0.4 V V 12 17 MIN. TYP. mA 5. CMOS Switching Characteristics PARAMETERS Output Clock Rise/Fall Time Output Clock Duty Cycle SYMBOL CONDITIONS 0.8V ~ 2.0V with 10 pF load 1.15 0.3V ~ 3.0V with 15 pF load 3.7 @ 1.4V 45 50 MAX. UNITS ns 55 % 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 3 (Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS 6. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change V OS 0 3 25 mV Power-off Leakage I OXD 1 10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 7. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 C L = 10 pF (see figure) @ 1.25V 0.2 0.7 1.0 ns 45 50 55 % Output Clock Duty Cycle LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50 VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 4 (Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS 8. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 9. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns 50 55 % Output Clock Duty Cycle @ Vdd – 1.3V 45 PECL Levels Test Circuit OUT PECL Output Skew VDD 50 OUT 2.0V 50% 50 OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 5 (Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS PAD ASSIGNMENT Pad # Name X (m) Y (m) 1 GND 248 109 2 GND 361 109 3 GND 473 109 4 GND 587 109 5 GND 702 109 6 REF_IN 874 109 7 GND 1042 109 8 GNDBUF 1171 109 9 OE_SELECT 1400 125 10 LVDS 1400 259 11 PECL 1400 476 12 VDDBUF 1400 616 13 VDDBUF 1400 716 14 PECLB 1400 871 15 LVDSB 1400 1089 16 CMOS 1400 1227 17 GNDBUF 1389 1365 18 OUTSEL1 1232 1365 19 GND 1042 1365 20 VDD (Optional) 854 1365 21 VDD 659 1365 22 VDD 559 1365 23 VDD 459 1365 24 VDD 358 1365 25 OUTSEL0 194 1365 26 GND (Optional) 109 1223 27 N/C 109 1017 28 GND 109 858 29 VDD (Optional) 109 646 30 OE_CTRL 109 397 31 N/C 109 181 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 6 (Preliminary) PL130-00 Selectable High Speed Translator Buffer to CMOS, PECL, LVDS ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL130-00 D C PART NUMBER TEMPERATURATRE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE D=DIE W=Wafer PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 8/10/10 Page 7