Application Note AN502-02X VCXO solution for

Application Note AN502-02X
VCXO solution for ITeX ADSL Analog Front-End
SINGLE CHIP VCXO SOLUTION: PLL502-02
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Specifically designed for ITeX ADSL Analog Front End.
High performance integrated VCXO (>300 ppm pull range) 35.328 MHz nominal frequency.
Works with low cost pullable crystals
Avoids costly external varicaps for crystal tuning or costly metal can VCXO.
Small circuit board footprint.
SOLUTION DESCRIPTION
PhaseLink PLL502-02 integrated VCXO chip has been specifically designed to meet the VCXO functionality of the ADSL analog frontend family from ITeX (I80134 and I80234).
The single chip solution provided by PhaseLink Corp. will avoid expensive discrete components while saving footprint.
The nominal output frequency of the VCXO is 35.328 MHz (> 300 ppm pullability) using a 17.664 MHz low cost crystal. Crystal must be parallel resonant,
with a C0/C1 < 250. Care must be given to the CL rating of the crystal: at nominal voltage control (1.65V) the load capacitance presented to the crystal by the
PLL502-02 is 9.5pF. Therefore, if the PLL502-02 is used with a crystal rated for CL more than 9.5pF, the additional capacitive load must be added externally
(with fixed capacitors), in order to properly center the pull-range curve around nominal frequency. Example, for crystal rated for CL = 14.5pF, two external
10pF capacitors (one between each electrode of the crystal and GND) are required in order to load the crystal correctly. Indeed, the two external capacitors
(seen in series by the crystal) will result in an additional 5pF in parallel to the 9.5pF presented by the PLL502-02, thus providing the total 14.5pF required by
the crystal (9.5pF // 5pF = 14.5pF). However, if the crystal used with the PLL502-02 is rated for a CL = 9.5pF, no external capacitors are required.
Layout details:
Figure 1 details two possible bias circuits used to accommodate the current output (VCXOUT) of the AFE chip as control signal (CTRL). Care must be given
to mount the crystal as close to the chip as possible. The external capacitors required by crystals of CL greater than 9.5pF are not shown on the figure.
However, these external capacitors must be mounted as close to the crystal as possible. Standard decoupling capacitors (not shown in fig. 1) between VDD
and GND are required: 2µF (or larger) for low frequency decoupling, and 100nF for higher frequency decoupling. The 100nF high frequency decoupling
capacitors must be mounted as close to the chip as possible (see data sheets for details).
Figure 1. Application diagrams
AVDD
XTAL
AVDD
R ref
VCOCAP
IVCO
ITeX AFE
392k Ω
8
1k Ω
1 XIN
XOUT 8
2 N/C
N/C 7
3.3V
DAC
3 CTRL
VDD 6
4 GND
CLK 5
CTRLIN
PN2907
VCXOUT
0.1uF
8.25k Ω
1k Ω
0.1uF
Freq.
doubler
MUX
XTAL1
CLOCK
AVDD
XTAL
AVDD
R ref
VCOCAP
IVCO
270k Ω
ITeX AFE
1 XIN
XOUT 8
2 N/C
N/C 7
3.3V
120k Ω
8
DAC
3 CTRL
VDD 6
4 GND
CLK 5
CTRLIN
VCXOUT
8.25k Ω
0.1uF
Freq.
doubler
MUX
XTAL1
CLOCK
For further information, sample chip or technical support, please contact: Sales@phaselink.com
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/30/01 Page 1