PL123-09N Low Skew Fanout Buffer FEATURES DESCRIPTION • • • • • • • • The PL123-09N is a low-cost fanout buffer for distributing high-speed clocks with low output to output skew. The PL123-09N accepts an input from DC to 134MHz and provides 9 outputs of the same frequency. A typical application for driving SDRAM in PC systems would use eight outputs to drive two DIMMs, or four SO-DIMMs, with the remaining output used for driving an external feedback to a PLL. 1:9 output fanout buffer for DC to 134MHz Low power consumption for portable applications Low input-output delay Output-Output skew less than 250ps Low Additive Phase Jitter of 60fs RMS 2.5V to 3.3V, ±10% operation Operating temperature range from -40°C to 85°C Available in 16-Pin SOP GREEN/RoHS package The PL123-09N is designed with three pairs of power/ground pins to minimize EMI and it consumes less than 32 mA at 66 MHz, ideal for low-power mobile applications. It is available in a compact 150-mil 16-pin SOP package. These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM AND PACKAGE PINOUT CLK1 CLK2 CLK3 REF REF 1 16 CLK9 CLK1 2 15 CLK8 CLK2 3 14 CLK7 CLK4 VDD 4 13 VDD CLK5 GND 5 12 GND CLK6 CLK3 6 11 CLK6 CLK4 7 10 CLK5 VDD 8 9 GND CLK7 CLK8 CLK9 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 SOPSOP-16L 16L www.phaselink.com Rev 08/26/10 Page 1 PL123-09N Low Skew Fanout Buffer PIN DESCRIPTIONS Name SOP-16L Type Description REF 1 I Input reference frequency. CLK1 2 O Buffered clock output CLK2 3 O Buffered clock output VDD 4, 8, 13 P VDD connection GND 5, 9, 12 P GND connection CLK3 6 O Buffered clock output CLK4 7 O Buffered clock output CLK5 10 O Buffered clock output CLK6 11 O Buffered clock output CLK7 14 O Buffered clock output CLK8 15 O Buffered clock output CLK9 16 O Buffered clock output LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces (> 1 inch) as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1µF for designs using frequencies < 50MHz and 0.01µF for designs using frequencies > 50MHz. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/26/10 Page 2 PL123-09N Low Skew Fanout Buffer ABSOLUTE MAXIMUM CONDITIONS Supply Voltage to Ground Potential ...... –0.5V to 4.6V DC Input Voltage ........................... V SS – 0.5V to 4.6V Storage Temperature ........................ –65°C to 150°C Junction Temperature………………………….. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)…………..> 2000V OPERATING CONDITIONS Parameter Description Min. Max. Unit V DD Supply Voltage 2.25 3.63 V 0 70 °C Industrial Operating Temperature (ambient temperature) -40 85 °C Load Capacitance, below 100 MHz ― 30 pF Load Capacitance, above 100 MHz ― 10 pF C IN Input Capacitance ― 7 pF REF, CLK[1:9] Operating Frequency, Input=Output DC 134 MHz t PU Power-up time for all V DD s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Commercial Operating Temperature (ambient temperature) TA CL ELECTRICAL CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter Description Test Conditions Min. Max. Unit – 0.8 V 2.0 – V VIL Input LOW Voltage [1] VIH Input HIGH Voltage [1] IIL Input LOW Current VIN = 0V – 50 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage [2] IOL = 8 mA – 0.4 V VOH Output HIGH Voltage [2] IOH = –8 mA 2.4 – V IDD Supply Current 66.67MHz with unloaded outputs – 32 mA SWITCHING CHARACTERISTICS (Commercial and Industrial Temperature Devices) [3] Parameter Description Test Conditions Min. Typ. Max. Unit Duty Cycle [2] = t2 ÷ t1 Measured at 1.4V 40 50 60 % t3 Rise Time [2] Measured between 0.8V and 2.0V – – 1.5 ns t4 Fall Time [2] Measured between 0.8V and 2.0V – – 1.5 ns t5 Output to Output Skew [2] All outputs equally loaded – – 250 ps t6 Propagation Delay, REF Rising Edge to CLKX Rising Edge [2] Measured at VDD/2 1 5 9.2 ns Notes: 1. REF input has a threshold voltage of V DD /2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. 3. All parameters are specified with loaded outputs. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/26/10 Page 3 PL123-09N Low Skew Fanout Buffer NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices) Parameter Description Test Conditions Min. Additive Phase Jitter V DD=3.3V, Frequency=100MHz Offset=12KHz ~ 20MHz Typ. Max. Unit 60 fs 10000000 100000000 PL123-09N Additive Phase Jitter: VDD=3.3V, CLK=100MHz, Integration Range 12KHz to 20MHz: 0.059ps typical. REF Input PL123-09N Output 10000 100000 -60 -70 -80 Phase Noise (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 10 100 1000 1000000 Offset Frequency (Hz) When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: 2 Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter) 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 2 www.phaselink.com Rev 08/26/10 Page 4 PL123-09N Low Skew Fanout Buffer SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 1.4V All Outputs Rise/Fall Time 1.4V 2.0V 2.0V 0.8V OUTPUT 3.3V 0.8V t3 0V t4 Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t5 Input-Output Propagation Delay VDD/2 INPUT VDD/2 OUTPUT t6 TEST CIRCUIT VDD 0.1 µF OUTPUTS C LOAD VDD 0.1 µF GND CLK GND 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/26/10 Page 5 PL123-09N Low Skew Fanout Buffer PACKAGE DRAWING (GREEN PACKAGE COMPLIANT) SOPSOP-16L 16L ( mm ) Symbol A A1 B C D E H L e Min. Max.. Min. Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 5.80 6.20 0.40 1.27 1.27 BSC E H D A A1 C B L e 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/26/10 Page 6 PL123-09N Low Skew Fanout Buffer ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part/Order Number PL123-09NSC PL123-09NSC-R PL123-09NSI PL123-09NSI-R Marking Package Option Green (Lead-Free) Package P123-09N 16-Pin SOP Tube SC 16-Pin SOP (Tape and Reel) LLLLL P123-09N 16-Pin SOP Tube SI 16-Pin SOP (Tape and Reel) LLLLL *Note: LLLLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 08/26/10 Page 7