PL602-03 Low Phase Noise CMOS XO (48MHz to 100MHz) FEATURES Low phase noise XO output for the 48MHz to 100MHz range (-130 dBc at 10kHz offset). 12 to 25MHz crystal input. Integrated crystal load capacitor: no external load capacitor required. Selectable High Drive (30mA) or Standard Drive (10mA) output. 3.3V operation. Available in 8-Pin TSSOP or SOIC. CLK 1 VDD 2 OE^ 3 XIN 4 PL602-03 PIN CONFIGURATION 8 GND 7 GND 6 N/C 5 XOUT Note: ^ denotes internal pull up OUTPUT RANGE DESCRIPTION The PL602-03 is a low cost, high performance and low phase noise XO, providing less than -130dBc at 10kHz offset in the 48MHz to 100MHz operating range. The very low jitter makes this chip ideal for applications requiring clean reference frequency sources. Input crystal can range from 12 to 25MHz (fundamental resonant mode). FREQUENCY RANGE 48 - 100MHz MULTIPLIER X4 OUTPUT BUFFER CMOS BLOCK DIAGRAM VCO Divider Reference Divider XIN XOUT Phase Comparator Charge Pump Loop Filter VCO CLK OE XTAL OSC 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/16/11 Page 1 PL602-03 Low Phase Noise CMOS XO (48MHz to 100MHz) PIN DESCRIPTIONS Name Number Type Description CLK 1 O Output clock. VDD 2 P power supply. OE 3 I Output enable input. Disables (tri-state) output when low. Internal pull-up enables output by default if pin is not connected to low. XIN 4 I Crystal input. See Crystal Specification on page 3. XOUT 5 I Crystal output. See Crystal Specification on page 3. N/C 6 - Not connected. GND 7, 8 P Ground. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS 4.6 V DD +0.5 V V V DD +0.5 150 85 260 2 V Supply Voltage Input Voltage, dc V DD VI -0.5 Output Voltage, dc Storage Temperature Ambient Operating Temperature* Lead Temperature (soldering, 10s) ESD Protection, Human Body Model VO TS TA -0.5 -65 -40 C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for e xtended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDU STRIAL), but tested for COMMERCIAL grade only. 2. DC Specifications PARAMETERS Supply Current, Dynamic, with Loaded Outputs Operating Voltage SYMBOL I DD CONDITIONS MIN. TYP. F XIN = 12 - 25MHz Output load of 10pF V DD 2.97 MAX. UNITS 35 mA 3.63 V Output drive current (High Drive) I OH V OH = V DD -0.4V, V DD =3.3V 30 mA I OL V OL = 0.4V, V DD = 3.3V 30 mA Output drive current (Standard Drive) I OH V OH = V DD -0.4V, V DD =3.3V 10 mA I OL V OL = 0.4V, V DD = 3.3V 10 mA 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/16/11 Page 2 PL602-03 Low Phase Noise CMOS XO (48MHz to 100MHz) 3. AC Specifications PARAMETERS SYMBOL CONDITIONS Input Crystal Frequency Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive) Output Clock Duty Cycle MIN. TYP. 12 0.3V ~ 3.0V with 15 pF load 2.4 0.3V ~ 3.0V with 15 pF load 1.2 Measured @ 50% V DD 45 MAX. UNITS 25 MHz ns 50 55 % 4. Jitter and Phase Noise Specification PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS RMS Period Jitter (1 sigma – 1000 samples) Phase Noise relative to carrier at 80MHz, with capacitive decoupling between VDD and GND. 80MHz @100Hz offset 20 ps -106 dBc/Hz Phase Noise relative to carrier 80MHz @1kHz offset -124 dBc/Hz Phase Noise relative to carrier 80MHz @10kHz offset -130 dBc/Hz Phase Noise relative to carrier 80MHz @100kHz offset -122 dBc/Hz Phase Noise relative to carrier 80MHz @1MHz offset -121 dBc/Hz 5. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Capacitance Rating Driving power SYMBOL MIN. F XIN C L (xtal) 12 ESR TYP. MAX. UNITS 25 MHz pF mW 30 20 1 RS PACKAGE INFORMATION 8 PIN ( dimensions in mm ) TSSOP Min. A Narrow SOIC Max . 1.34 1.74 - Max . 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 4.80 4.95 2.90 3.10 Symbol Min. E 3.80 4.00 4.30 4.50 H 5.80 6.20 6.20 6.60 L 0.38 1.27 0.45 e 1.27 BSC E H D A 0.75 0.65 BSC A1 C L B e 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/16/11 Page 3 PL602-03 Low Phase Noise CMOS XO (48MHz to 100MHz) ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range P L602-03 (H) X C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL Optional High Drive PACKAGE TYPE S=SOIC, O=TSSOP Part/Order Number (Commercial) PL602-03OC PL602-03OC-R PL602-03HOC PL602-03HOC-R PL602-03SC PL602-03SC-R PL602-03HSC PL602-03HSC-R Marking* P602-03 OC LLLLL P602-03 HOC LLLLL Package Option 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) P602-03 SC LLLLL P602-03 HSC LLLLL 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) *Note: LLLLL designates lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fu rnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this prod uct. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the e xpress written approval of the President of PhaseLink Corporation. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 11/16/11 Page 4