PicoEMI T M Programmable Spread Spectrum Clock FEATURES DESCRIPTION Advanced programmable Spread Spectrum clock generator with 16 modulation steps to choose from Programmable SST Modulation Magnitude: o Center Spread: ±0.125% to ±2.0% in ±0.125% steps o Down Spread: -0.25% to -4.0% in 0.25% steps Input Frequency Range: o Fundamental Crystal: 10MHz to 40MHz Output Frequency Range: o 1MHz to 200MHz @ 3.3V operation o 1MHz to 166MHz @ 2.5V operation Programmable Output Drive (4mA, 8mA, 16mA) Low Cycle to Cycle jitter, 100pS Single 2.5V to 3.3V, ± 10% power supply Available in Die form The PL671-00 is an advanced programmable Spread Spectrum clock generator (PSSCG), and a member of PhaseLink’s PicoPLL Programmable Clock family. The PL671-00 clock outputs can be programmed up to 200MHz (3.3V) or 166MHz (2.5V), and has 16 modulation magnitudes (±0.125 to ±2.0% or -0.25 to -4.0%) to choose from for use in Center or Down Spread modulation applications. In addition, 2 configuration pins can be programmed to allow cycling the device through 4 preprogrammed states*. The option of being able to turn ‘ON/OFF’ the Spread Spectrum modulation allows for completing a design with PL671-00 and having the assurance of turning ‘ON’ the EMI modulation if EMI becomes an issue*. The PL671-00’s spread spectrum modulation greatly reduces the fundamental and harmonic frequencies’ peak magnitude, reducing the system level electromagnetic radiation by as much as 20dB. *Note: Requires 6-pad package PAD CONFIGURATION DIE SPECIFICATION 0.80mm XIN Parameter XOUT OE^, PDB^, CLK1 CSEL1^ GND Value Chip size 1.40mm x 0.80mm VDD Chip thickness 150 to 250µm CSEL0^, CLK2 PAD size 90µm x 90 µm CLK0 Chip base GND level Note: ^ denotes internal pull up resistor BLOCK DIAGRAM XIN Xtal Osc XOUT PDB CLK[0:2] CSEL[0:1] SST On/Off Programming Logic Modulation Magnitude* * Optional Pre-defined Modulation Magnitude Control Programmable Function SST Modulation FREF R-Counter 9-bits M-Counter 11-bits ÷8 ÷8 Phase Detector Charge Pump Loop Filter VCO FVCO = FREF * (M/R) P-Counter 6-bits Odd/Even FOUT = FVCO / P CLK1/PDB CLK0 /1, /2 /1, /2, /4 CLK2/CSEL0 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/22/08 Page 1 PicoEMI T M Programmable Spread Spectrum Clock PAD ASSIGNMENT AND DESCRIPTION Name Pad Assignment* Type Description 1286 I Crystal input pad. This pin can be programmed to function as OE (input), PDB (input) or CLK1 (output). Output Enable (OE) input. Enables and disables the clock output buffer. Internal pull up resistor. Power Down (PDB) input. Turns off the oscillator, PLL and the output when pulled to logic “0”. Internal pull up resistor. 930 I/O Pad # X (µm) Y (µm) XIN 1 124 OE, PDB, CLK1 2 87 Pin State OE PDB 0 Disable CLK Power Down Mode 1 (default) Normal mode Normal mode Clock1 (CLK1) output. This optional clock can be set to F REF , F REF /2 or F OUT (Programmable PLL output). CSEL1 3 87 628 I Optional programming of CSEL0 & CSEL1 input pins allow switching between ‘4’ pre-defined configurations. Internal pull up resistor. GND 4 87 275 P GND connection CLK0 5 714 380 O Programmable Clock Output CSEL0, CLK2 6 714 677 I This pin can be programmed to function as CSEL0 (input) or CLK2 (output). CSEL0 input. Optional programming of CSEL0 & CSEL1 input pins allow switching between ‘4’ pre-defined configurations. Internal pull up resistor. CLK2 output. This optional clock can be set to F REF , CLK0, CLK0/2 or CLK0/4. VDD 7 714 916 P VDD connection XOUT 8 677 1286 O Crystal output pad. See Crystal Specifications on page 6. * Note: The X/Y coordinates indicate pad centers referenced from the lower left corner of the die. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/22/08 Page 2 PicoEMI T M Programmable Spread Spectrum Clock KEY PROGRAMMING PARAMETERS CLK[ 0:2 ] Output Frequency SST Modulation Magnitude (Spread Percentage) F OUT = F REF * M / (R * P) 16 programmable modulation where M =11 bit magnitudes to choose from: R = 9 bit P = 6 bit Center Spread: ±0.125% to CLK0= F REF , F REF /2 or F VCO /P* ±2.0% in ±0.125% steps CLK1= F REF , F REF /2 or F VCO /P* Down Spread: -0.25% to -4.0% in 0.25% steps CLK2= F REF , CLK0, CLK0/2 or CLK0/4 SST On/Off Control. Programmable Input/Output Programmable I/O’s include: PDB – input Optional CSEL0, CSEL1 (Pre-defined configurations) – input SST On/Off control – input CLK[0:2] - output Output Drive Strength Three optional drive strengths to choose from: Low: 4mA Std: 8mA (default) High: 16mA * ‘P’ is a 6-bit Odd/Even divider. FUNCTIONAL DESCRIPTION PL671-00 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-power Spread Spectrum modulation applications. The PL671-00 accepts a fundamental input crystal of 10MHz to 40MHz or a reference clock input of 1MHz to 200MHz and is capable of producing three SST modulated outputs up to 200MHz. This flexible design allows the PL671-00 to deliver any PLL generated frequency, F REF (Crystal or Ref Clk) frequency or F REF /2 to CLK0, CLK1 and/or CLK2. Alternate configuration using CSEL0 & CSEL1 allows the device to choose from up to 4 different pre-defined settings providing a range of spread settings, drive levels and outputs to choose from. Some of the design features of the PL671-00 are mentioned below. PLL Programming The PLL in the PL671-00 is fully programmable. The PLL is equipped with a 9-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 6-bit post VCO Odd/Even divider (PCounter). The output frequency is determined by the following formula [F OUT = (F REF * M)/(R*P). Modulation Magnitude and Type The PL671-00 provides the following programmable capabilities for Modulation Type and Modulation Magnitude (Spread Percentage): Modulation Type Modulation Magnitude Programming Steps Center Spread ±0.125% thru ±2.00% ±0.125% Down Spread -0.25% thru -4.00% 0.25% Clock Outputs (CLK[0:2]) CLK0 is the main clock output. The PL671-00 can also be programmed with additional clock outputs CLK1 and CLK2. The outputs of CLK[0:2] can be configured as described below: CLK0= FREF, FREF/2 or FVCO/P* CLK1= FREF, FREF/2 or FVCO/P* CLK2= FREF, CLK0, CLK0/2 or CLK0/4 Where F REF - Reference (Crystal) Frequency FOUT = FREF * M / (R * P) The output drive level of each output can be independently programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The output frequency can be programmed up to 200MHz at 3.3V (166MHz at 2.5V). Modulation Rate The PL671-00 modulation rate is defined as F REF (Crystal Frequency) divided by 8 times the R-counter, i.e. Modulation Rate = (F REF / 8R). The rate can be changed by choosing alternate R-Counter settings. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/22/08 Page 3 PicoEMI T M Programmable Spread Spectrum Clock Output Enable Control (OE) When activated (logic ‘0’), OE disables the clock output buffer putting it into a Hi-Z state. The PDB input incorporates a pull up resistor giving a default condition of logic “1”. Power-Down Control (PDB) When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10µA of power. The PDB input incorporates a pull up resistor giving a default condition of logic “1”. Configuration Selectors (CSEL[0:1]) The PL671-00 has the capability to be programmed with 4 distinct configurations and to toggle “On the Fly” between these configurations using the selector pads CSEL0 and CSEL1. CSEL0 and CSEL1 both incorporate a pull up resistor giving a default condition of logic “1”. When the CSEL0/CLK2 pin is programmed to be CLK2, CSEL0 is set to a default of Logic 1. This means that two programmable configurations are available to be selected “On the Fly” using CSEL1. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN MAX UNITS V DD -0.5 7 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V Supply Voltage Range 10 Data Retention @ 85C Storage Temperature TS Ambient Operating Temperature* Year -65 150 C -40 85 C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS CONDITIONS Crystal Input Frequency(XIN) Fundamental Crystal Output Frequency Settling Time Output Enable Time Output Rise Time Output Fall Time @ VDD =3.3V @ VDD =2.5V MIN TYP 10 MAX UNITS 40 MHz 200 1 166 At power-up (after VDD increases over 2.25V) OE Function; Ta=25º C, 15pF Load. Add one clock period to this measurement for a usable output. PDB Function; Ta=25º C, 15pF Load MHz 2 ms 10 ns 2 ms 15pF Load, 10/90% V DD , Standard Drive 2.0 3.0 15pF Load, 10/90% V DD , High Drive 1.2 1.7 15pF Load, 90/10% V DD , Standard Drive 1.7 2.5 15pF Load, 90/10% V DD , High Drive 1.2 1.7 ns ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/22/08 Page 4 PicoEMI T M Programmable Spread Spectrum Clock AC SPECIFICATIONS (Continued) PARAMETERS CONDITIONS MIN TYP MAX UNITS 45 50 55 % 100 ps MAX UNITS 27MHz, 3.3V, load=15pF, (PDB=1) 15 mA PDB=0 10 A 3.63 V 100 ms 0.4 V Duty Cycle At V DD /2 Cycle to Cycle Jitter* TCYC-CYC Over output frequency range @ 3.3V * Note: Jitter performance depends on the programming parameters. DC SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS MIN TYP Supply Current, Dynamic, with Loaded Outputs I DD Operating Voltage V DD Power Supply Ramp t PU Output Low Voltage V OL Time for V DD to reach 90% V DD . Power ramp must be monotonic. I OL = +4mA (Std Drive) Output High Voltage V OH I OH = -4mA (Std Drive) V DD - 0.4 V Output Current, Low Drive I OSD V OL = 0.4V, V OH = 2.4V 4 mA Output Current, Std Drive I OSD V OL = 0.4V, V OH = 2.4V 8 mA Output Current, High Drive I OHD V OL = 0.4V, V OH = 2.4V 16 mA 2.25 CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating SYMBOL MIN F XIN 10 C L (xtal) TYP 40 MHz pF 100 Operating Drive Level Low C0 UNITS 14 Maximum Sustainable Drive Level High C0 MAX W 30 Shunt Capacitance ESR Max Shunt Capacitance ESR Max W C0 5.5 pF ESR 50 Ω C0 2.5 pF ESR 80 Ω 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/22/08 Page 5 PicoEMI T M Programmable Spread Spectrum Clock ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The ordering number for this device is a combination of the following: Part number, Package type and Operating temperature range Part Number Package Type D=Die W=Wafer Temperature C=Commercial (0°C to 70°C) Part / Order Number Marking Package Option PL671-00DC PL671-00DC Die (Waffle pack) PL671-00WC PL671-00WC Wafer PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/22/08 Page 6