(Preliminary) PL686-05 Low Phase Noise, LVPECL XO (for 70MHz to 170MHz Fundamental Crystals) • • • • DESCRIPTION The PL686-05 is a non-multiplier XO IC specifically designed for fundamental mode crystals from 70MHz to 170MHz. The phase noise performance, with <50fs phase jitter, makes this an ideal solution for all high end clocking applications such as SONET, WiMax, CPRI, OBSAI, Fiber Channel, and any application where performance and quality are required. 0.952mm XIN 7 XOUT 8 QB • • Advanced non multiplier XO Design for High Performance Crystal Oscillators Input/Output Range: 70MHz to 170MHz Ultra Low Phase Noise: -163dBc @10MHz at 156.25MHz Ultra Low Phase Jitter: <50fs RMS Complementary LVPECL Outputs Power Supply: 3.3V ±10% Available in Die or Wafer Form VDD • DIE CONFIGURATION 0.952mm FEATURES 6 5 Q 4 1 DNC 3 VSS 2 OE Die ID (0,0) OUTPUT ENABLE LOGIC DIE SPECIFICATIONS Name Value OE State (Pad 4) Output Buffers State Size 952 micron x 952 micron 0 Outputs Tri-Stated Reverse side GND 1 (Default) Outputs Enabled Pad dimensions 80 micron x 80 micron Thickness 8 mil * Internal 60KΩ pull-up resistor BLOCK DIAGRAM OE XIN XOUT Xtal Osc Q QB 2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 2/9/12 Page 1 (Preliminary) PL686-05 Low Phase Noise, LVPECL XO (for 70MHz to 170MHz Fundamental Crystals) PAD ASSIGNMENT Pad # Name X (µ µ m)* Y (µ µ m)* Description 1 DNC -194 -365 Do Not Connect 2 XOUT -372 -190 Crystal output connection 3 XIN -372 158 Crystal input connection 4 VDD -117 329 V DD connection 5 QB 140 315 Complementary LVPECL output 6 Q 315 75 LVPECL output 7 VSS 373 -127 GND connection 8 OE 373 -373 Output enable pin. Internal pull up resistor. * Note: Referenced to center of the die. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage SYMBOL MIN. V DD MAX. UNITS 4.6 V Input Voltage, DC VI V SS -0.5 V DD +0.5 V Output Voltage, DC VO V SS -0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature TA -40 85 °C HBM ESD Protection 2,000 V Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 2/9/12 Page 2 (Preliminary) PL686-05 Low Phase Noise, LVPECL XO (for 70MHz to 170MHz Fundamental Crystals) 2. Crystal Specifications PARAMETERS SYMBOL Crystal Resonator Frequency F XIN Crystal Loading Rating CONDITIONS MIN. Fundamental Mode, AT cut 70 C L (xtal) Shunt Capacitance TYP. UNITS 170 MHz 8 RE pF 2.0 pF C 0 ≤ 2.0pF, up to 135MHz 30 Ω C 0 ≤ 2.0pF, up to 160MHz 20 Ω C 0 ≤ 1.5pF, up to 170MHz 20 Ω MAX. UNITS 65 mA C0 Recommended ESR MAX. 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. Standard LVPECL Loading Supply Current I DD Operating Voltage V DD (See LVPECL Levels Test Circuit, page 4) @ V DD – 1.3V Output Clock Duty Cycle (See LVPECL Transition Time Waveform, page 4) 2.97 3.3 3.63 V 45 50 55 % Short Circuit Current mA ±50 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. 2.5 Period Jitter pk-to-pk At 156.25MHz, with capacitive decoupling between V DD and GND. Over 10,000 cycles Integrated Jitter RMS at 156.25MHz Integrated 12 kHz to 20 MHz 47 Period Jitter RMS MAX. UNITS ps 20 fs 5. Phase Noise Specifications PARAMETERS Phase Noise, relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz @1MHz @10MHz 156.25MHz -67 -97 -125 -149 -158 -162 -163 UNITS dBc/Hz 2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 2/9/12 Page 3 (Preliminary) PL686-05 Low Phase Noise, LVPECL XO (for 70MHz to 170MHz Fundamental Crystals) 6. LVPECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output High Voltage V OH V DD – 1.025 V DD – 0.950 V DD – 0.880 V Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) V DD – 1.810 V DD – 1.700 V DD – 1.620 V 7. LVPECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS Clock Rise Time tr Clock Fall Time tf MAX. UNITS @20/80% of output waveform 300 ps @80/20% of output waveform 300 ps LVPECL Levels Test Circuit MIN. TYP. LVPECL Transistion Time Waveform DUTY CYCLE OUT VDD 50? 2.0V 45 - 55% 55 - 45% OUT 80% 50% 50? 20% OUT OUT tR tF 2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 2/9/12 Page 4 (Preliminary) PL686-05 Low Phase Noise, LVPECL XO (for 70MHz to 170MHz Fundamental Crystals) ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Order Number Packaging PL686-05DC Die – Waffle Pack PL686-05WC Wafer PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Road, San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 2/9/12 Page 5