TMC6130 DATASHEET

POWER DRIVER FOR STEPPER MOTORS
INTEGRATED CIRCUITS
TMC6130 DATASHEET
Cost-effective high-current BLDC motor driver with state-of-the-art feature set.
Fastest settling time and built-in EEPROM for extensive configuration.
APPLICATIONS
Battery operated equipment
Handcraft gear
Professional healthcare
Fail-safe applications
Low-torque control applications
BLDC sine wave applications
Positioning Actuators
Factory Automation
Pumps and Valves
CNC Machines
FEATURES
AND
BENEFITS
Level Shifting: µC PWM outputs / 6 or 3 ext. N-FET half-bridges
100% PWM Operation
Low Offset, Low Drift, Fast Current Sense Amplifier with
configurable input range
Operating Range VM = [4.5, 28]V, 32V abs. max
Fault Interrupt & Feedback to microcontroller
Fastest settling time and minimum noise
Diagnostics: overcurrent, overtemperature, undervoltage
Configurable communication interface for diagnostics feedback
Drain-Source Voltage / Gate-Source Voltage external FET
monitoring for short circuit protection
Sleep Mode with low quiescent current (<30µA)
Compatible with 3V and 5V microcontrollers
Charge-Pump provides NFET reverse polarity drive
Small Size: QFN 5x5mm package, 32 pins
BLOCK DIAGRAM
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
DESCRIPTION
The TMC6130 is a high-current motor driver for
compact and energy efficient BLDC solutions.
It is designed to drive N-type FET 3-phase
motor control applications and contains all
power and analog circuitry required for a high
performance system. The built-in EEPROM
allows extensive configurability without the
need for external resistors and SPI interface
programming. This reduces the pin count to
only 32. All output voltages are monitored and
controlled. The device comprises a current
shunt amplifier with a high gain bandwidth
(GBW), offering a fast settling time with low
noise. A combination of bootstrap and charge
pump enables driving 6 (or 3) NFETs, with gate
charges up to 400nC/NFET with a minimum of
device self-heating. Further, the IC reset level
below 4.5V allows also for low-voltage
operation.
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
2
APPLICATION EXAMPLES: HIGH POWER – FASTEST SETTLING TIME
The TMC6130 3-phase motor pre-driver scores with a very fast settling time, high reliability, and broad
diagnostic and safety features. It can be used within a large operating range from battery systems on up to
24V DC. This versatility covers a wide spectrum of applications and motor sizes, all while keeping costs down.
Several safe operating features are integrated, including diagnostics related to all output voltages, power on
reset, and short circuit protection. Diagnostics feedback is communicated to the microcontroller via a
bidirectional error interface. Finally, this BLDC driver chip features a low side shunt amplifier with large gain
bandwidth (GBW), ideal for torque control applications requiring very fast settling time and minimum noise.
Extensive support at the chip, board, and software levels enables rapid design cycles and fast time-to-market
with competitive products.
PWM
High-Level
Interface
TMC6130
µC
Error
Position
TMC6130 EVALUATION BOARD
Layout with MOSFET power module (B6-bridge)
This evaluation board is a development
platform for applications based on the
TMC6130 three phase BLDC motor driver
chip. Supply voltages are 4.5… 28V DC
(max. 32V). The board features an
embedded microcontroller with USB
and RS232 (TTL level) interfaces for
communication. The board offers test
points for all pins of the TMC6130.
For positioning, three digital hall
sensors can be connected as well as an
ABN
encoder.
Using
the
IOs,
potentiometers and switches can be
attached.
TRINAMICs TMCM-BLDC software tool
(running under Windows) enables
access to all functions of the TMC6130
from a PC.
ORDER CODES
Order code
TMC6130-LA
TMC6130-EVAL
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Description
BLDC 3-phase driver, QFN32
Evaluation board for TMC6130.
Size [mm2]
5x5
80 x 115
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
3
TABLE OF CONTENTS
1
PRINCIPLES OF OPERATION .................................................................................................................................... 4
1.1
1.2
2
KEY CONCEPTS .......................................................................................................................................................... 4
APPLICATION CIRCUITS ............................................................................................................................................ 5
PIN ASSIGNMENTS ...................................................................................................................................................... 8
2.1
2.2
3
PACKAGE OUTLINE .................................................................................................................................................... 8
SIGNAL DESCRIPTIONS ............................................................................................................................................. 8
CURRENTS AND CURRENT CONTROL ................................................................................................................... 10
3.1
3.2
3.3
4
SUPPLY SYSTEMS .................................................................................................................................................... 10
100% PWM WITH BOOTSTRAP ............................................................................................................................. 11
CURRENT CONSUMPTION IN SLEEP MODE ............................................................................................................... 11
DIAGNOSTICS ............................................................................................................................................................. 13
4.1
4.2
5
ERROR INTERFACE ................................................................................................................................................. 13
HARDWARE PROTECTION ........................................................................................................................................ 15
EEPROM DEFAULT CONFIGURATION.................................................................................................................... 16
5.1
6
BASIC INFORMATION FOR SPI COMMUNICATION ................................................................................................... 17
SENSE AMPLIFIER ...................................................................................................................................................... 18
6.1
7
SENSE AMPLIFIER CURRENT RANGES: EXAMPLES FOR 1MΩ SHUNT ......................................................................... 19
FET DRIVER IMPLEMENTATION ............................................................................................................................. 20
7.1
7.2
NORMAL OPERATION .............................................................................................................................................. 20
FET DRIVER DURING SLEEP MODE ......................................................................................................................... 20
8
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................ 21
9
GENERAL ELECTRICAL SPECIFICATIONS............................................................................................................. 22
9.1
10
OPERATIONAL RANGE (UNLESS OTHERWISE SPECIFIED) .......................................................................................... 22
PACKAGE MECHANICAL DATA ............................................................................................................................... 29
10.1
10.2
QFN32 DIMENSIONAL DRAWINGS ......................................................................................................................... 29
PACKAGE CODE ....................................................................................................................................................... 29
11
DISCLAIMER ................................................................................................................................................................ 30
12
ESD SENSITIVE DEVICE ........................................................................................................................................... 30
13
TABLE OF FIGURES .................................................................................................................................................... 31
14
REVISION HISTORY .................................................................................................................................................. 32
15
REFERENCES ................................................................................................................................................................. 32
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
1
4
Principles of Operation
VBAT
Cboost
VM
VCC
VCP_SW
3.3V
BHx
Charge
Pump
12V
Regulator
Power on
reset
RC
Oscillator
To Drivers
BLx
VCP
Diagnostics
VCP_BOOST OV
VCP_REG
Diagnostics
VCP_REG OV
Diagnostics
VCP_REG UV
Band Gap
Diagnostics
VGS UV
Driver
Logic
Diagnostics
VDST OV
VMON
ENABLE
3
LS-Drive
LS-Drive
High
Side
EEPROM
SPI
LS-Drive
LS-Drive
Low
Side
VCPx
3
HSx
3
BMx
3
LSx
3
Diagnostics
VDSB OV
ERROR
Diagnostics &
Error Feedback
VMON
Diagn. Comp.
RS+
Current
Measurement
Overvoltage
Undervoltage
Overtemperature
CURRENT
GNDA
VREF
Rshunt
RS-
GNDP
Figure 1.1 Block diagram and principle operation circuit
1.1 Key Concepts
The TMC6130 BLDC motor pre-driver implements advanced features which contribute toward energy
efficiency, high precision, high reliability, smooth motion, and cool operation in industrial BLDC motor
applications.
Configuration
All configurations are done. The TMC6130 is equipped with a programmed EEPROM
in order to simplify the design-in. In almost all cases the default values will fit.
Nevertheless, special configurations are possible, if necessary.
Interfacing
The TMC6130 communicates with the microcontroller using the ERROR input/output
for diagnostic feedback. During stand still, the SPI interface on the pre-driver can
be used for configuration purposes. Further, it is possible to communicate via bit
banging.
Fast Settling Time The TMC6130 offers an extremely short settling time. The shunt amplifier has a
high gain bandwidth (GBW) to reach a fast settling time with minimum noise.
Voltage
The TMC6130 can be used within the range of 4.5V to 28V DC.
Boost Current
For quick motor reaction on a target setting, a higher boost current can be used.
This way, the time interval for acceleration and deceleration can be shortened.
Sleep Mode
In sleep mode, the current consumption can be reduced to or below 30µA.
TRINAMIC motor drivers also offer safeguards to detect/protect from shorted outputs, overtemperature,
overvoltage, and undervoltage conditions.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
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1.2 Application Circuits
+12V
Optional
reserve
polarity
diode
Optional charge pump
circuit for applications
below 12V operation
VM
3/5 V
Regulator
VCP_SW VCP VCP_REG
VMON
VCC
TMC6130
VCPx
HS1
Bridge_en
Diagn_I/O
ENABLE
HS2
ERROR
HS3
BM1
BM2
I/ 0 Port
3
BHx
3
BLx
BM3
LS1
LS2
ADC_ Vref
VREF
ADC input
CUR
LS3
RS+
*17.2
GNDA
RS-
S
GNDP
N
BLDC Motor
Figure 1.2 Application example for +12V DC
+24V
VM VCP_SW VCP VCP_REG
3/5 V
Regulator
VMON
VCC
TMC6130
R2R
R2R
VCPx
HS1
Bridge_en
ENABLE
HS2
Diagn_I/O
ERROR
HS3
BM1
R2R
BM2
3
I/ 0 Port
3
R2R
BHx
BM3
BLx
R2R
LS1
LS2
ADC_ Vref
VREF
ADC input
CUR
GNDA
LS3
RS+
*17.2
RSGNDP
S
N
BLDC Motor
Figure 1.3 Application example for +24V DC
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R2R
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
6
1.2.1 Ground Connections
Optional reserve polarity diode
VMON
TMC6130
VM
CPU
VCP
(regulated to GND)
VCP_REG
VCC
RS+
RSGNDA GNDP
Analog ground
Controller ground
Figure 1.4 Ground connections
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Power ground
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
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1.2.2 Pin Internal Connections
SUPPLY CONNECTIONS
VMON
VM
VCP_SW
55V
GNDP
VCC
VCP_REG
VCP
55V
18.5V
8V
GNDP
GNDP
GNDP
Figure 1.5 Supply connectinons
GATE DRIVER CONNECTIONS
VCPx
VCP_REG
55V
HSx
18.5V
BMx
LSx
GNDP
GNDP
10V
Figure 1.6 Gate driver connections
DIGITAL IO CONNECTIONS
VCC
VCC
VCC
ENABLE
ERROR
BHx
BLx
18.5V
GNDP
GNDP
GNDP
GNDP
Figure 1.7 Digital IO connections
AMPLIFIER CONNECTIONS
VCC
VCC
RSRS+
Figure 1.8 Amplifier connections
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VCC
VCC
CUR
VREF
GNDA
GNDP
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
2
Pin Assignments
GNDA
VMON
7
14
15
16
BM3
HS3
VCP3
BM1
13
VCP1
VCP2
12
HS1
11
HS2
8
10
24
BH2
6
9
23
BH1
TMC6130-LA
VM
VCP_SW
22
BH3
25
GNDP
21
VCC
26
LS1
20
VREF
27
5
BM2
28
LS3
19
4
ENABLE
29
LS2
18
3
BL2
ERROR
30
VCP_REG
17
BL1
BL3
31
2
CURRENT
32
1
RS+
RS-
2.1 Package Outline
VCP
Top view
Figure 2.1 TMC6130 pin assignments
2.2 Signal Descriptions
Name
RS+
CURRENT
BL1
BL2
BL3
ERROR
ENABLE
BM2
HS2
VCP2
BM1
HS1
VCP1
BM3
HS3
VCP3
VCP
VCP_REG
LS2
LS3
LS1
GNDP
VCP_SW
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
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Type
Analog
Analog
Digital
Digital
Digital
IO
IO
Phase
Output
Supply
Phase
Output
Supply
Phase
Output
Supply
Analog
Analog
Output
Output
Output
Ground
Analog
Function
Current sensor input (positive)
Current sensor output; diagnostic output in case of fault
PWM input for low-side bridge n-FET1
PWM input for low-side bridge n-FET2
PWM input for low-side bridge n-FET3
Diagnostic feedback IO
Enable input
Motor phase 2
PWM output to high-side n-FET2 gate
Charge pump supply for high-side n-FET2
Motor phase 1
PWM output to high side n-FET1 gate
Charge pump supply for high-side n-FET1
Motor phase 3
PWM output to high side n-FET3 gate
Charge pump supply for high-side n-FET3
Charge pump generated supply, unregulated
Regulated output from charge pump to drive n-FET gates
PWM output to low-side n-FET2 gate
PWM output to low-side n-FET3 gate
PWM output to low-side n-FET1 gate
Driver ground
Output of charge pump to boost low battery
8
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
Name
VM
VMON
GNDA
BH2
BH1
BH3
VCC
Number
24
25
26
27
28
29
30
Type
Supply
Input
Ground
Digital
Digital
Digital
Supply
VREF
RS-
31
32
Analog
Analog
Function
Power supply input
Supply for 3 high-side n-FETs to monitor drain source voltage VDS
Analog ground
PWM input for high-side n-FET2
PWM input for high-side n-FET1
PWM input for high-side n-FET3
The input voltage on VCC is used to drive the digital IO’s, and is
used to supply the shunt amplifier.
Sleep mode control: VCC = 0V puts the pre-driver in sleep mode.
Reference voltage input for current sense
Current sensor input (negative)
Table 2.1 Pin definitions and descriptions
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9
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
3
10
Currents and Current Control
3.1 Supply Systems
The current for operation of the system is supplied via VM and VCC. VCC supplies the IOs, and the amplifier.
In case VCC is supplied with a limited output impedance (for instance from a microcontroller IO), the
performance of the amplifier may be affected. VM supplies the internal operation and the charge pump.
There are two possibilities to connect the boost current capacitor to the TMC6130. For charge pump
mode 0 (default setting), connect it to VCP as shown in Figure 3.1.
CBOOST
IDIODE_CP
ITOT
IDIODE_CP
ITOT
+VBAT
+VBAT
C M IM
ILOAD
CCP
VM
VCP_SW
C M IM
CBOOST
VCP
VM
IM_CP
VCP_SW
ILOAD
VCP
IM_CP
IM_INT
ICC
VCC
CCP
VREG
VCP_REG
+3.3V
VCPx
SLEEP
BHx
IM_INT
VREG
VCP_REG
+3.3V
ICC
VCC
VCPx
SLEEP
BHx
HSx
BLx
ENABLE
HSx
BLx
ENABLE
BMx
ERROR
BMx
ERROR
LSx
CURRENT
*17.2
Charge Pump Mode = 0
LSx
CURRENT
*17.2
Charge Pump Mode = 1
Figure 3.1 Power supply systems: CPMODE = 0 and CPMODE = 1
STANDARD OPERATION: CHARGE PUMP MODE = 0
The standard operation of the charge pump is to ensure sufficient gate voltage to the bootstrap
capacitors in case of low voltage conditions. VBOOST is regulated compared to GND level. The charge
pump will not be switching when VM > VREG+2*VF with VF = forward voltage of charge pump diodes.
CHARGE PUMP MODE = 1
(has to be programmed and stored in EEPROM via SPI)
Alternatively, the charge pump can regulate VBOOST compared to VM. In this case the CBOOST capacitor
should be connected to VM to ensure any supply variations are coupled to the VBOOST level. The
disadvantage is an additional amount of dissipation inside the pre-driver to regulate VREG.
The default configuration is stored in the integrated EEPROM. In case CPMODE1 is desired, it is necessary
to change EEPROM configuration bits (using the SPI interface or via bit banging).
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
11
3.2 100% PWM with Bootstrap
A current is drawn from the VCP_SW pin to the phase pins. This current will discharge the gate voltage
on top of any external pull down gate resistance.
CALCULATION EXAMPLE 1
CALCULATION EXAMPLE 2
Parameter
Value
Unit
Parameter
Value
Unit
bootstrap
330
nF
bootstrap
100
nF
VCP_reg
12
V
VCP_reg
12
V
Qbootstr
3960
nC
Qbootstr
1200
nC
QFET
200
nC
QFET
120
nC
VGS_initial
11.4
V
VGS_initial
10.9
V
Rcp_leak
0.75
MΩ
Leakage
15
µA
Leakage
15
µA
On time
60
ms
On time
10
ms
Qleak
914
nC
Qleak
152
nC
VGS_end
9.4
V
VGS_end
9.8
V
VGS_drop
2.06
V
VGS_drop
1.13
V
This gate leakage will limit the maximum state time during which 100% PWM can be applied.
3.3 Current Consumption in Sleep Mode
Sleep mode is activated when the supply input VCC is pulled below VCC_SLEEP level. In sleep mode, the
current consumption is reduced to ISSLEEP.
Pin
Current consumption in Sleep Mode
Input/Output
BHx
BLx
ENABLE
VREF
ERROR
CURRENT
VCP_REG
VCP
VCP_SW
VCPx
Input pins, supplied from VCC
GND
Supplied from VCC
Supply regulator disabled
Externally connected to supply.
Charge pump disabled.
Any charge that remains after VCP_REG is disabled will leak to
ground.
VM > 4.5V
In sleep mode, gate-discharge-resistors (RSGD) between HSx and
BMx are activated.
VM > 4.5V
In sleep mode, gate-discharge-resistors (RSGD) between LSx and
DGND are activated.
GND
GND
~VBAT
GND
GND
HSx
BMx
LSx
GND
GND
ATTENTION!
In case input pins are externally pulled high while VCC is low, current will flow into VCC via internal
protection diodes. This condition is not allowed!
When VCC is pulled low, also ERROR will go low. This should not be interpreted as a diagnostic
interrupt.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
STATES
Name
RS+
CUR
BL1
BL2
BL3
ERROR
ENABLE
BM2
HS2
VCP2
BM1
HS1
VCP1
BM3
HS3
VCP3
VCP
VCP_REG
LS2
LS3
LS1
GNDP
VCP_SW
VM
VMON
GNDA
BH2
BH1
BH3
VCC
VREF
RS-
IN
SLEEP MODE
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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Type
Analog
Analog
Digital
Digital
Digital
IO
IO
Phase
Output
Supply
Phase
Output
Supply
Phase
Output
Supply
Analog
Analog
Output
Output
Output
Ground
Analog
Supply
Input
Ground
Digital
Digital
Digital
Supply
Analog
Analog
State in Sleep Mode
GND
GND (tied to VCC)
GND (tied to VCC)
GND (tied to VCC)
GND (tied to VCC)
GND (tied to VCC)
GND (tied to VCC)
Connected via diode to GATE2
Internal pull down (RSGD) to GND
Any present charge leaks to GND
Connected via Diode to GATE1
Internal pull down (RSGD) to GND
Any present charge leaks to GND
Connected via Diode to GATE3
Internal pull down (RSGD) to GND
Any present charge leaks to GND
Connected via charge pump diodes to VBAT
GND
Internal pull down (RSGD) to GND
Internal pull down (RSGD) to GND
Internal pull down (RSGD) to GND
Driver ground
GND
Power supply input
Connected to supply
Analog ground
GND (tied to VCC)
GND (tied to VCC)
GND (tied to VCC)
Externally pulled low
GND
GND
12
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
4
13
Diagnostics
4.1 ERROR Interface
ERROR is a serial interface that feeds back detailed diagnostics information to the microcontroller. Two
modes for supplying diagnostic feedback can be used (configured in EEPROM). The default configuration
for the TMC6130 is PWM_SPEED = 1.
PWM_SPEED = 0
Slow response diagnostic mode
PWM period TERROR ≈ 64µs for frequency FERROR_S
PWM_SPEED = 1
Fast response diagnostic mode
PWM period TERROR ≈ 10µs for frequency FERROR_F
In these modes detailed diagnostic information is provided in the form of a PWM duty cycle. Each error
corresponds to one duty cycle. The duty cycle is transmitted until the microcontroller acknowledges the
reception of the duty cycle. The microcontroller acknowledges by pulling the ERROR line low for a period
tACK > tERROR.
2
1
MCU
T
1
3
3
ERROR 2
ERROR 1
T
2
2
T
T
T
Tack
1
3
EOF
ERROR 3
T
Tack
T
T
T
Tack
T
T
Tack
1 MCU pulls ERROR low.
2 TMC6130 detects acknowledge on falling edge.
3 MCU releases ERROR line.
Figure 4.1 ERROR handshake protocol
At each falling edge the TMC6130 checks the actual voltage on the ERROR line to detect an
acknowledgement. When an acknowledgement is detected the duty cycle value is changed to the
corresponding duty cycle value of the highest priority next error that has not yet been transmitted. This
sequence of capturing duty cycle and acknowledging continues until the end of the frame (EOF) duty
cycle has been received. By acknowledging the EOF duty cycle all error latches are reset and the ERROR
line goes high again until a new error occurs.
ATTENTION
-
It is possible that a lower priority error is transmitted before a higher priority error because the
higher priority error occurred after the start of transmission of the lower priority error.
When VCC is pulled low to put the TMC6130 into sleep mode, ERROR will go low as well. As soon
as VCC goes high, ERROR will go high as well and remains high: no EOF is required in this case.
As long as the regulated voltages on VCP and VCP_REG have not been achieved, ERROR may
immediately start to go in diagnostic mode. This implies the microcontroller has to acknowledge
these errors until the undervoltage conditions have been resolved. As soon as ERROR no longer
enters diagnostic mode, the pre-driver is ready for operation.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
ACKNOWLEDGE
ON
14
ERROR
For the CPU to acknowledge ERROR it should be able to keep the line low while ERROR is pulling the
line high.
VCC
Microcontroller
VCC
TMC6130
<5mA
ERROR
<5mA
CLOAD < 100pF
Figure 4.2 ERROR output
OVERVIEW
Priority
DIAGNOSTIC ERRORS
16
Input Error
Code
ERROR_EOF
Duty Cycle
[%]
93.5
Debounce
Time
n/a
End of frame
9
EEP_ERR
55
n/a
EEPROM DED error
8
VCC_UV
8µs
7
VM_OV
49.5
44
6
VM_UV
38.5
8µs
VCC undervoltage
VM overvoltage.
This event cannot be masked!
VM undervoltage
5
OVT
33
2µs
Overtemperature
4
VCP_REG_UV
27.5
16µs
3
VGS_UV
22
2µs
2
VCP_UV
16.5
16µs
1
VCP_REG_OV
11
2µs
0
VDS_ERR
5.5
2µs
VCP_REG undervoltage
Gate-source undervoltage
This event can be masked by setting
VGS_UV_COMP_EN=0
VCP undervoltage
Voltage regulator overvoltage
This event can be masked by setting
VREG_OV_BF_EN=0
Drain-source voltage Error = VDS_T1 || VDS_T2 ||
VDS_T3 || VDS_B1 || VDS_B2 || VDS_B3
Can be Masked by VDS_COMP_EN.
To avoid erroneous triggering due to switching
there is a programmable blanking time on top
of the debounce time: VDS_BLANKTIME[1:0].
2µs
Description
NOTES
- In case of multiple errors at the same time, priority is defined: 0 is highest priority, 16 is lowest
priority.
- Duty cycle is transmitting with 5 bits resolution.
- Since the rise and fall times are matched, the resulting error is depending on the input
comparator level of the microcontroller. If the comparator level is at VCC/2, there is no error. In
any other case there is a systematic error which can be taken into account.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
15
4.2 Hardware Protection
Hardware protection refers to the capability of the microcontroller to turn off the TMC6130 pre-driver
without intervention in case of error condition. All gate voltages have to be pulled low to Z-state. An
overvoltage condition on VM will always switch off the pre-driver, in order to protect it. This safety
feature cannot be masked.
4.2.1 VDS Overvoltage
The reaction of the pre-driver on VDS (drain source voltage) overvoltage events can be configured in
EEPROM with bridge feedback (BF) bits.
Per default configuration, VDS_COMP_EN and VDS_BF_EN are set to 1. Thus, in case of VDS overvoltage,
ERROR reports error and the pre-driver is enabled.
For any other EEPROM configuration it is necessary to use the SPI interface or to communicate with the
microcontroller via bit banging. Note, that in most cases it is not necessary to change EEPROM settings.
Therefore, information about programming the EEPROM via SPI is subject of an application note and
not mentioned here.
VDS_COMP_EN
VDS_BF_EN
0
-
1
1
0
1
Reaction
Any possible drain source (VDS) overvoltage events are
neglected: no reaction on ERROR line. Pre-driver remains active.
ERROR reports error and pre-driver remains active.
ERROR reports error and pre-driver is disabled.
4.2.2 VCP_REG Overvoltage
The reaction of the pre-driver on VCP_REG overvoltage events can be configured in EEPROM with bridge
feedback (BF) bits.
The default configuration is VCP_REG_OV_BF_EN = 1. Thus, ERROR reports error and bridge driver is set
in tri-state if the error flag VCP_REG_OV is set.
For any other EEPROM configuration it is necessary to use the SPI interface or to communicate with the
microcontroller via bit banging. Note, that in most cases it is not necessary to change EEPROM settings.
Therefore, information about programming the EEPROM via SPI is subject of an application note and
not mentioned here.
VCP_REG_OV_BF_EN
0
1
Reaction
ERROR reports error.
ERROR reports error.
VCP_REG overvoltage bridge feedback is enabled:
1:
When error flag VCP_REG_OV = 1  bridge driver is set in tri-state.
0:
When error flag VCP_REG_OV = 1  no effect on bridge driver. This
setting can be used to mask VCP_REG_OV event.
4.2.3 Pre-driver Output State Summary
The table below shows all conditions due to which the pre-driver may be disabled.
Pre-driver disabled (Z-state)
As soon as an error condition appears for which
the hardware protection is activated.
VM_OV
VDS
VCP_REG_OV
As soon as VCC is low.
Pre-driver released again
As soon as the end of frame EOF has been
acknowledged.
As soon as ENABLE is low.
As soon as ENABLE is high.
www.trinamic.com
As soon as VCC is high.
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
5
16
EEPROM Default Configuration
A good pre-driver configuration is already done by TRINAMIC. The EEPROM features single error
correction and double error detection.
EEPROM PROGRAMMING
The EEPROM data can be programmed by the microcontroller via an SPI interface. In most cases it is
not necessary to change EEPROM settings. Therefore, information about programming the EEPROM via
SPI is subject of an application note and not mentioned here.
MEMORY MAP
SPI
Address
[2:0]
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CPMODE
Res.
PWM_SPEED
Res.
VDS_
COMP_EN
VGS_UV_CO
MP_EN
2
DEAD_TIME[2:0]
3
VDS_BLANK_TIME[1:0]
4
VREG_OV_B
F_EN
VDS_
BF_EN
5
SPI_EN
1
VDSMON[2:0]
Res.
Res.
CUR_GAIN[2:0]
0
Res.
EN_CP
Res.
Res.
Res.
Res.
Res.
Res.
EEPROM BITS
Bit name
Description
Default
DEAD_TIME[2:0]
Defines the DEAD TIME between the HS FET and LS FET of the same phase.
Default value: 1.0µs.
011
VDSMON[2:0]
Defines the detection threshold level of the Vds monitoring. Default value:
2V.
111
VDS_BLANK_TIME
[1:0]
Defines the duration of the Vds monitor blanking time after the ontransition of the FET. Default value: 3.0 µs
10
CUR_GAIN[2:0]
Defines the gain of the current sense amplifier.
Default value: *17.2
0: VBOOST voltage is regulated relative to ground
1: VBOOST voltage is regulated relative to VSUP.
011
SPI_EN
When set, the SPI block is enabled.
When reset, no SPI possible.
In SPI mode this value can only be programmed from 1 to 0, not from 0
to 1.
1
VCP_REG_OV_BF_EN
VCP_REG Overvoltage bridge feedback enable
1: When VCP_REG_OV = 1  Bridge driver is SET in tri-state
0: When VCP_REG_OV = 1  No effect on Bridge driver.
1
VDS_BF_EN
VDS bridge feedback enable
1: When VDS_ERR = 1  Bridge driver is SET in tri-state.
0: When VDS_ERR = 1  No effect on Bridge driver.
1
VDS_COMP_EN
1:
0:
1:
0:
1
Driver Configuration
CPMODE
0
IC Configuration
VGS_UV_COMP_EN
VDS comparator enabled
VDS comparator disabled
gate-source undervoltage comparator enabled
gate-source undervoltage comparator disabled
PWM_SPEED
1: PWM = FERROR_F
0: PWM = FERROR_S
EN_CP
1: boost charge pump enabled
0: boost charge pump disabled
Undefined
OUT_RESERVE_RG
www.trinamic.com
0
1
(ERROR PWM frequency slow ≈ 12.5KHz.)
0
0
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
17
5.1 Basic Information for SPI Communication
To communicate with the TMC6130 via SPI the motor has to be in standstill because of pin sharing.
When the chip is in SPI mode the EEPROM is programmable and readable via the SPI port.
The TMC6130 switches from normal mode to SPI mode if the following conditions are met:
-
EN = 0
ERROR:
⋅
Any pending errors have been acknowledged
⋅
All BHx = high
⋅
All BLx = low
⋅
A Low Level pulse is applied on ERROR between 256µs (2048 Tclk) and 512µs (4096 Tclk) )
The chip returns from SPI mode to normal mode when
-
EN = 1.
This means that any ongoing EEPROM writes will be completed and the EEPROM state machine will
copy all EEPROM contents into registers. Then the chip will return to normal mode. During this time the
ERROR pin will be kept low.
When the TMC6130 comes out of power ON reset, after leaving SPI mode and returning to normal
mode, the pre-driver will be blocked until the data have been copied to the registers. This assures that
all chip parameters are set correctly.
It only makes sense for the CPU to call for SPI if all errors are clear and acknowledged.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
6
18
Sense Amplifier
The sense amplifier offers very low input offset, and very fast settling times. The input range can be
adjusted by applying a suitable voltage on the VREF pin, typically as a resistor divider on VCC. For the
definition of VREF, the input offset, the current range, and the linear output range of the CURRENT pin
should all be taken into account.
Input signal:
VIN = VISP – VISN
Max. input offset:
VOFFSET_MAX = VIS_IO_MAX + TRANGE * VIS_IO_TDRIFT
TRANGE = over the full temperature range
VISENSE = (VIN +/-VOFFSET) * ISGAIN + VREF has to be in the range [VISENSE_MIN, VISENSE_MAX]
IMIN = [(VISENSE_MIN – VREF) / ISGAIN + VOFFSET] / RSHUNT
IMAX = [(VISENSE_MAX – VREF) / ISGAIN - VOFFSET ] / RSHUNT
Symbol
VIS_IO
VIS_IO_TDRIFT
ISGAIN
VISENSE_MIN
VISENSE_MAX
VREF
Parameter
Input offset voltage
Input offset voltage thermal drift
Closed loop gain
ISENSE output voltage range low
ISENSE output voltage range high
Reference voltage input
The table below shows the current input range for two resistive divider settings on VREF.
1.
2.
VREF = VCC/2 for a symmetrical input range
VREF = VCC/18 for a maximum current level, whilst ensuring it is possible to measure the input
offset before starting the motor (ISENSE_MIN > 0A).
For ease of calculation a max temperature offset drift of 1mV was added to the 5mV offset. From this
follows that the maximum input offset is 6mV.
VCC
Visensemin
Visensemax
div
VREF
Voffset
www.trinamic.com
3.3
3.3
3(**)
3(**)
5
5
4.5(**)
4.5(**)
0.02
3.28
2
1.65
0.006
0.02
3.28
18
0.18
0.02
2.98
2
1.50
0.02
2.98
18
0.17
0.02
4.98
2
2.50
0.02
4.98
18
0.28
0.02
4.48
2
2.25
0.02
4.48
18
0.25
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
19
6.1 Sense Amplifier Current Ranges: Examples for 1MΩ Shunt
ISENSE_MIN
-
Gain
DIV2
DIV18
DIV2
DIV18
DIV2
DIV18
DIV2
DIV18
8
-198
-14.4
-179
-12
-304
-26.2
-273
-23
10.3
-152
-9.9
-138
-8
-235
-19.0
-211
-16
13.3
-117
-6.3
-105
-5
-180
-13.4
-162
-11
17.2
-89
-3.5
-80
-3
-138
-9.0
-124
-7
22.2
-67
-1.4
-61
-0.6
-106
-5.6
-94
-4
28.7
-51
0.3(*)
-46
0.9(*)
-80
-3.0
-72
-2
37.0
-38
1.6(*)
-34
2.0(*)
-61
-1.0
-54
0
47.8
-28
2.6(*)
-25
3(*)
-46
0.6
-41
1
(*) Applying a GAIN of 28.7 or higher with DIV 18 for 3.3V does not allow the measure the input
offset
(**) examples taking a 10% supply variation into account.
ISENSE_MAX
Gain
DIV2
DIV18
DIV2
DIV18
DIV2
DIV18
DIV2
DIV18
8
10.3
13.3
17.2
22.2
28.7
37.0
47.8
198
152
117
89
67
51
38
28
381
295
227
174
133
102
78
59
179
138
105
80
61
46
34
25
346
267
206
158
121
92
70
53
304
235
180
138
106
80
61
46
582
451
348
267
206
158
121
92
273
211
162
124
94
72
54
41
523
405
312
240
185
141
108
82
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
7
20
FET Driver Implementation
7.1 Normal Operation
The top side FET drivers are bootstrapped drivers. Each of the six external FET transistors which have
to be connected can be controlled directly via six digital inputs.
The six external FET transistors (or three half bridges) can also be controlled using only three digital
input signals. Therefore, proceed as follows:
-
Connect the BHx to VCC.
Control the 3 phases via the BLx inputs. In this mode of operation, the TMC6130 will
automatically generate the programmed dead times.
The drain source voltage VDS as well as the gate voltage VGS are monitored to ensure fail safe operation.
The FET gate outputs are all pulled low by pulling ENABLE low.
7.2 FET Driver during Sleep Mode
In sleep mode, a gate discharge resistance (RSGD ~ 1KΩ) is activated. This ensures that the FET gates
remain fully in OFF state. It is the responsibility of the microcontroller to ensure all gate voltages are
low, for instance by setting the ENABLE input low, prior to switching to sleep mode.
VCPx
TMC6130
HSx
RSGD
BMx
VCP_REG
LSx
RSGD
Figure 7.1 Fet driver during sleep mode: BMx is kept low with HSx through the internal body
diode of the TMC6130.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
8
21
Absolute Maximum Ratings
The maximum ratings may not be exceeded under any circumstances. Operating the circuit at or near
more than one maximum rating at a time for extended periods shall be avoided by application design.
All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum
ratings given in the table below are limiting values that do not lead to a permanent damage of the
device but exceeding any of these limits may do so. Long term exposure to limiting values may affect
the reliability of the device. Reliable operation of the IC is only specified within the limits shown in the
table.
Parameter
Supply voltage
Voltage on analogue LV
Digital output voltage
Digital input voltage
Digital input current
Input voltage on BMx pins
Maximum
latch–up
free
current at any pin
ESD capability of any other
pin
Storage temperature
Junction temperature
Thermal resistance package
Symbol
VM
VMON
VAN_LV
VOUT_DIG
VIN_DIG
IIN_DIG
VIN_BMx
Condition
t < 200ms *1)
permanent (functional)
Min
-0.5
-0.5
-0.5
-0.5
-0.5
-10
-2
Max
Unit
45
28
VCC+0.5
VCC+0.5
VCC+0.5
10
45
V
V
V
V
V
mA
V
ILATCH
according JEDEC JESD78,
AEC-Q100-004
-100
100
mA
ESD
human body model *2)
-2
+2
kV
tSTG
tJ
-55
-40
in free air on multilayer pcb (37)
to be
(JEDEC 1s2p)
confirmed
150
150
°C
°C
RTHJA
RTHJC
*3)
referring to
exposed pad
center
of (10)
to be
confirmed
K/W
K/W
NOTES
*1) Only during load dump pulse.
*2) Equivalent to discharging a 100pF capacitor through a 1.5kΩ resistor conform to MIL STD 883 method
3015.7
*3) For applications with tJ > 125C: the extended temperature range is only allowed for a limited period
of time. The application mission profile has to be agreed by TRINAMIC. Some analogue parameters
may drift out of limits, but chip function is guaranteed.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
9
22
General Electrical Specifications
9.1 Operational Range (unless otherwise specified)
Parameter
Symbol
Min
Max
Unit
Application temperature
Supply voltage TMC6130
VCC logic supply input voltage
tA
VM
VCC
-40
7
3
125
18
5.5
°C
V
V
Max
Units
relaxed
7
4.5
18
7
V
V
relaxed
18
28
V
30
µA
1
mA
35
V
BATTERY SUPPLY
Parameter
Symbol
Supply voltage
Supply voltage
extended range low
Supply voltage
extended range high
Quiescent current
drawn from VM
Operating current
drawn from VM
VM
VM_ERL
Battery overvoltage
threshold high
Battery overvoltage
threshold low
Battery overvoltage
threshold hyst
Battery overvoltage
debounce time
Battery undervoltage
threshold high
Battery undervoltage
threshold low
Battery undervoltage
threshold hyst
Battery undervoltage
debounce time
Power on reset level
VM_OVH
Pre-driver operation without
charge pump operation
(EN_CP=0).
Warning on ERROR.
VM_OVL
ERROR released.
www.trinamic.com
VM_ERH
IMSLEEP
IM_INT
Test Conditions
Functional with
specification.
Functional with
specification.
VCC = low
Min
VM_OV_HY
Typ
31
0.4
V
1
VM_OV_DEB
VM_UVH
Warning on ERROR.
VM_UVL
ERROR released.
VM_UVHY
0.2
Reset released on rising
edge of VM while VCC is high.
2
µS
6
V
5
VM_UV_DEB
VPOR
V
3
V
0.5
V
10
µS
4.5
V
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
23
POWER AND TEMPERATURE
Parameter
Overtemperature
protection high
Overtemperature
protection low
Symbol
OTH
Test Conditions
Warning on ERROR.
Min
153
Typ
166
Max
183
Units
OTL
ERROR released.
123
137
153
°C
Test Conditions
Maximum input current
includes ERROR current
sourcing.
Min
Typ
Max
20
Units
mA
230
300
370
KΩ
3
5.5
V
2.7
2.8
V
2.6
2.7
V
°C
VCC IO SUPPLY INPUT
Parameter
VCC operating current
Symbol
ICC
VCC pull down
resistance
VCC input voltage
VCC_RPD
VCC input
undervoltage high 1)
VCC input
undervoltage low
VCC input
undervoltage hyst
VCC sleep voltage high
VCC_UV_H
VCC sleep voltage low
VCC_SLEEP_L
VCC
VCC_UV_L
VCC = 3.3V or 5V,
logic supply.
VCC increasing,
NFET control is activated.
VCC decreasing,
disable NFET control.
VCC_UV_HY
VCC_SLEEP_H
0.07
VCC increasing,
out of sleep.
VCC decreasing,
go to sleep.
VCC sleep voltage hyst VCC_SLEEP_HY
1)
0.1
V
2.45
2.6
V
1.9
2
V
0.45
0.58
Min
170
Typ
V
The info VCC_UV_X is used to disable the control of the external FETs.
ON-CHIP OSCILLATOR
Parameter
Charge pump
frequency
ERROR PWM frequency
fast
ERROR PWM frequency
slow
SPI start up pulse
duration
www.trinamic.com
Symbol
FCP
Test Conditions
Max
230
Units
KHz
FERROR_F
85
115
KHz
FERROR_S
10.6
14.4
KHz
2048/F
OSC
4096/F
OSC
Sec
tSPI_SU
EN = Low
BH1/2/3 = low
BL1/2/3 = high
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
24
The charge pump of the TMC6130 can be used with three modes of operation.
CHARGE PUMP / CPMODE=X
(Silicon diodes BAS16, Ccp=1µF,Cboost=1µF +Creg=4.7µF: to be confirmed)
Parameter
Resistive load from
VCP to GND
Symbol
RCP_LEAK
Test Conditions
RTYP = room temperature
RMIN = 150C
(excl. RVCP_REG_LEAK)
Min
6
Output slew rate
Charge pump
frequency
VCP undervoltage
(VCP high)
VCP undervoltage
(VCP low)
Typ
8
Max
Units
MΩ
100
FCP
170
VCP_UVH
ERROR released.
VCP_UVL
Warning on ERROR.
200
V/us
230
kHz
7.2
V
6.7
V
5.7
CHARGE PUMP / CPMODE=0
(Silicon diodes BAS16, Ccp=1µF,Cboost=1µF +Creg=4.7µF: to be confirmed)
Parameter
CP Load current on
VCP_REG
Output voltage
VCP_REG
Symbol
Test Conditions
ICP_REG_MODE VCP_REG > 11V
EN_CP = 1
0
VREG
VM > 8V
Ireg < 40mA
Output voltage
VCP_REG
VCP Undervoltage,
(VCP high)
VCP Undervoltage,
(VCP low)
VCP_REG
Min
Typ
Max
40
Units
mA
11
12
13
V
13
V
7.2
V
6.7
V
10
VCP_UVH
VM = [7,8]V
IVCP_REG < 40mA
ERROR released.
VCP_UVL
Warning on ERROR.
5.7
CHARGE PUMP / CPMODE=1
(Silicon diodes BAS16, Ccp=1µF,Cboost=1µF +Creg=4.7µF: to be confirmed)
Parameter
CP load current on
VCP_REG
Reverse polarity NFET
gate voltage
(VCP – VM)
Output voltage
VCP_REG
VCP undervoltage,
(VCP – VM) high
VCP undervoltage,
(VCP – VM) low
www.trinamic.com
Symbol
Test Conditions
ICP_REG_MODE VREG > 11V
EN_CP = 1
1
VGS_RPFET
VM > 7
IVCP_REG < 20mA
VCP_REG
IREG < 20mA
VCP_UVH
ERROR released.
VCP_UVL
Warning on ERROR.
Min
Typ
Max
20
Units
mA
5
12
13
V
11
12
13
V
7.2
V
6.7
V
5.7
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
VREG Warnings / CPMODE=X
Parameter
Symbol
Internal resistive load RVCP_REG_LEAK
from VCP_REG to GND
VCP_REG overvoltage
VCP_REG_OVH
high
VCP_REG overvoltage
VCP_REG_OVL
low
VCP_REG overvoltage
VCP_REG_OVHY
hyst
VCP_REG undervoltage VCP_REG_UVH
high
VCP_REG undervoltage VCP_REG_UVL
low
25
Test Conditions
RTYP = Room
RMIN = 150C
Warning on ERROR.
Min
0.3
14.2
ERROR released.
13.5
0.7
Typ
0.4
Max
Units
MΩ
16.5
V
V
1
ERROR released.
V
8.1
V
7.8
V
Warning on ERROR.
6.9
Test Conditions
Pre-driver is not in sleep
mode.
Min
Typ
Max
20
Units
µA
Test Conditions
Min
6
4
2.4
Max
8
15
15
6.5
Units
5.7
Ω
IG_ON
Cload = 1nF, 20% to 80%
Cload = 1nF, 80% to 20%
-10mA tJ = -40
-10mA, tJ = 150
10mA tJ = -40
10mA, tJ = 150
VGS = 0V
Typ
4
7
7
-1
-1.4
A
IG_OFF
VGS = 12V
1
1.6
A
tPD_DRV
From logic input threshold
20
to 2V VGS drive output at no
load.
Transitions at the different
-20
phases at no load condition.
DEAD_TIME[2:0] = 000
0.0001
001
010
011
100
101
110
111
-15
100
ns
20
ns
0.0002
µs
15
%
VBATF
Parameter
Symbol
Internal leakage from RVMON_LEAK
VMON to GND
FET GATE DRIVERS
Parameter
Driver ON resistance2)
Rise time
Fall time
Pull-up on resistance
Symbol
RDR_ON
tR
tF
RON_UP
Pull down on
resistance
Turn on gate drive
peak current
Turn off gate drive
peak current
Propagation delay
RON_DN
Propagation delay
tPD_DRVM
matching
Programmable dead
tDEAD
time :
asynchronous internal
delay between top and
bottom FET
Dead time tolerance
www.trinamic.com
tDEAD_TOL
1.5
0
0.5
0.75
1.0
1.5
2.0
3.0
6.0
Ω
ns
ns
Ω
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
26
FET GATE DRIVERS
Parameter
Programmable VDS
monitor voltage
Symbol
VDS_MON
Programmable VDS
tVDS_BL
monitor blanking time:
internal delay between
GATE signal high and
enabling the
corresponding VDS
monitor
VDS blanking time
tolerance
Sleep gate discharge
resistor
tVDS_TOL
VGS under voltage
monitor
PWM frequency
Leakage from VCPx to
BMx
VGS_UV
2)
RSGD
FPWM
RCP_LEAK
Test Conditions
VDSMON[2:0] = 000:
disabled
001
010
011
100
101
110
111
VDS_BLANK_TIME[1:0] = 00
01
10
11
Min
0.4
0.6
0.85
1.05
1.25
1.5
1.70
Typ
0.5
0.75
1.00
1.25
1.50
1.75
2.00
Typ = Room
Min = 150C
TBD
5
0.75
20
1
Units
V
0.6
0.9
1.15
1.45
1.75
2.00
2.3
0.75
1.5
3
6
-15
Internal resistance between
FET gate-source pins to
switch-off FET.
VCC = 0V (sleep mode)
VGS = 0.5V
See chapter FET driver
during sleep mode.
Warning on ERROR.
Max
µs
15
%
1
KΩ
75
%VREG
100
KHz
MΩ
Max
70
Units
%VCC
The driver on resistance is <5Ω at 25°C. Maximum values correspond with 150°C.
Logic IO (FET inputs, EN input)
Parameter
Symbol
Digital input high
VIN_DIG_H
voltage
Digital input low
voltage
Input pull-up
resistance
Input pull-down
resistance
Input pull-down
resistance
RIN_DIG_PU
Test Conditions
Minimum voltage for input
to be treated as logical
high
Maximum voltage for input
to be treated as logical low
BL1, BL2, BL3
RIN_DIG_PD
VIN_DIG_L
Min
Typ
30
%VCC
90
410
KΩ
BH1, BH2, BH3
90
410
KΩ
REN_PD
ENABLE
90
410
KΩ
Symbol
tSPI_ISU
FSPI
Test Conditions
Max
Units
µsec
KHz
SPI TIMING
Parameter
SPI initial setup time
SPI clock frequency
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Min
2
Typ
500
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
27
SPI TIMING
Parameter
Rise/fall times
Symbol
tSPI_RF
Test Conditions
All rise/fall times on CLK,
CSB, MISO, MOSI
Min
Typ
Max
200
CSB setup time
CSB high time
Clock high time
Clock low time
Data in setup time
Data in hold time
Data out ready delay
EEPROM read delay
EEPROM write delay
tCSB_SU
tCSB_H
tCLK_H
tCLK_L
tDI_SU
tDI_H
tDO_R
tEE_RD
tEE_WR
Cload at BL1<50pF
EE_RD = 1
EE_RD = 1
Symbol
IERROR_PU
IERROR_PD
Test Conditions
VERROR = 0V
VERROR = VCC
Min
-2.23
5
Typ
Max
-5
2.6
Units
mA
mA
Symbol
ENPR_DEL
Test Conditions
From bridge enable EN<
0.2*VCC to VGS<0.5V with
Cload=1nF.
Min
Typ
Max
1
Units
µs
1
2
1
1
1
500
Units
nsec
µsec
µsec
µsec
µsec
µsec
µsec
µsec
µsec
msec
500
6
12
ERROR OUTPUT
Parameter
Pull-up current
Pull-down current
ENABLE INPUT
Parameter
Bridge disable
propagation delay
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
28
CURRENT SENSE AMPLIFIER
Parameter
Input offset voltage
Symbol
VIS_IO
Input offset voltage
thermal drift
VIS_IO_TDRIFT
Input common mode
rejection DC
ISCMR_DC
Input common mode
rejection 1MHz
ISCMRR_AC
Input power supply
rejection DC for VCC
supply
ISPSRR_DC
Input power supply
rejection 1MHz for VCC
supply
ISPSRR_AC
Closed loop gain
ISGAIN
Output settling time
ISSET
Output voltage range
high
Output voltage range
low
Output short circuit
current to ground
GBW
Output slew rate
CM spike recovery
VCURRENT_MAX
VREF voltage input
VREF
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VCURRENT_MIN
ICURRENT_SC
ISGBW
ISSR
ISCM_REC
Test Conditions
Input diff. voltage within
+/-100mV;
common mode within -0.5…
1.0V.
Input diff. voltage within
+/-100mV;
common mode within -0.5…
1.0V.
Input diff. voltage within
+/-100mV;
common mode within -0.5…
1.0V.
Input diff. voltage within
+/-100mV;
common mode within 0.5… 1.0V.
Input diff. voltage within
+/-100mV;
common mode within -0.5…
1.0V
Input diff. voltage within
+/-100mV;
common mode within -0.5…
1.0V.
Gain is programmable in
EEPROM.
Amplified output to 99% of
final value after input
change.
Current sense output max
level.
Current sense output min
level.
Output current saturation
level.
Min
-5
Typ
-10
Max
5
Units
mV
10
µV/°C
60
dB
40
dB
60
dB
40
dB
-3%
8.0
10.3
13.3
17.2
22.2
28.7
37.0
47.8
VCC 0.020
GND
+3%
-
1.0
µs
VCC
V
GND
+0.020
V
1.4
mA
40
730
MHz
V/µs
nS
50
%VCC
10
CM spike = ± 1.5V
duration = 250nsec
0
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
29
10 Package Mechanical Data
10.1 QFN32 Dimensional Drawings
Attention: Drawings not to scale.
Figure 10.1 Dimensional drawings
Parameter
Total thickness
Standoff
Lead frame thickness
Lead width
Body size X
Body size Y
Lead pitch
Exposed die pad size X
Exposed die pad size Y
Lead length
Ref
A
A1
A3
b
D
E
e
J
K
L
Min
0.80
0.00
Nom
0.85
0.05
0.2
0.18
Max
1.00
0.05
0.3
5.0
5.0
0.5
3.5
3.5
0.3
3.7
3.7
0.5
General tolerance of D and E is ±0.1mm.
Bottom pin 1 identification may vary depending on supplier.
10.2 Package Code
Device
TMC6130
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Package
QFN32 (RoHS)
Temperature range
-40° to +125°C
Code/ Marking
TMC6130-LA
TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
30
11 Disclaimer
TRINAMIC Motion Control GmbH & Co. KG does not authorize or warrant any of its products for use in
life support systems, without the specific written consent of TRINAMIC Motion Control GmbH & Co. KG.
Life support systems are equipment intended to support or sustain life, and whose failure to perform,
when properly used in accordance with instructions provided, can be reasonably expected to result in
personal injury or death.
Information given in this data sheet is believed to be accurate and reliable. However no responsibility
is assumed for the consequences of its use nor for any infringement of patents or other rights of third
parties which may result from its use.
Specifications are subject to change without notice.
All trademarks used are property of their respective owners.
12 ESD Sensitive Device
The TMC6130 is an ESD-sensitive CMOS device and sensitive to electrostatic discharge. Take special care
to use adequate grounding of personnel and machines in manual handling. After soldering the devices
to the board, ESD requirements are more relaxed. Failure to do so can result in defects or decreased
reliability.
Note: In a modern SMD manufacturing process, ESD voltages well below 100V are standard. A major
source for ESD is hot-plugging the motor during operation. As the power MOSFETs are discrete devices,
the device in fact is very rugged concerning any ESD event on the motor outputs. All other connections
are typically protected due to external circuitry on the PCB.
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
31
13 Table of Figures
Figure 1.1 Block diagram and principle operation circuit......................................................................................... 4
Figure 1.2 Application example for +12V DC................................................................................................................. 5
Figure 1.3 Application example for +24V DC................................................................................................................. 5
Figure 1.4 Ground connections ......................................................................................................................................... 6
Figure 1.5 Supply connectinons ....................................................................................................................................... 7
Figure 1.6 Gate driver connections .................................................................................................................................. 7
Figure 1.7 Digital IO connections .................................................................................................................................... 7
Figure 1.8 Amplifier connections ..................................................................................................................................... 7
Figure 2.1 TMC6130 pin assignments.............................................................................................................................. 8
Figure 3.1 Power supply systems: CPMODE = 0 and CPMODE = 1 ........................................................................ 10
Figure 4.1 ERROR handshake protocol .......................................................................................................................... 13
Figure 4.2 ERROR output ................................................................................................................................................... 14
Figure 7.1 Fet driver during sleep mode: BMx is kept low with HSx through the internal body diode of
the TMC6130. ........................................................................................................................................................................ 20
Figure 10.1 Dimensional drawings ................................................................................................................................ 29
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TMC6130 DATASHEET (Rev. 0.90 / 2014-MAR-10) PRELIMINARY
14 Revision History
Version
Date
Author
Description
SD – Sonja Dwersteg
0.9
2014-MAR-10
SD
Initial version; preliminary.
15 References
[TMC6130-EVAL]
TMC6130-EVAL Manual
Please refer to our web page http://www.trinamic.com.
www.trinamic.com
32