AN0018 Application Note: THERMAL MANAGEMENT for DIES and PLASTIC PACKAGES GaAs Monolithic Microwave IC 1. Introduction Thermal management is key for proper usage of semi-conductors, and particularly III-V based circuits. Gallium Arsenide has very good microwave dielectric properties, with quite poor thermal conductivity as a counter part (at least compare to silicon). Thermal computation and simulation are then recommended to provide the requested thermal environment to a chip, from die-attach to package assembly, mother-board and housing design. Keeping the junction temperature below the defined Tjmax (maximum junction temperature) is mandatory to ensure reliability. This document aims to give an overview on thermal management at the chip level and also in plastic packages (QFN). Basic rules, definitions and simplified methodologies are given here to help making temperature evaluation. There is no intention to replace precise and time consuming 3D physical thermal simulations. The real mechanical structure, the non linear thermal materials properties, the very large scale factors involved in an integrated circuit, especially from the transistors junctions (few nanometres) to the final chip housing (several millimetres), the coupling between the different hot areas will have also a strong effect on the final result. Ref. : AN0018-9084-25 Mar 09 1/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 2. Thermal Management at the chip level Two thermal sources exist at the chip level. The main source is coming from the transistor junctions and the second one is due to the resistive layers implemented on the circuit. The lifetime of the device is mainly driven by the junction temperature of the transistors and must be maintained as low as possible. The maximum junction temperature used by UMS for reliability and processes qualification is +175°C. Higher temperature should have an impact on the device reliability and lifetime. Guides lines to estimate this junction temperature are given below. The thermal power dissipated by a transistor junction is (Pdissipated_J in Watts) defined by the simple expression Eq 1. Eq 1 : Pdissipated_J(W) = Pdc(W) – [Pout_RF(W)-Pin_RF(W)] Where: Pdc (W) is the DC power consumption of the transistor junction= Vdc(Volts) x Idc (Amperes). Vdc is the DC voltage applied to the junction. Idc is the DC current flowing through the junction. Pin_RF (W) is the input microwave power injected to the transistor junction in Watts. Pout_RF (W) is the output microwave power emitted by the transistor junction in Watts. Another expression can be defined around the Power Added Efficient (PAE in %) commonly used in electronic: Eq 2 : PAE(%)=[Pout_RF(W)-Pin_RF(W)]/Pdc(W) Then Eq 1 becomes: Eq 3 : Pdissipated_J(W) =Pdc(W) x [1-PAE(%)] The junction temperature must remain lower than a maximum limit defined according to the lifetime targeted for the device. Note that the safe estimation should be done considering the PAE=0% (No RF, CW mode) in most cases. There is also thermal energy dissipated on chip due to the Joule effect through the resistive layers (metallic resistors …). Then this dissipated power is defined with the very basic Joule equation: Eq 4 : Pdissipated_R(W)=R(Ohms) x I2 (Amperes). Where: R stands for the resistance of the concerned conductor in Ohms. Ref. : AN0018-9084-25 Mar 09 2/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 I stand for the current flowing through the resistor in Amperes. The total dissipated power Pdissipated (W) at the chip level is the sum of all the thermal contributors: Eq 5 : Pdissipated (W ) = ∑ ∑ Pdissipated _ R(W ) Pdissipated _ J (W ) + junctions resistors Due to the small dimensions of the devices, the distances between each of theses hot spots will induce thermal coupling and a rigorous analyse force to estimate each of these contributors and their coupled effects should be considered at the same time. But for a preliminary and simple estimation the following approximation can be done: Each transistor constituted by several junctions can be considered as one single hot spot decoupled from the others transistors. It is assumed that all the junctions are strictly similar (same consumption, same PAE). Then the dissipated power of the transistor is given by: Eq 6 : Pdissipated_T(W)=N x Pdissipated_J(W) Pdissipated_T(W)=N x Pdc(W) x [1-PAE(%)] Where N is the number of gates for the transistor. The junction temperature of this stand alone component can be estimated by the following conductivity equation: Eq 7 : Tj(°C)=[Pdissipated_T(W) x Rth GaAs(°C/W)]+Tb(°C) Where: Tj (°C) is the junction temperature of a junction c onstituting the transistor considered. Tb (°C) is the back side temperature of the chip. RthGaAs (°C/W) is the thermal resistance equivalent to the semiconductor layer under the transistor. This thermal resistance is function of several parameters and should be estimated with a rigorous 3D thermal simulation considering: • The semiconductor physical properties • The chip thickness • The transistor geometry: via-holes location and shape, junctions spacing, metal drains, etc… For a simple and quick first estimation, empirical rules can be used to determine this thermal resistance. In the case of the UMS PHEMT processes (PH25 and PH15), Fig. 1 and Fig. 2 can be used to evaluate the thermal resistance of a FET (100µm GaAs substrate Ref. : AN0018-9084-25 Mar 09 3/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 thickness), when the unit finger width Wu and package temperature (given as a parameter) are known. RTH is given for 1mm gate width. To obtain the thermal resistance RTHC of the component, the following formula can be used: Eq 8: RthGaAs(°C/W) = R TH(°C.W -1.mm) * 1000/W(µm) Where W is the total gate width of the FET. Theoretical curves are based on FUKUI curves and are given for information purposes (H. FUKUI ”Thermal Resistance Of GaAs Field-Effect Transistors”, p118, IEDM, 1980). (°C) 120 115 120 110 100 105 80 100 R T H 95 60 90 40 85 20 80 0 75 ° C / W * m m -20 70 65 -40 60 -60 55 50 45 40 35 30 25 20 10 20 30 40 50 60 70 80 90 100 Wu : unit gate width (µm) Fig. 1: Thermal resistance as a function of the unit gate width and chip back side temperature for the UMS PH25 process Ref. : AN0018-9084-25 Mar 09 4/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 (°C) 140 R 120 100 80 120 T H 60 40 100 * 20 0 o 80 -20 C -40 -60 / W . m m 60 40 * 20 10 20 30 40 50 60 Wu:unit gatewidth (µm) 70 80 90 Fig. 2: Thermal resistance as a function of the unit gate width and chip back side temperature for the UMS PH15 process 3. Worst case estimation: To estimate the real margins of the integrated circuit, the calculation of the junction temperature should be done for the worst operating conditions: 1. Maximum DC consumption. 2. For the circuit working with pulsed power supplies, the temperature estimation should be done in CW mode. 3. The reference temperature (chip back-side temperature or package back-side temperature) must be set-up to the maximum temperature specified for the equipment. 4. The microwave signal must be turned off (no RF signal injected to the function). Then the PAE = 0%. Ref. : AN0018-9084-25 Mar 09 5/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 4. Thermal management for packaged product: Physically, the GaAs chip is not assembled on a perfect heat spreader. Then, it is necessary to considered the whole structure from the die attach to the main thermal drain. In this paragraph, the example of a die embedded in a plastic package assembled on a glass laminated carrier is considered. See Fig. 3 below. Fig. 3: Cross section of a QFN package assembled on the PCB & thermal model At a first order, the main thermal limitations in this structure to dissipate the thermal power generated from the top side of the MMIC to the heat sink are coming from: • • • The GaAs layer (RGaAs) The die attach layer (Rdie attach) The carrier (Rcarrier) Ref. : AN0018-9084-25 Mar 09 6/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 The thermal resistance for each layer is given by Eq 9. 1 h ( m) °K Eq 9 : Rth × = W K W S (m²) th m.° K Where: Kth is thermal conductivity of the layer. h the thickness of the layer. S is the section of the layer participating to the heat conduction. The volume of the layer participating to the thermal conduction is estimated assuming that all the layer volume is used for the heat conduction (Volume(m3) =h(m) x S(m²)). But in the reality, the thermal power will be conduced trough a dissipation cone where the opening angle (α) is a function of the materials thermal conductivities λ (see Eq 10 and Fig. 4). Eq 10 : tan α ( Deg ) = λ1 (W / m.°C ) λ2 (W / m.°C ) Hot spot λ1 (W/m.°C) Back-side thermal dissipation surface for a poor thermal conductivity material Back-side thermal dissipation surface for a better thermal conductivity material α (Deg) h (mm) W (mm) L (mm) λ2 (W/m.°C) Fig. 4 : Thermal dissipation cone though an homogenous layer Naturally, when the layer is thick enough the back-side dissipation surface is equivalent to the total layer surface S(mm²)=L x W as represented on Fig. 4. However, to simplify the analyse in a first approximation it is possible to apply Eq 9 for the layers under the GaAs chip considering that all the contact surface between the layers will conduce the heat. That is due to the layers staking. Generally, the GaAs layer is the poorest thermal conductor in the structure because only a small Ref. : AN0018-9084-25 Mar 09 7/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 volume of the crystal is used to spread out the thermal energy. This volume is limited by the dissipation cone defined at the Fig. 4. The die-attach and the lead-frame can be considered as good conductors. But the PCB mother board below this structure is generally limiting again. Then the angle α in Eq 10, will close to 90° in the die attach and in the lead-frame layers and reduced in the motherboard. The temperature gradient ∆T(°C) through a layer flowing the dissipated power Pdissipated (W) is given bellow: °C Eq 11 : ∆T (°C ) = Rth × Pdissipated (W ) W Then, the thermal model equivalent to the structure shown Fig. 3 is equivalent to Eq 12: ∆T (°C ) = T j − Ta = ( RGaAs + Rdie _ attach + Rlead _ frame + Rsolder1 + Rcarrier + Rsolder 2 ) × Pdissipated Eq 12: ∆T (°C ) = T j − Ta = Rthtotal × Pdissipated T j − Tb = RGaAs × Pdissipated is the gradient of temperature through the MMIC. Tb − Tcase = ( Rdie _ attach + Rlead _ frame ) × Pdissipated is the gradient of temperature through the package’s base. Tcase − Ta = ( Rsolder1 + Rcarrier + Rsolder 2 ) × Pdissipated is the gradient of temperature through the PCB. If we consider that the hot spot is constituted by a FET, Pdissipated is given by the equation Eq 6. And Tj is the junction temperature as defined in Eq 7. Thermal conductivities figures of some commonly used materials are collected in the following table. Ref. : AN0018-9084-25 Mar 09 8/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 Materials GaAs crystal Si Quartz Alumina (Al203 96%) Alumina (Al203 99,8%) Copper (Cu) AlSiC C194 (Copper alloy) Aluminium Gold Ro4003 CuW/15-85 CuW/10-90 CuMo/15-85 Silva-K ™ BeO Kovar Molybdenum FR4 or other PCB… BCB Speedboard Prepgreg SN63 solder Ablestick ABLETHERM 2600AT Epoxy die attach – high thermal performance epoxy (electrically conductive) Ablestick ABLEBOND 2815A Epxoy die attach – high thermal performance epoxy (electrically conductive) Ablestick ABLEBOND 84-1 LMISR4 Epoxy die attach – low thermal performance epoxy (electrically conductive) Diemat DM6030Hk Epoxy die attach - high thermal performance epoxy (electrically conductive) Ablestick ABLEBOND 84-3j Epoxy die attach (electrically non-conductive) Thermal conductivity -1 -1 Kth (W.m .°K ) (1) 44,3 @ T0=+25°C 124 1,4 24 to 27,6 36 393,7 180 260 235 311 - 315 0,62 180 209 184 110 250 14 140 0,3 0,15 - 0,4 0,28 50 20 20 2,5 CTE @ +25°C (ppm/°K) 5,73 2,6 0,59 6,5 to 7 8,4 16,5 6.7 16 23,1 14,7 15 7 6.5 6.6 7 6.4 5.9 5.1 13-15 42 56 36 for T°<Tg 111 for T°>Tg (Tg=84°C) 64 fro T°<Tg 122 for T°>Tg (Tg=63°C) 40 for T°<Tg 150 for T°>Tg (Tg=120°C) 60 26 0,5 41 for T°<Tg 112 for T°>Tg (Tg=87°C) Table 1: Materials physical properties (1) The thermal conductivity of the GaAs crystal is non-linear and depends on temperature. For more precise calculations it is possible to use the following equations: Kth (W.m-1.°K -1) = 55.9x103*(273.15+To)-1.253 Calorific Capacity (J/kg.K) = 330 Density (kg/m3) = 5307 Ref. : AN0018-9084-25 Mar 09 9/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 4.1. The GaAs layer For the transistors the contribution of the GaAs layer on the thermal dissipation can be estimated by applying the rules defined in the paragraph 2. Then RGaAs in the equation Eq 12 can be substituted by the equation Eq 8. For a simple planar component such as a resistor, the GaAs crystal thermal conductivity given in the Table 1 must be considered to estimate RGaAs with the equation Eq 9. 4.2. The die attach layer The die attach layer should be as thin as possible to minimize the thermal resistance from the MMIC back-side to the package lead-frame. But the thickness must be calibrated to manage also the differential dilatations between the GaAs chip (CTE = 5.73 ppm/°C) and the copper lead-frame (CTE = 16.5 ppm/°C). Then, it is recommended to verify that the process used for this die attach will provide a void free layer: voids should be considered as insulators, and so not contributing to the heat conduction. Typically the die attach thickness is between 10µm to 20µm depending on the MMIC surface. 4.3. The lead frame layer The lead frame of the QFN packages is made of copper. This material has a very good thermal conductivity. So, the thermal power dissipated by the MMIC can be considered as fully spread through the entire die attach pad (DAP) surface. It can be considered as the closest heat sink from the MMIC. It is 200µm thick for typical QFN packages. 4.4. The solder layer Typically, the thickness of the solder layer is about 20µm to 50µm and the thermal conductivity is close to 50 W/(m.°K). Theses figures depend on the selected assembly process. And a special care must be taken in the soldering process to minimize the surface void in the solder. 4.5. The PCB (carrier layer) The PCB constitutes a key point in the thermal design of the final product. Typically UMS recommends using a glass-laminated carrier (Rogers 4003, thickness h = 203µm) to achieve high electrical performance and low cost product. To improve the thermal management through this layer, thermal via holes must be implemented. The density of the via-holes matrix and the fill-in material has to be considered to get the best thermal conductibility to the PCB. The soldering process associated to carful PCB design is a key factor to minimize the voids under the package. Ref. : AN0018-9084-25 Mar 09 10/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 The thermal resistance through the PCB can be approximated considering that all the thermal conduction is done by the via-holes metallization. The conduction through the substrate is then neglected. This approximation is realistic if: • • The via-hole pitch (Pvia) is not too large in comparison with the via-hole diameter (dvia). o Typically Pvia/dvia < 2.5 The via-hole is filled in with a low thermal resistive material (copper, solder paste, conductive glue). The equivalent via-hole thermal conductivity Kvia has to be very high in comparison with the substrate thermal conductivity Ksub. o Typically Kvia > 100 x Ksub. Thermal viaholes area QFN package outline Fig. 5: Example of foot-print on PCB for QFN package Then the PCB thermal resistance is given by: hsub (m) 1 °K Eq 13: Rthmother _ board × = dext via (m) 2 d int via (m) 2 W K W N via × π via − m.° K 2 2 Where: Kvia is the thermal conductivity of the fill-in material of the via-hole in W/(m.°K). hsub the substrate thickness in meters Nvia the number of via-holes under the die attach pad of the QFN package. dextvia the external via-holes diameter in meters. dintvia the internal via-holes diameter in meters. Eq 13 based on Application Note «Thermal Management for Surface Mount Components» from Hittite Microwave. Ref. : AN0018-9084-25 Mar 09 11/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 5. Thermal resistance for UMS standard QFN PLASTIC packages Package ground pad surface QFN 3X3 1.45x1.45mm² QFN4X4 2.45x2.45mm² QFN5X5 3.65x3.65mm² 2.89 mm² 0.24°C/W 7.29 mm² 0.08°C/W 13.32 mm² 0.04°C/W 2.89 mm² 1.9°C/W 7.29 mm² 0.67°C/W 13.32 mm² 0.3°C/W 0.37°C/W 0.13°C/W 0.06°C/W 0.610°C/W 0.210°C/W 0.100°C/W 2.270°C/W 0.800°C/W 0.360°C/W Thermal resistance equivalent to the die attach join: Surface and thermal resistance -1 -1 (Kth = 20 W.m .°K ) Thermal resistance equivalent to the die attach join: Surface and thermal resistance -1 -1 (Kth = 2.5 W.m .°K ) Package thermal resistance Thermal resistance from the chip back-side to the package back-side (assuming die attach high -1 -1 conductibility 20 W.m . °K ) Thermal resistance from the chip back-side to the package back-side (assuming die attach high -1 -1 conductibility 2.5 W.m . °K ) Table 2: QFN plastic packages thermal resistance 6. Thermal limits UMS has already demonstrated the capability of the plastic packages to handle high power levels. The maximum power handling reached up to now for ambient temperature lower than +75°C is: Package type QFN 3 X 3 16 leads QFN 4 X 4 24 leads QFN 5 X 5 28 leads Dissipated power at ambient temperature = +75°C 1.7 W - CW 3 W - CW >6 W – CW Table 3: QFN plastic packages maximum dissipated power The QFN final assembly will have a strong influence on the maximum dissipated power level acceptable by the device. Remark: The thermal figures given in this UMS’ product data-sheet are obtained assuming that the QFN device is cooled down only by conduction through the package thermal pad (no convection mode considered). The temperature is monitored at the package back-side interface (Tcase) as shown below. Ref. : AN0018-9084-25 Mar 09 12/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 The system maximum temperature must be adjusted in order to guarantee that Tcase remains below the maximum value specified in the next table (Fig.6). So, the PCB should be designed to comply with this requirement. A de-rating must be applied on the dissipated power if the Tcase temperature can not be maintained below than the maximum temperature specified (see the curve Pdiss Max) in order to guarantee the nominal device life time (MTTF). DEVICE THERMAL SPECIFICATION : Product name Recommanded max. junction temperature (Tj max) : 124 °C Junction temperature absolute maximum rating : 175 °C Max. continuous dissipated power @ Tcase= 85 °C : 0,34 W (1) => Pdiss derating above Tcase = 85 °C : 9 mW/°C (2) Junction-Case thermal resistance (Rth J-C) : <114 °C/W (3) Min. package back side operating temperature : -40 °C (3) Max. package back side operating temperature : 85 °C Min. storage temperature : -55 °C Max. storage temperature : 125 °C (1) Derating at junction temperature constant = Tj max (2) Rth J-C is calculated for a worst case where the hotter junction of the MMIC is considered. (3) Tcase=Package back side temperature measured under the die-attach-pad (see the drawing below). Tcase 0,4 0,35 0,25 0,2 0,15 0,1 Pdiss. Max. (W) 0,05 Pdiss. Max. (W) 0,3 Example of QFN 16L 3x3 back-side view, temperature reference point (Tcase) location. 0 -50 -25 0 25 50 75 100 125 Tcase (°C) 5.6 Fig. 6: Thermal information sheet included to the UMS QFN product’s data-sheet Ref. : AN0018-9084-25 Mar 09 13/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 7. Example of junction temperature calculation If we consider the Ku band driver described as below: Output power at 1dB compression: Linear gain: Nominal positive supply voltage: Nominal positive supply current in linear mode: MMIC surface: Pout_P1dB = 30.5dBm Gain = 28dB Vd = +7V Id = 600mA 2300 x 1900µm2 Biggest transistor: Maximum drain-source voltage: Maximum drain-source curent: Transistor gain: FET output power at 1dB compression: PHEMT 0.25µm 12 x 100µm Vds = +7V Ids = +155mA G_FET = 9dB P1dB_FET = 28dBm Package: Plastic QFN 4x4 28 leads Exposed ground paddle at the package bottom-side: 2700 x 2700µm2 Equipment maximum operating temperature: Ta_max = +75°C Mother board: Laminated substrate h = 0.203µm (Ro4003) 12 empty via-holes through the mother board. The external via-holes diameter is = 300µm. The internal via-holes diameter is = 260µm. The via-hole platting is copper. As a first approximation, the junction temperature of the largest transistor can be considered as the maximum temperature for the chip. The thermal coupling between the transistors is neglected. The maximum dissipated power for the transistor is given by the equation Eq 6. In order to consider the worst thermal case, no microwave signal is applied to the function. Then all the DC prime power is dissipated by the transistor by thermal conduction and the PAE in Eq 6 equal 0%. Then Eq 6 becomes: Pdissipated_T(W) = Vds x Ids = 7V x 0.155A = 1.08W. The considered structure is equivalent to the Fig. 3. The thermal resistance equivalent to the structure below the GaAs chip is calculated in the Table 4. Then the MMIC back-side temperature Tb can be estimated. Ref. : AN0018-9084-25 Mar 09 14/16 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 AN0018 Layers (see Fig. 3) Rsolder 2 Rcarrier Rsolder 1 Rlead frame Rdie attach Heat sink Solder 2 Mother board Solder 1 Copper leadframe Epoxy die attach Length (µm) Width (µm) Thickness (µm) Surface (mm²) Material thermal conductivity -1 -1 (W.m .°K ) Layer Rth (°C/W) Used equation to calculate Rth Thermal power flowing through the layers (W) Top-side temperature (°C) see Eq 11 - - - - - 0 Perfect conductor 1.08W Ta=75 2700 2700 20 7.29 50 0.05 1.08W 75.05 - - - - - 2.44 1.08W 77.69 2700 2700 20 7.29 50 0.05 1.08W 1.08W 77.74 2700 2700 200 7.29 393.7 0.07 2300 1900 10 4.37 20 0.11 Eq 9 Eq 13, considering 12 empty copper via-holes (external diameter=300µm, internal diameter=260µm), through a PCB of 203µm in thickness. Eq 9 Eq 9, considering that all the package exposed pad surface participates to the heat conduction Eq 9, considering that all the chip back-side surface participates to the heat conduction 77.81 1.08W Tb=77.93 + Rthtotal carrier = 2.72 °C/W Table 4: Carrier equivalent thermal resistance calculation (see Fig. 3) The thermal resistance equivalent to the GaAs layer used in the Table 5 is estimated by using the Fig. 1, considering that the chip back side temperature is Tb = +77.93°C. Ref. : AN0018-9084-25 Mar 09 15/16 United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice AN0018 Layers (see Fig. 3) Length (µm) Width (µm) Carrier See Table 4 RGaAs GaAs FET 12x FET 100µm PHEMT =12x100 0.25µm Thickness (µm) Surface (mm²) - - Material thermal conductivity -1 -1 (W.m .°K ) - - Layer Rth (°C/W) Used equation to calculate Rth Following thermal power (W) Top side Temperature (°C) see Eq 11 2.72 Perfect conductor 1.08W Tb=77.93 1.08W Tj=168.8 - 100 84.2 Eq 8 and Fig. 1 with Wu=100µm, Tb=+77.93°C, W=12x100µm + Rthtotal 86.92 = °C/W Table 5: Complete structure thermal resistance calculation (see Fig. 3) Using the equation Eq 12, and assuming that the heat sink temperature is Ta = +75°C, Tj(°C) = Rth total (°C/W) x Pdissipated_T(W)+Ta (°C) Tj(°C) = 86.92 x 1.08 + 75 = 168.8°C. The maximum acceptable junction temperature is given to be +175°C. (De-rating might apply for specific applications, such as Space). Ref. : AN0018-9084-25 Mar 09 16/16 United Monolithic Semiconductors S.A.S. Route Départementale 128 - B.P.46 - 91401 Orsay Cedex France Tel. : +33 (0)1 69 33 03 08 - Fax : +33 (0)1 69 33 03 09 Specifications subject to change without notice

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