A Low Phase Noise VCO Design for PCS Handset Applications

APPLICATION NOTE
APN1016: A Low Phase Noise VCO Design for
PCS Handset Applications
Introduction
The factors that have significant impact on the primary VCO electrical specifications may be summarized as follows:
The VCO design in a PCS handset must satisfy a number of
stringent electrical, cost, and size requirements which include:
• Primary design criteria
- Frequency tuning range
• Power supply
- Tuning sensitivity
- 3 V DC power supply
- Output power level
• Stability and spectrum purity factors
- < 6 mA total current consumption
• Layout
- Minimum components count
- Phase noise at a given frequency offset
- Aggressive PCB layout design and component placement
rules with spacing less than 5 mils and placement pads no
larger than component’s land area
- Frequency pulling when terminated with SWR > 2 at all
phases
- Frequency pushing
- Total VCO footprint smaller than 7 x 8 mm
• Cost
- Temperature stability
Other electrical specifications may include harmonic content or
spur levels in the output signal, tuning linearity, etc. However, for
the existing handset VCO market these specifications have been
standardized based on available technology. Some typical PCS
VCO characteristics for PCS handsets are given in Table 1.
- Minimum component cost
- Maximum production yield
- Tight component tolerance control to minimize or
avoid trimming
- Total VCO cost well under $0.50
Manufacturer
Murata
Parameter
Test Conditions
Frequency Range* (GHz)
Other
MQE523
MQE920
Typical
VCTL = 0.5 V
1.715
1.948
-
VCTL = 2.5 V
1.778
2.086
-
31.5
69
40
3
3
3
Tuning Sensitivity (MHz/V)
Supply Voltage (V)
Supply Current (mA)
Control Voltage (V)
VCTL
Output Power (dBm)
POUT
Pushing Figure (MHz/V)
15.3
7
<8
0.5–2.5
0.5–2.5
0.5–2.5
-2
-0.5
0
3.8
-
<2
Pulling Figure (MHz)
SWR = 2, for all phases
0.90
-
<2
Phase Noise (dBc/Hz)
@ 10 kHz
-91
-91
-90
Table 1. Typical Characteristics for PCS Handset VCOs
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APPLICATION NOTE • APN1016
This application note describes the design and performance of a
VCO centered at 1750 MHz for a PCS handset that uses the
SMV1763-079 varactor diode. This low R varactor was designed
specifically for low phase noise applications. The VCO was
designed to satisfy the listed requirements for a PCS handset.
The Colpitts VCO Fundamentals
The fundamental Colpitts VCO operation is illustrated in Figures
1a and 1b.
Figure 1a shows a Colpitts VCO circuit the way it is usually implemented on a PCB. Figure 1b reconfigures the same circuit as a
common emitter amplifier with parallel feedback. We have separated the transistor junction and package capacitors, CEB, CCB
and CCE, from the transistor parasitic components to demonstrate
their direct effect on the VCO tank circuit.
In an actual low noise VCO circuit, the capacitor we noted as CVAR
may have a more complicated structure. It would include series
and parallel connected discrete capacitors used to set the oscillation frequency and tuning sensitivity. The parallel connection of
the resonator inductor, LRES, and the varactor capacitive branch,
CVAR, refer to the parallel resonator (or simply resonator). A
fundamental property of the parallel resonator in a Colpitts VCO
implementation is its inductive impedance at the oscillation
frequency. This means that its parallel resonant frequency is
always higher than the oscillation frequency.
At parallel resonance in the resonator branch, the impedance in
the feedback loop is high, acting like a stop-band filter. Thus, the
closer the oscillation frequency to the parallel resonant frequency,
the higher the loss introduced in the feedback path. However,
since more reactive energy is stored in the parallel resonator
closer to the resonant frequency, then higher Q load (QL) will be
achieved. Obviously, low loss resonators, like crystal or dielectric
resonators, allow much closer and lower oscillation loss buildup
at parallel resonance, in comparison to microstrip or discrete
inductor-based resonators.
The proximity of the parallel resonance to the oscillation
frequency may be effectively established by the CSER capacitor
value. Indeed, if the capacitance of CSER is reduced, the parallel
resonator will have higher inductance to compensate for the
increased capacitive reactance. This means that the oscillation
frequency will move closer to parallel resonance resulting in
higher QL and higher feedback loss.
VCC
CCB
CCE
CSER
CDIV1
LRES
CVAR
CVCC
CCB
CSER
POUT
CEB
CDIV2
RL
CEB
CVCC
CVAR
CDIV1
Figure 1a. Basic Colpitts VCO Configuration
LRES
CDIV2
RL
Figure 1b. Common-Emitter View of the Colpitts VCO
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APPLICATION NOTE • APN1016
The Leeson equation, establishing a connection between tank
circuit QL and its losses, states:
ξ ( ƒm)
=
FkT
2P
1+
signals. Since there are no such specifications currently available
for standard industry transistors, we can base our transistor
choice only on experience.
ƒ2
4Q
2
L
ƒm2
Where F is the large signal noise figure of the amplifier as shown
in Figure 1b; P is the loop or feedback power (measured at the
input of the transistor); and QL is loaded Q. These three parameters have significant consequences for phase noise in an
actual low noise RF VCO. In designing a low noise VCO, we need
to define the condition for minimum F and maximum P and QL.
This discussion shows that loop power and QL are contradictory
parameters. That is, an increase in QL leads to more loss in the
feedback path resulting in lower loop power. The condition for the
optimum noise figure is also contrary to maximum loop power
and largely depends on the specific transistor used. The best
noise performance is usually achieved with a high gain transistor
and the maximum gain coinciding with minimum noise at large
The VCO Model
In Figure 2, the transistors X1 and X2 are connected in DC
Cascode sharing the base biasing network consisting of R2
(RDIV1), R3 (RDIV2) and R4 (RDIV3). The bias resistor values were
designed to distribute the DC voltages evenly between X1 and X2.
Resistor R6 (RL) was chosen as low as 100 to minimize the DC
voltage drop to the specified 8 mA. At RF frequencies, X2 works
as a common emitter amplifier with the emitter grounded through
capacitor SRLC2. The oscillator stage output is fed to the buffer
transistor through coupling capacitor C17 (CCPL).
The output circuit of the buffer stage consists of the printed
microstrip line inductor TL5 and output capacitor C1 (COUT).
Capacitor SLC2, in parallel with the microstrip line inductor TL5,
may be used for finer trimming, when SLC2 is selected lower
than 0.5 pF.
Figure 2. PCS VCO Schematic for Libra IV, Using DC Cascode Colpitts VCO Configuration
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APPLICATION NOTE • APN1016
The equivalent series resistance of the capacitive branch of the
VCO resonator, shown in Figure 1, includes the varactor with its
series resistance. This resistance may be expressed as follows:
0.3
SMV123x
SMV11x9
SMV14x
RS_MIN
The resonator circuit consists of the printed microstrip line
inductor T3 in parallel with ceramic capacitor X3 (CPAR), the
capacitive varactor branch with X5 (CSER1) and varactor
SMV1763-079 X6 connected in series. The model for varactor
SMV1763-079 is described in a separate circuit schematic bench
shown in Figure 4. The varactor choice was based on the VCO
frequency coverage and the requirement for low phase noise.
This requirement is related to the need for low equivalent series
resistance, RS_EQV, in the overall VCO resonator.
0.2
SMV1763
0.1
1
2
3
4
5
KF (%)
R S _ EQV ≈ K V K ƒ ( R S + r S + r P )
C JO
CE
- 2 rP
K VK
ƒ
C JO
+ rP ;
CE
Where:
KV= 2
VJ
M
1+
V VAR
VJ
1
M
;Kƒ =
Figure 3. Optimum RS vs. Relative Frequency
Sensitivity for Different CE
1 ∆ƒ
ƒ ∆V VAR
VVAR is the varactor DC bias in the middle of the tuning range;
CE is the capacitance of the resonator capacitive branch in the
middle of the tuning range;
CJO, VJ, M are the parameters describing varactor
Ce = 8 pF
Ce = 3 pF
capacitance[1];
RP, RS are the series resistances of CPAR and CSER1; and
The results of this equation versus relative tuning sensitivity are
given in Figure 3 for different varactor processes. The low resistance SMV1763 process looks best for tuning sensitivities higher
than 1.5–2.0% per V.
The values of variables used in the circuit are given in the
variable equation module.
The default and test benches are shown in Figures 4 and 5
respectively.
KF is the relative tuning sensitivity.
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APPLICATION NOTE • APN1016
Figure 4. Default Bench for Libra IV
Figure 5. PCS VCO Test Bench
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APPLICATION NOTE • APN1016
Figure 6. SMV1763-079 SPICE Model for Libra IV
SMV1763-079 SPICE Model
The SMV1763-079 is a low series resistance, hyperabrupt
varactor diode. It has the industry’s smallest plastic package, SC79, with a body size of 47 x 31 x 24 mils (total length with leads
is 62 mils).
Table 2 describes the model parameters. It shows default values
appropriate for silicon varactor diodes that may be used by the
Libra IV simulator.
The SPICE model for the SMV1763-079 varactor diode, defined
for the Libra IV environment, is shown in Figure 6 with a
description of the parameters employed.
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APPLICATION NOTE • APN1016
Parameter
Unit
Default
IS
Saturation current (with N, determine the DC characteristics of the diode)
Description
A
1e-14
RS
Series resistance
Ω
0
N
Emission coefficient (with IS, determines the DC characteristics of the diode)
-
1
TT
Transit time
S
0
CJO
Zero-bias junction capacitance (with VJ and M define nonlinear
junction capacitance of the diode)
F
0
VJ
Junction potential (with VJ and M define nonlinear junction capacitance of the diode)
V
1
M
Grading coefficient (with VJ and M define nonlinear junction capacitance of the diode)
-
0.5
EG
Energy gap (with XTI, helps define the dependence of IS on temperature)
EV
1.11
XTI
Saturation current temperature exponent (with EG, helps define
the dependence of IS on temperature)
-
3
KF
Flicker noise coefficient
-
0
AF
Flicker noise exponent
-
1
FC
Forward bias depletion capacitance coefficient
-
0.5
BV
Reverse breakdown voltage
V
Infinity
1e-3
IBV
Current at reverse breakdown voltage
A
ISR
Recombination current parameter
A
0
NR
Emission coefficient for ISR
-
2
IKF
High injection knee current
A
Infinity
NBV
Reverse breakdown ideality factor
-
1
IBVL
Low-level reverse breakdown knee current
A
0
NBVL
Low-level reverse breakdown ideality factor
-
1
TNOM
Nominal ambient temperature at which these model parameters were derived
°C
27
FFE
Flicker noise frequency exponent
-
1
Table 2. Silicon Diode Default Values in Libra IV
According to the SPICE model, the varactor capacitance, CV, is a
function of the applied reverse DC voltage, VR, and may be
expressed as follows:
CV =
C JO
V
1+ R
VJ
M
This equation is a mathematical expression of the capacitance
characteristic. This model is accurate for abrupt junction
varactors (like the SMV1408); however for hyperabrupt junction
varactors the model is less accurate because the coefficients are
dependent on the applied voltage. To make the equation work
better for the hyperabrupt varactors, the coefficients were optimized for the best capacitance versus voltage fit, as shown in
Table 3.
+CP
Please note that in the Libra model above, CP is given in picofarads, while CJO is given in farads to comply with the default
unit system used in Libra.
Part Number
CJO (pF)
M
VJ (V)
CP (pF)
Ω)
RS (Ω
LS (nH)
SMV1763-079
7.6
90
120
1.6
0.6
1.1
Table 3. SPICE Parameters for SMV1763-079
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APPLICATION NOTE • APN1016
VCC (3 V)
VVAR
C9
100
R3
270
C1
100
MSL2
R1
3.9 k
V2
NE68619
V1
NE68119
SL1
C5
2.4
C4
1.0
C2
2.0
RF Out
C10
2.0
C8
100
C11
0.5
R2
6.8 k
MSL1
D1
C3
2.0
C6
0.5
R4
100
C7
0.75
Figure 7. PCS VCO Schematic (D1: SMV1763-079)
VCO Design, Materials and Layout
The VCO schematic diagram is shown in Figure 7. The circuit is
powered by a 3 V voltage source. The ICC current was established
near 8 mA. The RF output signal is coupled from the VCO through
the capacitor C10 (2 pF).
The PCB layout is shown in Figure 8. The board was made of
standard, 30 mil thick FR4 material. A more detailed drawing of
the VCO layout is shown in Figure 9 with the dimensions of
critical circuit components.
The bill of materials used is given in Table 4.
Designator
Value
Part Number
Footprint
C1
100 p
0402AU101KAT
0402
AVX
Manufacturer
C2
2p
0402AU2R0JAT
0402
AVX
C3
2p
0402AU2R0JAT
0402
AVX
C4
1p
0402AU1R0JAT
0402
AVX
C5
2.4 p
0402AU2R4JAT
0402
AVX
C6
0.5 p
0402AU0R5JAT
0402
AVX
C7
0.75 p
0402AU0R75JAT
0402
AVX
C8
100 p
0402AU101KAT
0402
AVX
C9
100 p
0402AU101KAT
0402
AVX
C10
2p
0402AU2R0KAT
0402
AVX
C11
0.5 p
0402AU0R5KAT
0402
AVX
D1
SMV1763-079
SMV1763-079
SC-79
Skyworks Solutions
R1
3.9 k
CR10-392J-T
0402
AVX/KYOCERA
R2
6.8 k
CR10-682J-T
0402
AVX/KYOCERA
R3
270
CR10-271J-T
0402
AVX/KYOCERA
R4
100
CR10-101J-T
0402
V1
NE68119
NE68119
SOT-416
NEC/CEL
V2
NE68619
NE68619
SOT-416
NEC/CEL
AVX/KYOCERA
Table 4. Bill of Materials
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APPLICATION NOTE • APN1016
Figure 8. PCB Layout
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APPLICATION NOTE • APN1016
Figure 9. Detailed Drawing of the PCS VCO Layout
Measurement and Simulation Results
The measured performance of this circuit and the simulated
results obtained with the model are shown in Figures 10 through
12. Phase noise measurements versus frequency offset are
shown in Figure 12. It shows greater than -90 dBc/Hz at 10 kHz
offset and greater than -110 dBc/Hz at 100 kHz offset. This 20
dB/decade slope is fairly constant up to 5–6 MHz. The measurements were done in the range below 7 MHz, offset because of
the 100 ns delay-line setup used. This measurement was made
using the Aeroflex PN9000 Phase Noise Test Set.
The measured frequency tuning response in Figure 10 shows
linear 60 MHz/V tuning in the 0.5–2.5 V range typical for battery
applications. The simulated frequency tuning response is very
similar to the measured response. VCO output power variation
versus tuning shows a divergence within ±2 dB between
measurement and simulation. This may be attributed to the VCO
model parameters, especially to the transistor model parameters.
These models are usually derived for small-signal amplifier applications, and may not necessary reflect the higher nonlinearity of
a VCO.
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2.5
0
2.0
100
-1
75
-2
50
-3
25
-4
Frequency Devation (MHz)
1
125
8
3
1.5
1.0
0.5
0
-2
-0.5
-7
0
-5
-25
-6
-50
-7
-75
-8
-2.0
-9
-17
-2.5
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
-100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Varactor Voltage (V)
Frequency (meas)
Power (meas)
Loop Power (simu)
Frequency (simu)
Power (simu)
-1.0
-1.5
Output Power (dBm)
150
Output Power (dBm)
Frequency Tuning (MHz)
APPLICATION NOTE • APN1016
-12
DC Power Supply Voltage (V)
Frequency (meas)
Power (meas)
Frequency (simu)
Power (simu)
Figure 10. Tuning Response Centered at 1750 MHz for VCC = 3 V,
VVAR = 1.5 V
Figure 11. DC Supply Pushing Response Centered at 1750 MHz
for VCC = 3 V, VVAR = 1.5 V
The simulated loop power shows constant behavior in the battery
range of 0.5–2.5 V and rapid degradation above it. This degradation may cause proportional degradation of phase noise
according to the Leeson equation.
pushing in the VCO may be further minimized by reducing the DC
bias current. However, the model supplied by the transistor
vendor does not reflect a negative pushing slope. The simulation
results shown in Figure 11 were obtained for a modified transistor model, which is available with the PCS VCO simulation
project file.
The DC supply pushing response, shown in Figure 11, shows
even larger differences between simulated and measured data.
The measured “slow down” of pushing near 2.4 V indicates that
Figure 12. Measured Phase Noise at 1750 MHz for VCC = 3 V, VVAR = 1.5 V
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APPLICATION NOTE • APN1016
List of Available Documents
VCO Related Application Notes
The PCS VCO Simulation Project Files for Libra IV.
APN1004, Varactor SPICE Models for RF VCO Applications.
The PCS VCO Circuit Schematic and PCB Layout for Protel, EDA
Client, 1998 version.
APN1006, A Colpitts VCO for Wide Band (0.95 GHz–2.15 GHz)
Set-Top TV Tuner Applications.
The PCS VCO PCB Gerber Photo-plot Files.
APN1005, A Balanced Wide Band VCO for Set-Top TV Tuner
Applications.
APN1007, Switchable Dual-Band 170/420 MHz VCO for Handset
Cellular Applications.
APN1012, VCO Designs for Wireless Handset and CATV Set-Top
Applications.
APN1013, A Differential VCO for GSM Handset Applications.
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APPLICATION NOTE • APN1016
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