Data Sheets - Skyworks Solutions, Inc.

DATA SHEET
SKY73101-11: 1930–1990 MHz High Performance
VCO/Synthesizer With Integrated Switch
Applications
Description
 2G, 2.5G, and 3G base station transceivers:
 GSM, EDGE, CDMA, WCDMA
Skyworks SKY73101-11 Voltage-Controlled Oscillator
(VCO)/Synthesizer is a fully integrated, high performance signal
source for high dynamic range transceivers. The device provides
ultra-fine frequency resolution, fast switching speed, and low
phase noise performance for 2G, 2.5G, and 3G base station
transceivers.
 General purpose RF systems
Features
The SKY73101-11 VCO/Synthesizer is a key building block for
high-performance radio system designs that require low power
and a fine step size. Reference clock generators with an output
frequency up to 52 MHz can be used with the SKY73101-11. A
functional block diagram is shown in Figure 1. As indicated in this
diagram, the reference frequency is divided down by 1, 2, 4, or 8
in the R1 divider, depending on the value of the reference divisor
input (R1). Refer to the Reference Input Divider section (page 10)
for more information.
 Frequency operation range: 1930 to 1990 MHz
 Process-tolerant compensation for VCO
 24-bit  fractional-N synthesizer
 Ultra-fine frequency resolution of 0.001 ppm
 Flexible reference frequency selection
 Three-wire serial interface up to 20 MHz clock frequency
 Integrated PLL supply regulation for spur isolation
The SKY73101-11 VCO/Synthesizer is provided in a compact,
38-pin Multi-Chip Module (MCM). The device package and pinout
are shown in Figure 2. Signal pin assignments and functional pin
descriptions are provided in Table 1.
Vtune
Varactor
 MCM (38-pin, 9 x 12 mm) SMT package (MSL3, 260 C per
JEDEC J-STD-020)
Z = 1:4
VCO Out +
Lr
Cal
2
Lr
2
2
Buffer
VCO Out –
RF Output
SW_EN
SR Out +
7
SR Out –
2
Vtune
cap [6:0]
Flag
FREF
PLL
Low Pass Filter
SP1
SC1
R1
Divider
RF
PFD
RF Charge
Pump
CLK
LE
DAT
3-Wire
Serial
Interface
CPO RF
R1
N
PS
RFIN
P/P+1
Prescaler
N
Divider
7
RFINB
LD
Mux
(LD/Test)
FN
ΔΣ
Modulator
Divide-by-2
ME
Digital
Coarse
Calibration
cap [6:0]
7
Calibration
Complete
S1040
Figure 1. SKY73101-11 Functional Block Diagram
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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1
GND
GND
GND
N/C
GND
GND
GND
38
VDD
GND
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
37
36
35
34
33
32
31
30
GND
3
27
N/C
SW_EN
4
26
GND
GND
5
25
GND
GND
6
24
GND
GND
7
23
FREF
GND
8
22
LD
GND
9
21
N/C
RF_OUT
10
20
GND
GND
11
12
13
14
15
16
17
18
19
LE
GND
DATA
28
CLK
2
GND
GND
GND
GND
N/C
29
GND
1
GND
GND
S958
Figure 2. SKY73101-11 Pinout– 38-Pin MCM Package
(Top View)
Table 1. SKY73101-11 Signal Descriptions
Pin #
1
Name
GND
Description
Ground
Pin #
20
Name
GND
Description
Ground
2
GND
Ground
21
N/C
No connection
3
GND
Ground
22
LD
Lock detect output
4
SW_EN
Synthesizer RF output switch enable
23
FREF
Frequency reference input
5
GND
Ground
24
GND
Ground
6
GND
Ground
25
GND
Ground
7
GND
Ground
26
GND
Ground
8
GND
Ground
27
N/C
No connection
9
GND
Ground
28
GND
Ground
10
RF_OUT
Synthesizer output
29
GND
Ground
11
GND
Ground
30
GND
Ground
12
GND
Ground
31
GND
Ground
13
GND
Ground
32
GND
Ground
14
N/C
No connection
33
N/C
No connection
15
GND
Ground
34
GND
Ground
16
GND
Ground
35
GND
Ground
17
CLK
Serial port clock
36
GND
Ground
18
DATA
Serial port data
37
VDD
+5 V power supply
19
LE
Serial port latch enable
38
GND
Ground
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Technical Description
The SKY73101-11 is a fractional-N frequency synthesizer using a
modulation technique. The fractional-N implementation
provides low in-band noise by having a low division and fast
frequency settling time. The device also provides programmable,
arbitrary fine frequency resolution. This compensates the
frequency synthesizer for crystal frequency drift.
Serial I/O Control Interface
The SKY73101-11 is programmed through a three-wire serial bus
control interface using four 26-bit words. The three-wire interface
consists of three signals: CLK (pin 17), LE (pin 19), and the bit
serial data line DATA (pin 18). The convention is to load data from
the most significant bit to the least significant bit (MSB to LSB). A
serial data input timing diagram is shown in Figure 3. Preset
timing parameter values are provided in Table 2.
Although the SKY73101-11 uses a 5 V DC supply, the internal
voltage regulator has a 3.3 V output for the PLL. Therefore, the
input DC voltage for the serial interface (CLK, DATA, and LE
signals) should be set to 3.3 V or lower.
Figure 4 depicts the serial bus, which consists of one 26-bit load
register and four separate 24-bit registers. Data is initially clocked
into the load register starting with the MSB and ending with the
LSB. The LE signal is used to gate the clock to the load register,
requiring the LE signal to be brought low before the data load.
Data is shifted on the rising edge of CLK.
The two final LSBs are decoded to determine which holding
register should latch the data. The falling edge of LE latches the
data into the appropriate holding register. This programming
sequence must be repeated to fill all four holding registers.
The specific hold register addresses are determined by the wd_0
and wd_1 parameters in the load register. These are the two
LSBs (bits [1:0]) as shown in Figure 4. Table 3 lists the four hold
registers and their respective addresses as determined in the load
register.
The dpll_ctrl parameter (bits [19:2] of Word 1) programs the
Digital Phase Locked Loop (DPLL) block. Each of the 18 bits that
comprise the dpll_ctrl parameter map directly to the signal ports
on the DPLL block as shown in Table 8 (except for the
dpll_flag_override and dpll_flag_value parameters).
Loading new data into a holding register not associated with the
synthesizer frequency programming does not reset or change the
synthesizer. The synthesizer should not lose lock before, during,
or after a new serial word load that does not change the
programmed frequency.
VCO Auto-Tuning Loop
A VCO auto-tuning loop provides the proper 7-bit coarse tuning
setting for the VCO switch capacitors in the VCO output. This sets
the oscillation frequency as close to target as possible before
starting fine analog tuning.
When VCO auto-tuning is enabled, the PLL performs a seven-step
successive approximation process to digitally tune the VCO close
to the final programmed frequency. Once that is complete, analog
tuning is switched in to lock the VCO to the programmed
frequency.
The auto-tuning loop is designed to compensate process variation
so that the VCO fine tuning range can be reduced to cover
temperature variation only. It significantly reduces VCO gain (Kv)
which reduces VCO phase noise.
There are two conditions that enable the VCO auto-tuning
function: a Power-On-Reset (POR) and a change in frequency. The
difference in the program flow under each of these conditions is
illustrated in Figure 5. Under either condition, dpll_en (bit [20] of
Word 1) should first be cleared so that a rising edge pulse can be
generated. Following this pulse, set dpll_en to enable VCO autotuning.
A POR timing diagram is shown in Figure 6. VCO auto-tuning
details in the frequency and time domains are shown in Figure 7.
The contents of each word in the load register are used to
program the four hold registers described in Tables 4 through 7.
DATA
tDHD
tDSU
tCKH
tCKL
CLK
tCLE
tLEC
tLEW
LE
S1053
Figure 3. SKY73101-11 Serial Data Input Timing Diagram (MSB First)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 2. CLK, DATA, LE Preset Timing Parameters
Parameter
Value
Input high voltage (VIH)
1.6 V
Input low voltage (VIL)
0.3 V
Input current (lDIG)
1 A (maximum)
Clock frequency
15 MHz (maximum)
Clock high (tCKH)
15 ns (minimum)
Clock low (tCKL)
15 ns (minimum)
Data set up (tDSU)
20 ns (minimum)
Data hold (tDHD)
10 ns (minimum)
Clock to latch enable (tCLE)
20 ns (minimum)
Latch enable width (tLEW)
15 ns (minimum)
Latch enable to clock (tLEC)
15 ns (minimum)
Word length
26 bits
Number of words
4
Current drain
2 A
Power-On
Preset
CLK
DATA
Load
Register
Bits [25:2]
(Words 0-3, bits [25:0])
Operation
Mode
Register
Latch
Word 0
Bits [25:2]
Word 1
Bits [25:2] Frequency
Auto
Calibration
Control
Register
Control 1
Register
Latch
Latch
Word 2
Bits [25:2]
Frequency
Control 2
Register
Word 3
Bits [25:2]
Latch
Words 0-3
Bits [1:0]
LE
2 LSB Decode
(Register Address,
Bits [1:0])
S918
Figure 4. Serial Bus Block Diagram
Table 3. SKY73101-11 Hold Registers and Addresses
Hold Register Name
Operation Mode
Hold Register Address (Binary) in Load Register Words
Bit [1]
Bit [0]
0
0
Auto Calibration Control
0
1
Frequency Control 1
1
0
Frequency Control 2
1
1
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 4. Load Register Word 0 (Programs the Operation Mode Register) (1 of 2)
Parameter
Function
wd_0, wd_1
Address bits [1:0]. Must be set to 00b (see
Table 3)
cp_output
Charge pump setting [4:2]
State Description
Recommended
Operational Value
(Binary)
00
Application
dependent
Bits [4:2]:
0 0 0 = 200 A
0 0 1 = 400 A
0 1 0 = 600 A
0 1 1 = 800 A
1 0 0 = 1000 A
1 0 1 = 1200 A
1 1 0 = 1400 A
1 1 1 = 1600 A
cp_delay
Charge pump delay [6:5]
00
Bits [6:5]:
0 0 = 2 nsec
0 1 = 4 nsec
1 0 = 7 nsec
1 1 = 9 nsec
NOTE: this device is fixed at 2 nsec.
pd_polar
Polarity of phase detector [7]
Bit [7]:
0
0 = Negative
1 = Positive
NOTE: this device is fixed at negative polarity.
cp_tristate
Tri-state selection for the transmit PLL
charge pump output [8]
Bit [8]:
0
0 = Charge pump in normal functional mode
1 = Charge pump disabled/tri-stated
rsvd
Reserved [9]
Reserved
sd_sel
Internal operating voltage control bit for 
synthesizer [10]
Bit [12] Bit [11] Bit [10]: N-Cntr/R1-Divider ΣΔ Mod
Voltage
Voltage
Note: this bit needs to be programmed
together with bits [11] and [12].
nr_sel
Internal operating voltage control bit for Ncounter and R1 divider [11]
0
1
1
1
1
0
X
0
0
1
1
X
0
1
0
1
=
=
=
=
=
0V
1.8 V
1.8 V
2.4 V
2.4 V
100
0V
1.8 V
2.4 V
1.8 V
2.4 V
This bit needs to be programmed together with bits [10] and [12].
–
This bit needs to be programmed together with bits [10] and [11].
–
Bits [14:13]:
11
See sd_sel parameter (bit [10])
pll_en
Internal operating voltage control bit for PLL
[12]
See sd_sel parameter (bit [10])
ref_bw_sel
Reference buffer bandwidth [14:13]
0 0 = 20 MHz
0 1 = 30 MHz
1 0 = 40 MHz
1 1 = 50 MHz
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected]rksinc.com • www.skyworksinc.com
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 4. Load Register Word 0 (Programs the Operation Mode Register) (2 of 2)
Parameter
test_mux
Function
Lock detect and diagnostic output select
[17:15]
State Description
Recommended
Operational Value
(Binary)
000
Bits [17:15]:
0 0 0 = Lock detect output
0 0 1 = R-divider output
0 1 0 = N-divider output
0 1 1 = Not used
1 0 0 = Not used
1 0 1 = Not used
1 1 0 = Not used
1 1 1 = DPLL test
rsvd
Reserved [20:18]
Reserved
000
pre_curr_sel
Prescaler current bias [22:21]
Bits [22:21]:
00
0 0 = 20 A
0 1 = 22 A
1 0 = 24 A
1 1 = 26 A
prescale_sel
Prescaler mode select [23]
Bit [23]:
Application
dependent
0 = Prescaler in 8/9 divide mode
1 = Prescaler in 16/17 divide mode
rsvd
Reserved [25:24]
Reserved
00
Table 5. Load Register Word 1 (Programs the Auto Calibration Control Register)
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
wd_0, wd_1
Address bits [1:0]. Must be set to 01b (see
Table 3)
01
dpll_ctrl
DPLL control [19:2]
Refer to Table 8
–
dpll_en
Digital PLL enable flag [20]
0 = Disable DPLL
1 = Enable DPLL
Refer to Figure 5
rsvd
Reserved [25:21]
Reserved
00000
Table 6. Load Register Word 2 (Programs the Frequency Control 1 Register) (1 of 2)
Parameter
Function
wd_0, wd_1
Address bits [1:0]. Must be set to 10b (see
Table 3)
rdiv
Reference divider ratio [3:2]
State Description
Recommended
Operational Value
(Binary)
10
Bits [3:2]:
00=8
01=4
10=2
11=1
rsvd
Reserved [5:4]
Reserved
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Application
dependent
–
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 6. Load Register Word 2 (Programs the Frequency Control 1 Register) (2 of 2)
Parameter
ndiv
Function
N-divider/prescaler mode for control of M
and A counters [15:6]
State Description
Recommended
Operational Value
(Binary)
Application
dependent
Bits [15:6]:
Bits [15:10]
Bits [9:6]
M bits [5:0]
M bits [5:0]
A bits [3:0] = use 16/17 prescaler
A bits [2:0] = use 8/9 prescaler
Note: The six MSBs of ndiv denote the M counter value and the four
LSBs denote the A counter value. For the 8/9 prescaler mode, the A
counter value requires only three bits. Therefore, bit [9] of ndiv is a
“don’t care” bit.
rsvd
Reserved [16]
mod_reset_f
Modulator reset/fractional mode select [17]
Reserved
0
Bit [17]:
1
0 = Modulator is reset or disabled
1 = Modulator is in fractional mode
fract_int_sel
Fractional/integer mode select [18]
Bit [18]:
1
0 = Modulator is in integer mode
1 = Modulator is in fractional mode
rsvd
Reserved [19]
Reserved. This bit should always remain set (logic high).
me
Modulus extender [23:20]
These four bits need to be programmed together with bits [12:2] of
Word 3. Bits [23:20] represent the four LSBs ([3:0]) of the 15-bit
modulus extender value (ME [14:0]). Refer to the Synthesizer
Programming section of this Data Sheet for further information.
rsvd
Reserved [25:24]
Reserved
1
Application
dependent
00
Table 7. Load Register Word 3 (Programs the Frequency Control 2 Register)
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
wd_0, wd_1
Address bits [1:0]. Must be set to 11b (see
Table 3)
11
me
Modulus extender [12:2]
These 11 bits need to be programmed together with bits [23:20] of
Word 2. Bits [12:2] represent the 11 MSBs ([14:4]) of the 15-bit
modulus extender value (ME [14:0]). Refer to the Synthesizer
Programming section of this Data Sheet for further information.
Application
dependent
fn
Fractional divisor code [20:13]
Bits [20:13] represent the 8-bit fractional divisor code (FN [7:0]).
Refer to the Synthesizer Programming section of this Data Sheet for
information.
Application
dependent
rsvd
Reserved [23:21]
These three bits should always remain cleared (logic low).
0
rsvd
Reserved [25:24]
Reserved
00
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 8. DPLL Digital Control Bits
Serial Port Name
Load Register Word 1 Bit
Recommended Operating Value (Binary)
dpll_clk_dly(0)
2
0
dpll_clk_dly(1)
3
0
dpll_temp_comp(0)
4
0
dpll_temp_comp(1)
5
0
dpll_temp_comp(2)
6
0
dpll_temp_comp(3)
7
0
dpll_temp_comp(4)
8
0
dpll_temp_comp_en
9
0
dpll_ext_test(0)
10
0
dpll_ext_test(1)
11
0
dpll_ext_test(2)
12
0
dpll_ext_test(3)
13
0
dpll_ext_test(4)
14
0
dpll_ext_test(5)
15
0
dpll_ext_test(6)
16
0
dpll_ext_test(7)
17
0
dpll_flag_override
18
0
dpll_flag_value
19
0
DC Power On
Frequency Change
Hardware Auto Reset
Clear dpll_en
(Word 1, Bit [20])
Clear dpll_en
(Word 1, Bit [20])
Send Word 0, 1, 2, and 3
Set dpll_en
(Word 1, Bit [20])
Send Word 1
Send Only Changed
Words
Set dpll_en
(Word 1, Bit [20])
Send Word 1
Lock on New Frequency
Lock on New Frequency
S998
Figure 5. VCO Auto-Tuning Enable Process Flow Due to POR or Frequency Change
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Word 0
Word 1 (Bit [20] low)
Word 2
Word 3
Word 1 (Bit [20] high)
CLK
DATA
D25
D24
D1
D0
D25
D24
D1
D0
D25
D24
D1
D0
D25
D24
D1
D0
D25
D24
D1
D0
LE
Phase Settling Time
LD
S1296
Figure 6. POR Timing Diagram
1976
1974
1972
1970
1968
1966
Frequency (MHz)
1964
1962
1960
1958
1956
1954
1952
1950
1948
1946
Analog Tune
1944
1942
Digital Tune
(VCO Auto-Tuning)
1940
0
50
100
150
200
250
300
350
400
450
Time (μs)
500
S2150
Figure 7. VCO Auto-Tuning @ 1960 MHz Frequency Settling
VCO Prescalers
The VCO prescalers divide the VCO output signal by either 16/17
or 8/9. The modulator determines whether to divide by 16 or
17 in the 16/17 mode, or whether to divide by 8 or 9 in the 8/9
mode. The 8/9 mode provides the best performance for the
SKY73101-11.
N-Counter
The N-counter consists of two asynchronous ripple counters, a
6-bit M-counter and a 4-bit A-counter. The M-counter determines
the counts using the lower division ratio in the prescaler (8 or 16);
the A-counter determines the counts using the upper division ratio
(9 or 17).
The total N-counter divider ratio for the 8/9 mode is 56 (8 × 7)
minimum; for the 16/17 mode, the ratio is 240 (16 × 15)
minimum.
By changing the counter setting at each reference clock cycle, the
Modulated Fractional Divider (MFD) achieves the desired noise
shaping.
VCO MFD Block
The MFD block divides down the prescaler output to the Phase
Locked Loop (PLL) reference frequency. A third order cascaded
modulation technique minimizes spurs through randomization
of the division ratio.
The MFD block controls the division ratio by dynamically
programming the M and A counters in the N-counter.
Phase Detector and Charge Pump
The phase detector and charge pump detect and integrate the
phase and frequency errors of the divided down VCO output
versus the reference clock. This results in a feedback adjustment
of the control voltage for the VCO.
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Lock Detect
Lock detection circuitry provides a CMOS logic level indication
when the PLL is frequency locked (high when locked). Normally,
pin 22 (LD) is used for lock detect output. This pin can also be
programmed as the R1 divider output, N-divider output, or DPLL
test output. Pin 22 is controlled by Word 0, bits [17:15].
Reference Input Divider
Because of the way the  modulator is implemented in the
SKY73101-11, the number 3.5 must be added to the division
number to obtain the final division ratio.
The calculated value for DTotal can then be used to determine the
correct synthesizer frequency, RF:
RF 
FREF
 DTotal
R1
(2)
Where: FREF = the reference frequency
The R-counter (reference input clock divider) consists of three
divide-by-two blocks and one multiplexer controlled by the
rdiv[3:2] parameter in Word 2. The R1 divider is used to select a
divide-by-one, two, four, or divide-by-eight function.
The integral loop filter (see Figure 1) is designed to operate at an
internal comparison frequency of approximately 6.5 MHz. The
input reference signal must be divided using the rdiv [3:2] bits in
Word 2 to closely match this frequency. Further optimization of
the loop filter bandwidth may be accomplished using the
cp_output [4:2] bits in Word 0.
R1 = the reference divider radio
The 6-bit M-counter and the 4-bit A-counter portions of the Ncounter are calculated according to the following relationships:
Nactual is the actual N-counter value and is the integer portion of
(DTotal – 3.5):
Nactual = Mactual × P + Aactual
If:
M = Mactual (binary number, fit to six bits)
A = Aactual (binary number, fit to four bits)
Then: N = M × 24 + A
Reference Buffer Bandwidth
The two-bit parameter ref_bw_sel adjusts the operating point of
the input buffer to compensate for different reference signal
sources. Generally the best setting is 50 MHz, but this could vary
depending on the source used.
Synthesizer Output Switch
An on-chip switch is integrated into the SKY73101-11 RF output
after the balun and is controlled by the SW_EN signal (pin 4) as
indicated below:
SW_EN Input
Synthesizer Output
High
On
Low
Off
FNactual = the actual fractional divisor
P = 24 = 16
In this case, N is the same as Nactual, M is equal to the six MSBs of
Nactual, and A is equal to the four LSBs of Nactual.
If the 8/9 prescaler is used:
P=8
The fractional divisor code (FN) sets the fractional-N modulo up to
256 modulo according to the following equation:
To program the synthesizer to the correct frequency, values for
the N-counter (both M and A portions), fractional divisor (FN), and
fractional modulus extender (ME) are needed. These values are
used to determine the total divider ratio, DTotal, according to
Equation 1:
Where: Nactual = the actual value of the N-counter
The synthesizer has a selectable prescaler of 8/9 or 16/17. If the
16/17 prescaler is used:
NOTE: The minimum actual N counter value for the 8/9 mode is
8 x 7 = 56, and for the 16/17 mode is 16 x 15 = 240.
Synthesizer Programming
DTotal = Nactual + FNactual + MEactual + 3.5
Where: N is the number to be programmed into the N-counter.
Here, N is not equal to Nactual. The A-counter portion only uses the
three LSBs (the 4th bit of the A-counter is a “don’t care” bit).
The switch provides >50 dB isolation at the synthesizer RF
output. This allows the SKY73101-11 to be used for GSM
applications.
(1)
 1
1
FN actual  D7    D6  2
2
2

 1
  D5 
3

2

 

  
 1
 D0  8
2



(4)
The value of FN is equal to the binary representation of 256 (or 28)
 FNactual, or:
FN = D7  27 + D6  26 + D5  25+ . . . D0
The fractional modulo can be extended up to 223 using the modulo
extender (ME) if required:
MEactual = D14(1/29) + D13(1/210) + D12(1/211) + . . . + D0(1/223)
MEactual = the actual fractional modulus extender
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
The value of ME is equal to the binary representation of the
integer part of 223  MEactual, or:
ME = D14  214 + D13  213 + D12  212 + . . .D0
Example :
A desired synthesizer frequency of 1960 MHz is required using a
crystal frequency of 52 MHz and an 8/9 prescaler. Since the
maximum internal reference frequency is 25 MHz, the crystal
frequency needs to be divided; a reference divider ratio of 8 is
used for this example.
Restating Equation (2) as a function of DTotal:
DTotal = (1960  8)/52 = 301.538461538461
Where: RF = 1960
R1 = 8
FREF = 52
Determine Nactual by subtracting 3.5 from DTotal and removing the
fractional portion:
DTotal – 3.5 = 298.038461538461
Using Equation (3):
Nactual = 298 = Mactual  P + Aactual
where: Mactual = 37
P=8
Multiply this result by 8388608 (the 23-bit  modulator value,
223) and remove the fractional portion to determine the value of
ME:
0.003305288461  8388608 = 27726.769226252288
ME = 27726 = 110110001001110b (the value programmed).
Refer to Tables 6 and 7 for the location of the resulting bits in the
ME parameter.
Package and Handling Information
Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipping. Instructions on the
shipping container label regarding exposure to moisture after the
container seal is broken must be followed. Otherwise, problems
related to moisture absorption may occur when the part is
subjected to high temperature during solder assembly.
The SKY73101-11 is rated to Moisture Sensitivity Level 3 (MSL3)
at 260 C. It can be used for lead or lead-free soldering. For
additional information, refer to Skyworks Application Note, PCB
Design and SMT Assembly/Rework Guidelines for MCM-L
Packages, document number 101752.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format.
Aactual = 2
Circuit Design Considerations
M = Mactual = 37 = 100101b (the six MSBs)
A = Aactual = 2 = 0010b (the four LSBs)
N = M  24 + A = 1001010010b (the value programmed)
Multiply the fractional portion that was removed in the previous
step by 256 and remove the fractional portion of the result to
determine FN:
0.038461538461  256 = 9.846153846016
FN = 9 = 00001001b (the value programmed)
Divide FN by 256 to determine the actual fractional part, FNactual:
FNactual = 9/256 = 0.03515625
Subtract this result from the fractional portion of DTotal – 3.5 to
determine the actual fractional modulus extender, MEactual:
The following design considerations are general in nature and
must be followed regardless of final use or configuration
1. Paths to ground should be made as short and as low
impedance as possible.
2. The ground pad of the SKY73101-11 provides critical
electrical grounding requirements. Design the connection to
the ground pad to provide the best electrical connection to the
circuit board. Multiple vias to the grounding layer are
recommended to connect the top layer ground area to the
main ground layer.
3. Skyworks recommends including external bypass capacitors
on the VDD voltage input (pin 37) of the device. These
capacitors should be placed as close as possible to the VDD
input pin.
4. A 50  impedance trace is needed for the RF_OUT (pin 10)
line.
MEactual = (DTotal – 3.5 – Nactual) – FNactual
= 0.038461538461 – 0.03515625
= 0.038461538461
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11
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Electrical and Mechanical Specifications
Electrostatic Discharge (ESD) Sensitivity
The absolute maximum ratings of the SKY73101-11 are provided
in Table 9. The recommended operating conditions are specified
in Table 10 and electrical specifications are provided in Table 11.
Spur suppression measurements are provided in Table 12.
Measurement plots for single sideband phase noise and settling
time are shown in Figures 8 and 9, respectively.
The SKY73101-11 ESD threshold level is 250 VDC for the RF_OUT
pin and 2000 VDC for all other pins using Human Body Model
(HBM) testing.
To avoid latent or visible ESD damage, always follow proper ESD
handling precautions.
Typical performance characteristics of the SKY73101-11 are
illustrated in Figures 10 through 27.
A typical application schematic for the SKY73101-11 is provided
in Figure 28. The PCB layout footprint for the SKY73101-11 is
provided in Figure 29. Figure 30 shows the package dimensions
for the 38-pin MCM and Figure 31 provides the tape and reel
dimensions.
Table 9. SKY73101-11 Absolute Maximum Ratings (Note 1)
Parameter
Min
Typical
Max
Units
VCC
0
5.0
5.5
V
0
4.6
V
Operating temperature
TOP
–40
+85
°C
Storage temperature
TST
–40
+150
°C
Supply voltage
Symbol
Input voltage (CLK, DATA, LE)
Note 1: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal values. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times. All pins
are rated for a Human Body Model (HBM) Class 1A ESD withstand threshold voltage (250 V).
Table 10. SKY73101-11 Recommended Operating Conditions
Parameter
Min
Typical
Max
Units
4.75
5.00
5.25
V
Input voltage (CLK, DATA, LE) (Note 1):
Low level
High level
1.4
3.3
0.6
3.6
V
V
Output voltage (LD) with 18 k load from
VCC PLL:
Low level, unlocked
High level, unlocked
0.4
2.4
V
V
1.5
Vp-p
0.8
V
V
Supply voltage
Symbol
VCC
Reference frequency input voltage (FREF,
pin 23)
RF output switch enable:
High
Low
FREFIN
0.5
SWENH
SWENL
2.2
Load connected to RF output
1.0
50 , maximum VSWR (load input) 2.0:1, all phases
Note 1: The CLK, DATA, and LE signals are internally 3.3 V DC. DO NOT drive these signals to 5 V.
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 11. SKY73101-11 Electrical Characteristics (Note 1) (Note 2)
(VCC = 5 V, TC = 25 °C, Charge Pump Current = 1600 A, FREF = 52 MHz, Reference Input Divider = 8, Prescale Divider = 8/9, Unless
Otherwise Noted)
Parameter
Symbol
Test Conditions
Oscillation frequency
Min
Typical
1930
Max
Units
1990
MHz
52
MHz
Reference frequency
13
Phase detector frequency
6.5
MHz
PLL loop bandwidth
25
kHz
Output level
–10
Output impedance
–8.6
–6.0

50
Output VSWR
2:1
Reference frequency input (FREF)
impedance
Integrated RMS phase noise
–46
–77
100 Hz to 100 kHz
Single sideband phase noise offset:
@ 10 kHz
@ 200 kHz
@ 400 kHz
@ 800 kHz
@ 1.8 MHz
@ 3.0 MHz
@ 6.0 MHz
–

470
Harmonic suppression:
2nd harmonic
3rd harmonic
dBm
–85
–121
–132
–139
–146
–150
–155
PLL-reference spurious suppression
–40
–69
dBc
dBc
1
degrees RMS
–80
–114
–124
–135
–142
–146
–151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–100
dBc
s
Frequency settling time
Within 2 kHz
240
375
Phase settling time
Within 5 deg
272
450
s
1.5
5
degrees
Peak phase error
Switch isolation
+45
Current consumption
+47
120
dBc
135
mA
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Note 2: Characterized performance may change if the SKY73101-11 is configured differently than the test conditions specified here. This characterization used a 6.5 MHz fixed comparison
frequency for the PLL loop filter. The PLL synthesizer is programmable up to a maximum comparison frequency of 26 MHz but with degraded performance.
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13
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Table 12. SKY73101-11 Spur Suppression Measurements
(VCC = 5 V, TC = 25 °C, Charge Pump Current = 1600 A, FREF = 52 MHz, Reference Input Divider = 8, Prescale Divider = 8/9, Unless
Otherwise Noted)
Frequency (MHz)
Spurious Power (kHz)
1930
1960
1990
 200
No spur
No spur
No spur
 400
498.51 kHz,
–92 dBc
No spur
No spur
 600
No spur
No spur
No spur
 800
No spur
No spur
No spur
 1000
2575.45 kHz,
–95 dBc
No spur
1000.00 kHz,
–91 dBc
 3000
No spur
6515.59 kHz,
–100 dBc
No spur
–60
–70
1930 MHz
1990 MHz
–80
Phase Noise (dBc/Hz)
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
0.1
1
10
100
1000
10000
Offset Frequency (kHz)
S1087
Figure 8. Single Sideband Phase Noise Measurements
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
90
80
1930 MHz
1990 MHz
70
60
50
Relative Phase (deg)
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
100
200
300
400
500
Time (μs)
S1088a
–5
–6
–5
–6
–7
–8
–7
–8
POUT (dBm)
POUT (dBm)
Figure 9. Phase Settling Time Measurements
–9
–10
–11
–12
–14
–15
1930
1945
1960
1975
–11
–12
+85 °C
+25 °C
–40 °C
–13
–9
–10
5.25 V
5.00 V
4.75 V
–13
–14
–15
1930
1990
1945
Figure 10. Output Power vs Frequency and Temperature
1990
2.0
1.8
1.8
Phase Noise (deg RMS)
Phase Noise (deg RMS)
1975
Figure 11. Output Power vs Frequency and Supply Voltage
2.0
1.6
1.4
1.2
1.0
0.8
0.6
+85 °C
+25 °C
–40 °C
0.4
0.2
0
1930
1960
RF Frequency (MHz)
RF Frequency (MHz)
1945
1960
1975
1.6
1.4
1.2
1.0
0.8
0.6
0.4
5.25 V
5.00 V
4.75 V
0.2
1990
RF Frequency (MHz)
Figure 12. Integrated Phase Noise vs Frequency and Temperature
0
1930
1945
1960
1975
1990
RF Frequency (MHz)
Figure 13. Integrated Phase Noise vs Frequency and Supply
Voltage
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
500
Phase Settling Time (μs)
Phase Settling Time (μs)
500
400
300
200
+85 °C
+25 °C
–40 °C
100
0
1930
1945
1960
1975
400
300
200
0
1930
1990
5.25 V
5.00 V
4.75 V
100
1945
RF Frequency (MHz)
Figure 14. Phase Settling Time vs Frequency and Temperature
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
–84
–86
+85 °C
+25 °C
–40 °C
–88
1945
1960
1975
–82
–84
–86
5.25 V
5.00 V
4.75 V
–88
–90
1930
1990
1945
RF Frequency (MHz)
–117
–117
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
–115
–119
–121
+85 °C
+25 °C
–40 °C
–123
1960
1975
–121
5.25 V
5.00 V
4.75 V
–123
–125
1930
1990
1945
1960
1975
1990
RF Frequency (MHz)
Figure 18. Phase Noise @ 200 kHz Offset vs Frequency and
Temperature
Figure 19. Phase Noise @ 200 kHz Offset vs Frequency and
Supply Voltage
–120
Phase Noise (dBc/Hz)
–120
–124
–128
–132
+85 °C
+25 °C
–40 °C
–136
1945
1960
1975
–124
–128
–132
5.25 V
5.00 V
4.75 V
–136
1990
RF Frequency (MHz)
Figure 20. Phase Noise @ 400 kHz Offset vs Frequency and
Temperature
–140
1930
1945
1960
1975
1990
RF Frequency (MHz)
Figure 21. Phase Noise @ 400 kHz Offset vs Frequency and
Supply Voltage
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1990
–119
RF Frequency (MHz)
Phase Noise (dBc/Hz)
1975
Figure 17. Phase Noise @ 10 kHz Offset vs Frequency and Supply
Voltage
–115
1945
1960
RF Frequency (MHz)
Figure 16. Phase Noise @ 10 kHz Offset vs Frequency and
Temperature
–140
1930
1990
–80
–82
–125
1930
1975
Figure 15. Phase Settling Time vs Frequency and Supply Voltage
–80
–90
1930
1960
RF Frequency (MHz)
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–130
–130
–134
–134
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
–138
–142
+85 °C
+25 °C
–40 °C
–146
–150
1930
1945
1960
1975
–138
–142
–150
1930
1990
5.25 V
5.00 V
4.75 V
–146
1945
Figure 22. Phase Noise @ 800 kHz Offset vs Frequency and
Temperature
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
–143
–147
–151
1945
1960
1975
–143
–147
–151
–155
1930
1990
5.25 V
5.00 V
4.75 V
–139
1945
RF Frequency (MHz)
1960
1975
1990
RF Frequency (MHz)
Figure 24. Phase Noise @ 1800 kHz Offset vs Frequency and
Temperature
Figure 25. Phase Noise @ 1800 kHz Offset vs Frequency and
Supply Voltage
–145
–145
+85 °C
+25 °C
–40 °C
–149
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
1990
–135
+85 °C
+25 °C
–40 °C
–139
–153
–157
–149
–153
–157
5.25 V
5.00 V
4.75 V
–161
–161
–165
1930
1975
Figure 23. Phase Noise @ 800 kHz Offset vs Frequency and
Supply Voltage
–135
–155
1930
1960
RF Frequency (MHz)
RF Frequency (MHz)
1945
1960
1975
1990
RF Frequency (MHz)
Figure 26. Phase Noise @ 6000 kHz Offset vs Frequency and
Temperature
–165
1930
1945
1960
1975
1990
RF Frequency (MHz)
Figure 27. Phase Noise @ 6000 kHz Offset vs Frequency and
Supply Voltage
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
C2
10 nF
6
7
8
9
10
GND
GND
GND
N/C
GND
GND
29
GND
GND
GND
GND
GND
N/C
SW_EN
GND
GND
GND
GND
GND
GND
FREF
28
27
26
25
24
23
22
GND
LD
GND
N/C
RF_OUT
GND
Frequency
Reference
Lock Detect
21
20
GND
RF Output
(50 Ω Controlled
Impedance Line)
30
11
12
13
14
15
16
17
18
LE
5
31
DATA
4
32
CLK
RF Output
Switch Control
33
GND
3
34
GND
2
35
N/C
1
36
GND
37
GND
38
GND
+
VDD
C1
10 μF
GND
+5 V
From Regulator
19
Latch Enable
Data
Clock
S1104
Figure 28. SKY73101-11 Typical Application Schematic
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DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
1.1
0.95
9.4
0.075
2X 0.2
Stencil aperture size for center
ground pads should be 80% to
100% (by area) of the solder
mask opening of the package.
Pin 1
0.075
0.8 0.95
Stencil and
Metallization
Component Outline
Soldermask Opening
SMT Pad Detail
Scale: 2X
1 X This Rotation
1X Rotated 180o
0.5 Typ
12X 0.1375
12.4
0.65
36X 1.4
0.5
1.0 Pitch
Typ
0.075
0.2
24X 0.28
0.075
0.8
0.95
Stencil and
Metallization
24X 0.27
Component Outline
12X 0.1375
SMT Pad Detail
Scale: 2X
7 X This Rotation
7X Rotated 180o
10X Rotated 90o CW
10X Rotated 90o CCW
Stencil Aperture
Top View
9.55
6.88
1.1
0.95
0.075
Component Outline
Soldermask Opening
36X 0.9
Component Outline
0.075
Pin 1
2X 0.2
0.95 0.8
Stencil and
Metallization
Soldermask Opening
SMT Pad Detail
Scale: 2X
1 X This Rotation
1X Rotated 180o
0.5 Typ
12.55
9.4
9.88
1.0 Pitch
Typ
2X 4.3
(2.8)
Pin 1
0.25
Typ
2X 5.8
Component Outline
Solder Mask Opening
Top View
(3.4)
0.5 Typ
12.4
(4.3)
1.0 Pitch
Typ
Thermal Via Array.
∅0.3 mm on 0.6 mm pitch.
Additional vias in common ground
pad will improve thermal and
electrical performance.
NOTE: thermal vias should be tented
and filled with solder mask,
30-35 μm Cu plating recommended.
Component Outline
Metallization
Top View
All measurements are in millimeters
Note: The cross-hatched area represents the merger of the center
ground pad +24 individual I/O ground pads. All I/O ground
pads should have at least one via connected to internal ground
planes for optimum electrical performance.
S1285
Figure 29. PCB Layout Footprint for the SKY73101-11 9 x 12 mm MCM
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Pin 1 Indicator
9
B
2X 2.937
2X 1.762
2X 0.587
4X 1
4X 2
4X 3
24X 4.4
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
0
C
0.1 A B C
Pin 38
C
18X 5.9
38X SMT Pad
Pin 1 Indicator
See Detail D
Pin 1
4X 4.5
A
4X 3.5
4X 2.5
4X 1.5
4X 0.5
0
12
12X 0.837
See Detail E
12X 2.512
12X 4.187
36X Solder Mask Openings
B
A
0.2 A B C
1.7 ± 0.1
0.15 A B C
0.1
Side View
Top View
0.5 ± 0.1
Bottom View
(0.1)
Metal Pad Edge
0.65 ± 0.1
2X (0.1)
0.5 ± 0.05
Metal Pad Edge
0.5 ± 0.1
0.5 ± 0.1
Solder Mask Edges
2X (0.1)
0.65 ± 0.1
Metal Pad Edge
Detail A
Detail B
Detail C
SMT Pad
Scale: 2X
10X This Rotation
10X Rotated 180o
7X Rotated 90o CW
7X Rotated 90o CCW
SMT Pad
Scale: 2X
1X This Rotation
1X Rotated 180o
SMT Pad
Scale: 2X
1X This Rotation
1X Rotated 180o
1
1
0.2 x 0.2
1.5
1.5
Solder Mask Edges
Solder Mask Edges
Detail D
Detail E
Scale: 2X
Scale: 2X
All measurements are in millimeters.
Dimensioning and tolerancing according to ASME Y14.5M-1994.
Figure 30. SKY73101-11 38-Pin MCM Package Dimensions
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S960
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
12.00 (P1)
4.00 (Po)
2.00 ± 0.05
∅1.55 ± 0.05
0.30 ± 0.05 (T)
Pin #1
indicator
1.75 ± 0.10
A
11.50 ± 0.05
B
24.00 ± 0.30
12.30 (Bo)
A
B
9.30 (Ao)
2.00 (Ko)
∅1.50 Min.
B
Notes:
1. Carrier tape material: black conductive polystyrene
2. Cover tape material: transparent conductive PSA
3. Cover tape size: 21.3 mm width
4. Po/P1 10 pitches cumulative tolerance on tape: ±0.20 mm
5. Ao and Bo measurement point to be 0.30 mm from bottom pocket
6. All measurements are in millimeters
A
S1832
Figure 31. SKY73101-11 Tape and Reel Dimensions
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200724C • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 8, 2010
21
DATA SHEET • SKY73101-11 VCO/SYNTHESIZER
Ordering Information
Model Name
SKY73101-11 1930-1990 MHz VCO/Synthesizer
Manufacturing Part Number
SKY73101-11
Evaluation Board Part Number
TW18-D910
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September 8, 2010 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200724C