Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Description SOT-26 The SR05-4A is designed to protect voltage sensitive components from ESD and transient voltage events. Excellent clamping capability, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Feature Functional Diagram u 300 Watts Peak Pulse Power per Line (tp=8/20μs) u Protects four I/O lines u Low clamping voltage u Working voltages : 5V u Low leakage current u IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact) u IEC61000-4-4 (EFT) 40A (5/50ηs) u IEC61000-4-5 (Lightning) 3A (8/20μs) Applications u USB 2.0 Power and Data Line Protection u Video Graphics Cards u Monitors and Flat Panel Displays u Digit Video Interface (DVI) u 10/100/1000 Ethernet u Notebook Computers u SIM Ports u ATM Interfaces Mechanical Characteristics u JEDEC SOT-26 Package u Molding Compound Flammability Rating : UL 94V-0 u Weight 16.0 Milligrams (Approximate) u Quantity Per Reel : 3,000pcs u Reel Size : 7 inch u Lead Finish : Lead Free Mechanical Characteristics Symbol Parameter Value Units 300 W PPP Peak Pulse Power (tp=8/20μs waveform) TL Lead Soldering Temperature 260 (10sec) ºC TSTG Storage Temperature Range -55 to +150 ºC Operating Temperature Range -55 to +150 ºC TJ Air Discharge ±15 Contact Discharge ±8 IEC61000-4-2 (ESD) IEC61000-4-4 (EFT) 40 A IEC61000-4-5 ( Lightning ) 3 A UN Semiconductor Co., Ltd. Revision January 06, 2014 KV www.unsemi.com.tw 1/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information. Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Electrical Characteristics (@ 25℃ Unless Otherwise Specified ) Part Number Device Marking VRWM (V) (Max.) VB (V) (Min.) IT (mA) VC @1A (Max.) (Max.) B05B 5.0 6.0 1 9.8 23.0 SR05-4A (@A) IR (μA) (Max.) C (pF) (Typ.) 3 1 1.0 VC Characteristic Curves Fig1. 8/20μs Pulse Waveform Fig2. ESD Pulse Waveform (according to IEC 61000-4-2) 120 IPP - Peak Pulse Current - % of IPP 100 100% TEST WAVEFORM PARAMETERS tr=8μs td=20μs Peak Value IPP 80 Percent of Peak Pulse Current % tr 60 40 td=t IPP/2 20 0 0 5 10 15 20 25 10% tr = 0.7~1ns Time (ns) 30ns 30 60ns t - Time (μs) Fig3. 90% Power Derating Curve % of Rated Power 110 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 Ambient Temperature – TA (ºC) UN Semiconductor Co., Ltd. Revision January 06, 2014 www.unsemi.com.tw 2/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information. Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Characteristic Curves Fig4. ESD Clamping (+8KV Contac per IEC61000-4-2) Fig5. ESD Clamping (-8KV Contac per IEC61000-4-2) SOT-26 Package Outline & Dimensions Inches Symbol Min. θ 0.035 - 0.057 0.90 - 1.45 A1 0.000 - 0.006 0.00 - 0.15 A2 0.035 0.045 0.051 0.90 1.15 1.30 b 0.010 - 0.020 0.25 - 0.50 - 0.009 0.08 - 0.22 c 0.003 D 0.110 0.114 0.122 2.80 2.90 3.10 E1 0.060 0.063 0.069 1.50 1.60 1.75 E 0.110 BSC 2.80 BSC e 0.037 BSC 0.95 BSC 0.075 BSC 1.90 BSC L 0.012 0.018 0.024 0.30 0.45 0.60 L1 θ UN Semiconductor Co., Ltd. Revision January 06, 2014 Nom. Max. Min. Nom. Max. A e1 Soldering Footprint Millimeters (0.024) 0° - (0.60) 10° 0° - 10° aaa 0.004 0.10 bbb 0.008 0.20 ccc 0.008 0.20 Symbol Inches Millimeters C (0.098) (2.50) G 0.055 1.40 P 0.037 0.95 X 0.024 0.60 Y 0.043 1.10 Z 0.141 3.60 www.unsemi.com.tw 3/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information. Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Applications Information Device Connection Options for Protection of Four High-Speed Data Lines Figure 1. Data Line and Power Supply Protection Using VCC as reference The SR05-4A is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 3, 4 and 6. The negative reference (REF1) is connected at pin 2. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (REF2) is connected at pin 5. The options for connecting the positive reference are as follows: Figure 2. Data Line Protection with Bias and Power Supply Isolation Resistor 1. To protect data lines and the power line, connect pin 5 directly to the positive supply rail (VCC). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over-voltage on the supply rail (See Figure1). 2. The SR05-4A can be isolated from the power supply by adding a series resistor between pin 5 and VCC. A value of 100kΩ is recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance (See Figure2). 3. In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop) (See Figure3). Figure 3. Data Line Protection Using Internal TVS Diode as Reference UN Semiconductor Co., Ltd. Revision January 06, 2014 www.unsemi.com.tw 4/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information. Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Applications Information (Continue) Video Interface Protection Figure 4．Video Interface Protection Video interfaces are susceptible to transient voltages resulting from electrostatic discharge (ESD) and “hot plugging” cables. If left unprotected, the video interface IC may be damaged or even destroyed. Protecting a high-speed video port presents some unique challenges. SR05-4A First, any added protection device must have extremely low capacitance and low leakage current so that the integrity of the video signal is not compromised. Second, the protection component must be able to absorb high voltage transients without damage or degradation. As a minimum, the device should be rated to handle ESD voltages per IEC61000-4-2, level 4 (±15kV air, ±8kV contact). The clamping voltage of the device (when conducting high current ESD pulses) must be sufficiently SR05-4A low enough to protect the sensitive CMOS IC. If the Figure 5 - Dual USB Port Protection clamping voltage is too high, the “protected” device may latch-up or be destroyed. Finally, the device must take up a relatively small amount of board space, particularly in portable applications such as notebooks and handhelds. The SR05-4A is designed to meet or exceed all of the above criteria. A typical video interface protection circuit is shown in Figure 4. All exposed lines are protected SR05-4A including R, G, B, H-Sync, V-Sync, and the ID lines for plug and play monitors. Universal Serial Bus ESD Protection The SR05-4A may also be used to protect the USB ports on monitors, computers, peripherals or portable systems. Each device will protect up to two USB ports (Figure5). Figure 6 - SIM Port When the voltage on the data lines exceed the bus voltage (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away from the protected controller chip. The TVS diode directs the surge to ground. The TVS diode also acts to suppress ESD strikes directly on the voltage bus. SR05-4A Thus, both power and data pins are protected with a single device. UN Semiconductor Co., Ltd. Revision January 06, 2014 www.unsemi.com.tw 5/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information. Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Applications Information (Continue) DVI Protection The small geometry of a typical digital-visual interface (DVI) graphic chip will make it more susceptible to electrostatic discharges (ESD) and cable discharge events (CDE). Transient protection of a DVI port can be challenging. Digital-visual interfaces can often transmit and receive at a rate equal to or above 1Gbps. The high-speed data transmission requires the protection device to have low capacitance to maintain signal integrity and low clamping voltage to reduce stress on the protected IC. The SR05-4A has a low typical insertion loss of <0.4dB at 1GHz (I/O to ground) to ensure signal integrity and can protect the DVI interface to the 8kV contact and 15kV air ESD per IEC 61000-4-2 and CDE. Figure 7 shows how to design the SR05-4A into the DVI circuit on a flat panel display and a PC graphic card. The SR05-4A is configured to provide common mode and differential mode protection. The internal TVS of the SR05-4A acts as a 5 volt reference. The power pin of the DVI circuit does not come out through the connector and is not subjected to external ESD pulse; therefore, pin 5 should be left unconnected. Connecting pin 5 to Vcc of the DVI circuit may result in damage to the chip from ESD current. Figure 7 . Digital Video Interface (DVI) Protection 10/100 ETHERNET PROTECTION Ethernet ICs are vulnerable to damage from electro-static discharge (ESD). The internal protection in the PHY chip, if any, often is not enough due to the high energy of the discharges specified by IEC 61000-4-2. If the discharge is catastrophic, it will destroy theprotected IC. If it is less severe, it will cause latent failures that are very difficult to find. being the most sensitive to damage. The fatal discharge occurs differentially across the transmit or receive line pair and is capacitively coupled through the transformer to the Ethernet chip. Figure 8 shows how to design the SR05-4A on the line side of a 10/100 ethernet port to provide differential mode protection. The common mode isolation of the transformer will provide common mode protection to the rating of the transformer isolation which is usually >1.5kV. If more common mode protection is needed, figure 9 shows how to design the SR05-4A on the IC side of the 10/100. 10/100 Ethernet operates at 125MHz clock over a twisted pair interface. In a typical system, the twisted-pair interface for each port consists of two differential signal pairs: one for the transmitter and one for the receiver, with the transmitter input UN Semiconductor Co., Ltd. Revision January 06, 2014 www.unsemi.com.tw 6/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information. Transient Voltage Suppressors Array for ESD Protection Low Capacitance SR05-4A Applications Information (Continue) Figure 8 - 10/100 Ethernet Differential Protection Figure 9 - 10/100 Ethernet Differential and Common Mode Protection UN Semiconductor Co., Ltd. Revision January 06, 2014 www.unsemi.com.tw 7/7 @ UN Semiconductor Co., Ltd. 2014 Specifications are subject to change without notice. Please refer to www.unsemi.com.tw for current information.