SC1486 NOT RECOMMENDED FOR NEW DESIGN Dual Synchronous Buck Pseudo Fixed Frequency DDR Power Supply Controller POWER MANAGEMENT Description Features Constant on-time for fast dynamic response VIN range = 1.8V – 25V DC current sense using low-side RDS(ON) sensing The SC1486 is a dual output constant on synchronousbuck PWM controller optimized for cost effective mobile DDR applications. Features include high efficiency, a fast dynamic response with no minimum on time, a REFIN input and a buffered REFOUT pin capable of sourcing 3mA. The excellent transient response means that SC1486 based solutions will require less output capacitance than competing fixed frequency converters. N O FO T R R EC N O EW M M D EN ES D IG ED N The frequency is constant until a step in load or line voltage occurs at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. or sense resistor Integrated reference buffer for VTT Low power S3 state Resistor programmable frequency Cycle-by-cycle current limit Digital soft-start PSAVE option for VDDQ Over-voltage/under-voltage fault protection <20uA shutdown current Low quiescent power dissipation Two separate PGOOD indicators Separate enable of each switcher Integrated gate drivers with soft switching Efficiency >90% 1% Internal reference 28 Lead TSSOP Industrial temperature range The output voltage of the first controller can be adjusted from 0.5V to VCCA. In DDR applications, this voltage is set to 2.5 volts. A resistor divider from the 2.5 volt supply is used to drive the REFIN pin of the second controller. A unity gain buffer drives the REFOUT pin to the same potential as REFIN. The second controller regulates its output to REFOUT. Two frequency setting resistors set the on-time for each buck controller. The frequency can thus be tailored to minimize crosstalk. The integrated gate drivers feature adaptive shoot-through protection and soft switching. Additional features include cycle-bycycle current limit, digital soft-start, overvoltage and under-voltage protection, and a PGOOD output for each controller. Applications Typical Application Circuit Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies R1 23 VBAT TON1 PGOOD1 27 PGOOD2 R2 9 VDDQ/2 8 TON2 SC1486 PGOOD2 VBAT 13 PGOOD1 REFIN Q4 10 REFOUT 22 EN1 REFOUT DH2 EN/PSV1 LX2 20 19 L2 R8 ILIM2 Q1 VDDQ, 2.5V 6 5 L1 + C7 DL2 LX1 PGND2 16 Q3 + C8 15 R3 4 R4 DH1 VTT, 1.25V 18 Q2 2 ILIM1 FBK2 DL1 FBK1 12 PGND1 26 R11 1 PGND1 PGND1 R10 R5 Revision 5, January 2003 1 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Symbol Maximum Units TON1 to AGND1, TON2 to AGND2 -0.3 to +25.0 V DH1, BST1 to AGND1 and DH2, BST2 to AGND2 -0.3 to +30.0 V LX1 to AGND1 and LX2 to AGND2 -2.0 to +25.0 V AGND1 to PGND1, and AGND2 to PGND2 -0.3 to +0.3 V BST1 to LX1 and BST2 to LX2 -0.3 to +6.0 V VCCA1, VDDP1 to AGND1 and VCCA2, VDDP2 to AGND2 -0.3 to +6.0 V N O FO T R R EC N O EW M M D EN ES D IG ED N Parameter FB1, PGOOD1, EN/PSV1, ILIM1, VOUT1, DL1 to PGND1 -0.3 to +6.0 V FB2, PGOOD2, REFIN, ILIM2, REFOUT, DL2 to PGND2 -0.3 to +6.0 V Thermal Resistance Junction to Ambient(5) θJA 37 °C/W Operating Junction Temperature Range TJ -40 to +125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Electrical Characteristics Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Input Supplies V C C A 1, V C C A 2 V D D P 1, V D D P 2 VDDP2 Undervoltage Threshold VDDP2 falling VDDP2 Undervoltage Hysteresis VDDP1 Operating Current FB > regulation point, ILOAD = 0A VDDP2 Operating Current Typ -40°C to 125°C Max Units Min Max 5.0 4.5 5.5 V 5.0 4.5 5.5 V 3.5 V 250 mV 1 5 5 10 1100 µA VCCA1, VCCA2 Operating Current FB > regulation point, ILOAD = 0A 700 VCCA2 Standby Current VDDP2 < VDDP2 UV threshold, no load on REFOUT 125 µA RTON = 1M 15 µA TON1, TON2 Operating Current REFIN Bias Current Shutdown Current 2002 Semtech Corp. REFIN = 1.25 µA 1 µA EN/PSV1 = 0V -5 -10 µA V C C A 1, V C C A 2 5 10 µA TON1, TON2, VDDP1 0 1 µA 2 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Units Min Max 0.495 0.505 V 0.5 VC C A V Controller Error Comparator Threshold (FBK1 Turn ON Threshold) VCCA = 4.5V to 5.5V VBAT = 2V to 25V 0.500 VDDQ Output Voltage Range REFOUT Source Capability no load, REFIN = 1.25 1.24 1.26 N O FO T R R EC N O EW M M D EN ES D IG ED N REFOUT DC Accuracy 3 mA 1.238 1.262 V Error Comparator Threshold (FBK2 Turn ON Threshold) VCCA = 4.5V to 5.5V VBAT = 2V to 25V REFOUT REFOUT -10mV REFOUT +10mV V On-Time, VBAT = 2.5V RTON = 1M (300kHz), VOUT = 1.25V 1660 1411 1909 ns RTON = 500K (600kHz), VOUT = 1.25V 913 776 1050 ns 550 ns Minimum Off Time 400 VOUT Input Resistance (VDDQ Controller) Line Regulation Error Load Regulation Error 500 kΩ VCCA, VDDP = 4.5V to 5.5V VBAT = 4.5V to 25V 0.04 %/V ILIM - PGND = 0V to OC Limit EN/PSV1 = Open 0.3 % FBK1 Input Bias Current FBK2 Input Bias Current -1.0 +1.0 2.5 µA µA Over-Current Sensing ILIM Current 10 Current Comparator Offset PGND - ILIM 9 11 µA -10 +10 mV PSAVE Zero-Crossing Threshold PGND - LX EN/PSV1 = 5V 5 mV RILIM = 5kΩ 50 -35 65 mV RILIM = 10kΩ 100 80 120 mV RILIM = 20kΩ 200 170 230 mV -140 -200 -100 mV Fault Protection Current Limit (Positive) (PGND-LX) (2) Current Limit (Negative) (PGND-LX) 2002 Semtech Corp. 3 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Max Units Fault Protection (Cont.) VDDQ - Output Under-Voltage Fault VTT - Output Under-Voltage Fault Over-Voltage Fault Delay PGOOD Low Output Voltage PGOOD Leakage Current PGOOD UV Threshold PGOOD Fault Delay VCCA1,VCCA2 Under Voltage Over Temperature Lockout Inputs/Outputs -30 -40 -25 % With respect to REFOUT -20 -28 -15 % VDDQ with respect to internal reference, VTT with respect to REFOUT +10 +8 +12 % FB forced above OV threshold 2 N O FO T R R EC N O EW M M D EN ES D IG ED N VDDQ/VTT Output Over-Voltage Fault With respect to internal reference µs Sink 1mA 0.4 V FB in regulation, PGOOD = 5V 1 µA -8 % With respect to internal reference for VDDQ and REFOUT for VTT -10 FB forced outside PGOOD window. 2 Falling (100mV hysteresis) 4.0 10°C Hysteresis 165 Logic Input Low Voltage EN/PSV1 low Logic Input High Voltage EN High, PSV low (Pin Floating) Logic Input High Voltage EN/PSV1 high 2.0 -15 µs 3.7 4.3 V °C 1.2 1.2 V 2.4 V 2.4 REFIN EN Threshold 0.80 REFIN EN Hysteresis 40 mV Pullup resistance 1.5 MΩ Pulldown resistance 1.0 EN/PSV1 high to full current limit. 1.6 ms SMPS turn-on 2 ms EN/PSV1 Input Resistance 0.55 V 1.00 V Soft Start Soft-Start Ramp Time Under-Voltage Blank Time 2002 Semtech Corp. 4 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Electrical Characteristics (Cont.) Test Conditions: VBAT = 15V, EN/PSV1 = 5V, REFIN=1.25V, VCCA1 = VDDP1 = VCCA2 =VDDP2= 5.0V, VVDDQ = 2.5, VVTT = 1.25, RTON1 = 1M, RTON2 = 1M Parameter Conditions 25°C Min Typ -40°C to 125°C Max Min Units Max Gate Drivers D H or DL rising 30 DL Pull-Down Resistance DL low 0.8 1.6 Ω DL Pull-Up Resistance DL high 2 4 Ω DH Pull-Down Resistance D H low, BST - LX = 5V 2 4 Ω DH Pull-Up Resistance D H high, BST - LX = 5V 2 4 Ω N O FO T R R EC N O EW M M D EN ES D IG ED N Shoot-Through Delay (4) ns Notes: (1) The output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram below. (5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7. Shoot-Through Delay Timing Diagram LX DH DL DL tplhDL 2002 Semtech Corp. tplhDH 5 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Pin Configuration Ordering Information Top View DEVICE PACKAGE(1) SC1486ITSTR TSSOP-28 SC1486ITSTRT(2) TSSOP-28 N O FO T R R EC N O EW M M D EN ES D IG ED N Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free option. (TSSOP-28) Pin Descriptions Pin # Pin Name Pin Function 1 PGND1 2 D L1 3 VD D P1 4 ILIM1 5 LX 1 6 DH1 7 BST1 Boost capacitor connection for the high side gate drive. 8 REFIN Reference input. A resistor divider from the 2.5 volt supply sets this voltage. A 0.1 µF input filter capacitor is reccomended. 9 TON2 Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply and VIN. 10 REFOUT Buffered REFIN output. The second controller regulates to this voltage. 11 VC C A2 Supply voltage input for the analog supply. Connect through a RC filter. 12 FB K 2 13 PGOOD2 14 AGND2 2002 Semtech Corp. Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Feedback input for the SMPS. Connect from resistive divider at output to select output voltage from 0.5V to VCCA. Power Good output. Goes high after a fixed clock cycle delay following power up. Analog ground. 6 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC1486 POWER MANAGEMENT Pin Descriptions (Cont) 15 PGND2 16 D L2 17 VD D P2 18 ILIM2 Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. 19 LX 2 Switching node inductor connection. 20 DH2 Gate drive output for the high side MOSFET switch. 21 BST2 Boost capacitor connection for the high side gate drive. 22 EN/PSV1 23 TON1 24 VOUT1 25 VC C A1 26 FB K 1 27 PGOOD1 28 AGND1 2002 Semtech Corp. Power ground. Gate drive output for the low side MOSFET switch. N O FO T R R EC N O EW M M D EN ES D IG ED N +5V supply voltage input for the gate drivers. Enable/Power Save input pin. Tie to ground to disable SMPS. Tie to +5V to enable SMPS and activate PSAVE mode. Float to Enable SMPS and activate continous conduction mode. Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply and VIN. Output voltage sense input for the SMPS output. Connect to the output of the SMPS. Supply voltage input for the analog supply. Connect through a RC filter. Feedback input for the SMPS. Connect from resistive divider at output to select output voltage from 0.5V to VCCA. Power Good output. Goes high after a fixed clock cycle delay following power up. Analog ground. 7 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Block Diagram AGND1 REF - 30% REF - 10% REF + 10% PGND1 1 28 DL1 2 PGOOD1 FAULT MONITOR UV LO 27 OV VDDP1 3 ILIM1 + - PWM +5V FBK1 X3 26 FB1 N O FO T R R EC N O EW M M D EN ES D IG ED N ZEROI ISENSE 4 OC REF FB1 1.5V TOFF 25 CONTROL LOGIC LX1 5 VOUT PWM 24 OFF TON ON DH1 VDDQ 6 23 EN/PSV1 7 OT VBAT 22 POR/SS VBAT VDDP VCCA VCCA1 VCCA2 VDDQ VDDP2 POR/SS 8 REFIN VREF VDDP VDDQ OT 21 BST2 HI 9 TON2 ON TON OFF 10 CONTROL LOGIC 20 DH2 19 LX2 VTT PWM REFOUT +5V +5V VDDQ TON1 HI BST1 VDDQ = 2.5V VCCA1 11 VCCA2 TOFF REF BUFFER OC ZEROI 12 FBK2 + - 18 ILIM2 ISENSE + - +5V PWM VTT 17 VDDP2 13 PGOOD2 14 AGND2 FAULT MONITOR OV UV REF + 10% REF - 10% REF - 30% LO 16 DL2 15 PGND2 FIGURE 1 - SC1486 Block Diagram 2002 Semtech Corp. 8 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information SC1486 required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator. +5V Bias Supplies The SC1486 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951A. To minimize channel to channel crosstalk, each controller has 4 supply pins, VDDP, PGND, VCCA and AGND. V TON = 3.3x10−12 • (RTON+ 37x103 ) • OUT +50ns VIN RTON is a resistor connected from the input supply to the TON pin. To avoid ground loops, separate AGND planes are recommended. Each contoller requires its own AGND plane which should be tied by a single trace to the negative terminal of that controller’s output capacitor. All external components referenced to AGND in the schematic should then be connected to the appropriate AGND plane. The supply decoupling capacitor for controller 1 should be tied between VCCA1 and AGND1. Likewise, the supply decoupling capacitor for controller 2 should be tied between VCCA2 and AGND2. A single 10 ohms resistor should be used to decouple the VCCA supplies from the main VDDP supplies. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to this plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, the two AGND planes must be connected to the PGND plane at the negative terminal of the respective output capacitors. The VDDP1 and VDDP2 input provides power to the upper and lower gate drivers. A decoupling capacitor for each supply is recommended. No series resistor between VDDP and the 5 volt bias is required. N O FO T R R EC N O EW M M D EN ES D IG ED N Enable & Psave The EN/PSV pin enables the VDDQ (2.5 volt) supply. REFIN and VDDP2 enable the VTT (1.25 volt) supply. The VTT and VDDQ supplies may be enabled independently. When EN/PSV is tied to VCCA the VDDQ controller is enabled and power save will also be enabled. When the EN/PSV pin is tristated, an internal pulled-up will activate the VDDQ controller and power save will be disabled. If PSAVE is enabled, the SC1486 PSAVE comparator will look for the inductor current to cross zero on eight consecutive cycles. Once observed, the controller will enter power save and turn off the low side MOSFET when the current crosses zero. To improve the efficiency and add hysteresis, the on time is increased by 50% in power save. The efficiency improvement at light loads more than offsets the disadvantage of slighlty higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. Since the controller counts crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when psave is enabled.Since the VTT supply must sink current, this controller does not have a power save option. If REFIN is low, the VTT controller shuts down to a low bias current. If Refin is greater than 1 volt, and VDDP2 is low, the reference buffer is active, but the VTT buck converter is disabled (S3 state). If REFIN is greater than 1 volt and VDDP is greater than 4 volts, the VTT supply is active. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant-ontime, pseudo fixed frequency PWM controller, (Figure 1). The output ripple voltage developed across the output filter capacitor’s ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The highside switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time which is typically 400ns. Output Voltage Selection The output voltage selection is set by the feedback resistors R2 & R3 of Figure 3. The internal reference is 1.5V. The internal feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can beselected to a minimum of 0.5V. The equation for setting he output voltage based on Figure 3 is: On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The TON time is the time 2002 Semtech Corp. 9 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) +5V R2 Vout= 1+ •0.5 R3 +VIN + D1 C1 Q1 Current Limit Circuit Current limiting of the SC1486 can be accomplished in two ways. The on-state resistance of the low-side MOSFETs can be used as the current sensing element or sense resistors in the low-side sources can be used if greater accuracy is desired. RDSON sensing is more efficient and less expensive. In both cases, the RILIM resistors between the ILIM pin and LX set the over current threshold. This resistor RILIM is connected to a 10uA current source within the SC1486 which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIMresistor, current limit will activate. The high side will not be allowed to turn on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. C2 BST DH LX ILIM VDDP DL PGND L1 Vout R1 D2 + C3 N O FO T R R EC N O EW M M D EN ES D IG ED N Q2 FIGURE 3 The schematic of RDSON sensing circuit is shown in Figure 3 with RILIM = R1 and RDSON of Q2. Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM.When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an over-current exists and the high side MOSFET will not be allowed to turn on. The over-current equation when using an external sense resistor is: The current sensing circuit actually regulates the inductor valley current (see Figure 2). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below: IL OC (Valley ) = 10 µA • Schematic of resistor sensing circuit is shown in Figure 4 with RILIM = R1 and RSENSE = R4. IPEAK INDUCTOR CURRENT R ILIM R SENSE +5V ILOAD +VIN + D1 ILIMIT C2 C1 Q1 BST DH LX ILIM VDDP DL PGND L1 Vout D2 + C3 Q2 TIME R1 Valley Current-Limit Threshold Point FIGURE 2 2002 Semtech Corp. R4 FIGURE 4 10 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) SC1486 An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on, until DL is fully off, and conversely, monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET. Power Good Output Each controller has its own PGOOD. Power good is an open-drain output and requires a pull-up resistor. When the output voltage is 10% above or below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGOOD is also held low during start-up and will not be allowed to transition high until soft start is over and the output reaches 90% of its set voltage. There is a 2us delay built into the PGOOD circuit to prevent false transitions. Design Procedure Prior to any design of a switch mode power supply (SMPS) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple current must be specified. N O FO T R R EC N O EW M M D EN ES D IG ED N Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched and the SMPS is off until the enable input, REFIN or VCCA is toggled. There is a 2us delay built into the OV protection circuit to prevent false transitions. A OV fault in either controller will not cause the other one to shutdown. Note: to reset VDDQ from a fault, VCCA1 or EN/PSV must be togled. To reset VTT from a fault, VCCA2 or REFIN must be togled. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Maximum Load Current There are two values of load current to consider. Continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tristated condition, and the SMPS is off until the enable input is toggled. There is a 2us delay built into the UV protection circuit to prevent false transitions. An UV fault in either controller will not effect the other controller. Switching Frequency Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA1 and VCCA2 exceed 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.2V. At this time the circuit will come out of UVLO and begin switching, and the softstart circuit being enabled, will progressively limit the output current over a predetermined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when the VCCA falls to 4.1V the output drivers are shutdown and tristated. Inductor Ripple Current Low inductor values create higher ripple current, resulting in smaller size, but are less efficient because of the high AC currents flowing through the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly. The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. 2002 Semtech Corp. 11 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) Stability Considerations Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing not enough voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. However, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a 10pF capacitor across the upper feedback resistor divider network. This is shown below in Figure 5, by capacitor C4 in the schematic. This capacitance should be left out until confirmation that double-pulsing exists. Adding this capacitance will add a zero in the transfer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed. N O FO T R R EC N O EW M M D EN ES D IG ED N +5V SC1486 ESR Requirements The constant on-time control used in the SC1486 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors the absolute minimum ESR must be considered. Existing literature describing the ESR requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. A time domain model of the converter was developed to generate equations for the minimum ESR empirically. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Refering to Figure 5, the equation for the minimum ESR as a function of output capacitance and switching frequency and duty cycle is; +VIN D1 + Fs - 200000 1+3 • R2 + R3 Fs • ESR > 2 • π • Cout • Fs • ( 1 − D ) 2 R3 C1 Q1 C2 BST DH LX ILIM VDDP DL PGND 14 13 12 11 10 9 8 L1 0.5V - 5.5V R1 R2 D2 + Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 500nS (maximum) minimum off-time one-shot. For best dropout performance, use the slowest on-time setting of 200KHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by: C4 10pF C3 Q2 R3 FBK FIGURE 5 Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero to full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is sign that the ESR should be increased. 2002 Semtech Corp. DUTY = TON(MIN) TON(MIN) + TOFF (MAX ) Be sure to include inductor resistance and MOSFET on-state voltage drops when performing worst-case dropout duty-factor calculations. Layout Guidelines (TBD) 12 www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC1486 POWER MANAGEMENT Application Information (Cont.) SC1486 System DC Accuracy (VTT Controller) Two IC parameters effect system DC accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. The 1486 regulates to the REFOUT voltage not the REFIN voltage. Since DDR specifications are written with respect to REFOUT, the offset of the reference buffer does not create a regulation error. 0.5 volts +/-1% at room temperature. The comparator offset trim compensates for any DC error in the reference. Thus, the percentage error is the sum of the reference variation over supply and temperature and the offset in the error comparator or 1.5%. The on pulse in the SC1486 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5V. If the ripple is 50mv with VIN = 6 volts, then the measured DC output will be 2.525 volts. If the ripple increases to 80mv with VIN = 25 volts, then the measured DC output will be 2.540. The best way to minimize this effect is to minimize the output ripple. N O FO T R R EC N O EW M M D EN ES D IG ED N The error comparator offset is trimmed so that it trips when VOUT is 1.25 volts at room temperature. This offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. The on pulse in the SC1486 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, ½ of the output ripple appears as a DC regulation error. For example, if REFOUT=1.25 volts, then the valley of the output ripple will be 1.25 volts. If the ripple is 20mv with VIN=6, then the DC output voltage will be 1.26 volts. If the ripple is 40mv with VIN=25 volts, then the DC output voltage will be 1.27 volts. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. To compensate for valley regulation is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Passive droops also improves stability so it should be used when possible. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage.It will not change the frequency. 1486 System DC Accuracy (VVDQ Controller) Three IC parameters affect system DC accuracy, the internal band gap reference, the error comparator offset voltage, and the switching frequency variation with line and load. Switching frequency variation with load can be minimized by choosing lower RDSON MOSFETs. High RDSON MOSFETS will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. This inherent droop should be considered when deciding if passive droop is required. If the output ripple some passive droop may be desirable to further reduce the output capacitance. The internal 1% 1.5V reference contains two error components, a 0.5% DC error and a 0.5% supply and temperature error. The error comparator offset is trimmed so that it trips when the feedback pin is nominally 2002 Semtech Corp. 13 www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Information (Cont.) DDR Supply Selection Where: TA = ambient temperature (°C) PD = power dissipation in (W) θJA = thermal impedance junction to ambient from absolute maximum ratings (°C/W) The SC1486 can be configured so that VTT and VDQ are generated directly from the battery. Alternatively, the VTT supply can be generated from the VDDQ supply. Since the battery configuration generally yields better efficiency and performance, the eval board is configured to generate both supplies from the battery. The power dissipation may be calculated as follows: ( PD = 2 • VCCA • IVCCA + Vg • Q g • f DDR Reference Buffer N O FO T R R EC N O EW M M D EN ES D IG ED N Inserting the following values as an example: TA = 85°C θJA = 37°C/W VCCA = 5V IVCCA = 1100µA (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz (enter the higher of the two set frequencies here) gives us: As with most opamps, a small resistor is required when driving a capacitive load. To ensure stability use either a 10 ohm resistor in series with a 1uf capacitor or a 100 ohm resistor in series with a 0.1uF capacitor from REFOUT to AGND2. REFIN should also be filtered so that VDDQ ripple does not appear at the REFIN pin. If a resistor divider is used to create REFIN from VDDQ, then a 0.1uF capacitor from REFIN to AGND2 will provide adequate filtering. ( ) TJ = 85 + 2 • 5 • 1100 • 10 −6 + 5 • 60 • 10−9 • 300 • 103 • 37 = 92 °C Thermal Considerations As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout. The junction temperature of the device may be calculated as follows: 2002 Semtech Corp. W Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) The reference buffer is capable of driving 3ma and sinking 25ua. Since the output is class A, if additional sinking i s required an external pulldown resistor can be added. Make sure that the ground side of this pulldown is tied to the VTT AGND plane near the AGND2 pin of the SC1486. TJ = TA + PD • θ JA ) °C 14 www.semtech.com +5 V_ SU S 2 2 1 1 0.1uF/ 25V C1 2 2 0.1uF C3 2 FBK1 MBR0530 0.1uF C4 10uF/ 25V C2 1 2 0.1uF 2 MBR0530 C19 1 1 1 D1 10 R1 VBAT 2 1 1 D2 1 DH1 IRF7811 Q5 1 TP4 LX1 8 7 6 5 2 0.1uF C5 DL1 TP2 1 20k R3 DL1 1 2 R4 2 C6 1 V2_5 1 V2_5 1 3 2 1 NO_POP 80k LX1 TP5 1 TP6 DH1 VDDP1 TP1 ILI M1 470k 2 2 C9 2 1 1 10uF/ 25V C10 Q2 TP9 4 7 5 1 V_TT TP10 1 TP11 2 V_TT V2 5 10k R5 VBAT DL1 1 2 1000k 1 1 0.1uF C8 1 2 DH2 2 150uF C7 MBR0530 D3 FDS7764 2 Q6 2uH L1 8 7 6 5 1 EN_PSV R6 1 0.1uF C11 Si4818DY 3 2 1 VIN_VTT TP 7 0530 M BR D4 8 2 0.1uF/ 25V 1 2 10k DL2 1 10k R9 1 REF I N 1 2 2 1 1 1 2 1 1 470k PGOOD2 2 PGOOD2 TP13 R13 NO_POP R12 +5V_SUS REF OUT REF_OUT TP12 2 220uF C14 + 3. 3uH L2 0.1uF/ 25V C15 1000pF/X7R 2 10k R10 C13 1 3 LX2 100 R11 1 0.1uF/X7R C12 1 R8 REF_I N2 TP8 750k R7 1 +5V_RUN 1 N O FO T R R EC N O EW M M D EN ES D IG ED N LX1 2 SC1486 R2 24 VOUT1 LX1 5 2 DH1 6 PGOOD1 BST1 BST2 21 BST2 REF_I N 8 REFI N 1 1 TON 2 9 2 VIN_VTT TON2 DH2 10 20 DH2 REFOUT TP3 PGND1 2 1 PGOOD1 VCCA2 1 28 AGND1 1 FBK1 26 FBK1 3 4 2 6 2 ILI M 12 18 ILI M2 11 VCCA 25 VCCA1 ILI M1 4 2 1 27 PGOOD1 DL1 D FBK2 TON1 1 23 TON1 DH1 D 22 EN/ PSV1 BST1 7 + 1 2 4 PGOOD2 LX2 2 17 VDDP2 V_T T 12 DL2 16 DL2 13 19 LX2 1 15 REF_RC 15 PGND2 AGND2 2002 Semtech Corp. 14 +5V_RUN NOT RECOMMENDED FOR NEW DESIGN SC1486 POWER MANAGEMENT Application Schematic www.semtech.com SC1486 NOT RECOMMENDED FOR NEW DESIGN POWER MANAGEMENT Application Schematic VBA T 2 VBA T 1 PO S N EG 1 1 N O FO T R R EC N O EW M M D EN ES D IG ED N 2 B _J A C K _ P A I R P G LE D 0 J2 J P4 1 B E R G _2 P I N OUT -- LEDs OFF (Bias measurements) T P 15 1 NE G 2 IN -- LEDs Enabled (Normal Mode) B _ J A C K _P AIR PO S Jumper Settings: J1 +5V_SU S T P 14 1 +5V_SUS 1 1 R 16 1 0k R 15 1 80 1 80 R 14 2 2 P G LE D 1 P G LE D 3 2 V IN _ V T T T P 16 1 2 V IN _ V T T 0 E N2 3 R 17 1 - 2 -- VIN_VTT = VBAT 2 - 3 -- VIN_VTT = 2.5V 3 B E R G _3 P I N 2 P G LE D 2 1 3 V 2 _5 1 + D 1 PO S N EG 1 2 L X1 Jumper Settings: 2 1 B _J A C K _ P A I R D H1 2 G S N O_PO P J3 8 7 2 N O_PO P Q1A 2 2N 7 0 02 Q4 2 D C 17 10 k R 18 VBA T 1 10nF 3 2N 7 0 02 PGO OD 2 1 C 16 2 P G LE D 4 Q3 PGO OD 1 1 1 Zero Ohm Resistor Settings: E N1 1 J P1 EN _PSV D 6 G R EEN D 5 G R EEN E N _P S V T P 17 Vtt PWR GOOD 1 Vddq PWR GOOD 1 - 2 -- ENABLE + POWERSAVE 6 5 N O_PO P Q1B 2 - 3 -- DISABLE D D 1 V_T T 1 N EG C 18 2 N O_PO P 2 B _J A C K _ P A I R + 1 Mode) 2 Vref ON, Vtt OFF (S3 Normal Operation Vref and Vtt OFF 0 OUT IN R 19 AGND T P 20 IN IN 1 2 0 16 R 20 2002 Semtech Corp. 1 PO S Vref and Vtt OFF 1 OUT IN GN D J P3 OUT OUT MODE T P 21 JP3 1 JP2 AG N DF 2 T P 19 1 B E R G _2 P I N B E R G _2 P I N J P2 R E F _I N 1 Jumper Settings: J4 2 S 3 + 5V _ R U N T P 18 1 + 5 V _R U N 1 G D L1 4 Open -- Enable + FIXED FREQUENCY www.semtech.com NOT RECOMMENDED FOR NEW DESIGN SC1486 N O FO T R R EC N O EW M M D EN ES D IG ED N POWER MANAGEMENT Outline Drawing - TSSOP-28 Land Pattern - TSSOP-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2002 Semtech Corp. 17 www.semtech.com