TS80002 High Efficiency Transmitter Controller for Wireless Power Systems TRIUNE PRODUCTS Features Description • • • The TS80002 is a power transmitter communications and control unit for wireless charging applications. The TS80002 can support systems up to 5W and proprietary applications. • • Supports portable wireless charging applications Wireless power systems up to 5W Integrated controller and FLASH for communications and control High precision data converter Low external component count Applications • Low-power wireless chargers for: Smart Watches Wearables Toys Portable Lighting Medical Devices The TS80002 performs the necessary coding of protocol to send commands to the transmitter to adjust the power level accordingly. Specifications • • • • • • • • RISC-based controller core with flash and SRAM memory 10-bit A/D converter Two 16-bit timers, advanced control and general purpose 8-bit timer Auto-wakeup and watchdog timers 4 configurable general purpose IOs I2C interface 20 pin 3x3 QFN Typical Application Circuit TS80002 + TS51231 TS51221 Transmitter Receiver DC Supply Load Application Processor TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 1 of 16 Semtech Proprietary & Confidential TS80002 Final Datasheet March 26, 2015 V_AC I_DC GPIO4 NRST DEBUG GPIO1 PMW2_H GPIO2 PMW1_H Rev 1.0 www.semtech.com PMW1_L PMW2_L SCL LDO SDA GPIO3 ALERT VSS VDD PIN 1 VREF V_DC Pinout (Top View) 2 of 16 Semtech Proprietary & Confidential Pin Description Pin # Pin Name Pin Function Description 1 NRST Reset Reset input 2 GPIO1 GPIO GPIO 1 3 GPIO2 GPIO GPIO 2 4 VSS Power GND Power GND 5 LDO Filter Internal LDO filter capacitor 6 VDD Input power Input power supply 7 ALERT I2C Alert I2C Alert signal 8 SDA I2C Serial Data I2C Serial Data 9 SCL I2C Serial Clock I2C Serial Clock 10 PWM1_L PWM output PWM1 low-side control 11 PWM2_L PWM output PWM2 low-side control 12 GPIO3 GPIO GPIO 3 13 PWM1_H PWM PWM1 high-side control 14 PWM2_H PWM PWM2 high-side control 15 DEBUG Debug Debug interface 16 V_AC Analog GPIO AC voltage measurement 17 I_DC Analog GPIO DC current measurement 18 GPIO4 GPIO GPIO 4 19 VREF Analog GPIO Voltage reference input 20 V_DC Analog GPIO DC voltage measurement TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 3 of 16 Semtech Proprietary & Confidential Functional Block Diagram Power On Reset PWM1_H System Supervisor VDD Voltage Reference PWM1_L PWM Control PWM2_H Oscillator AGPIOx I_DC Memory Timers GPIO Controller SDA V_AC V_DC I_DC IO Buffers V_AC V_DC AGPIO Interface ADC1 GPIO Interface CONTROLLER PWM2_L ALERT GPIO1 GPIO4 I2C / UART SCL GND TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 4 of 16 Semtech Proprietary & Confidential Absolute Maximum Rating Over operating free–air temperature range unless otherwise noted(1, 2, 3) Parameter Min Max Unit -0.3 6.5 V GPIO1, GPIO2, VSS, VDD, ALERT, SDA, SCL, PWM1_L, PWM2_L, GPIO3, PWM1_H, PWM2_H, DEBUG, V_AC, I_DC, GPIO4, VREF, V_DC VSS - 0.3 6.5 V NRST, LDO VSS - 0.3 VDD + 0.3 V Operating Junction Temperature Range, TJ -40 125 °C Storage Temperature Range, TSTG -65 150 °C Electrostatic Discharge – Human Body Model ±2k V Lead Temperature (soldering, 10 seconds) 260 °C VDD, VSS Notes: (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) ESD testing is performed according to the respective JESD22 JEDEC standard. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD Input Operating Voltage 2.95 5.5 V FMCU Operating Frequency 0 16 MHz VDD Decoupling capacitor value 1 uF LDO Decoupling capacitor value 1 uF TA Operating Free Air Temperature -40 85 °C TJ Operating Junction Temperature -40 105 °C Communication Interfaces The Applications Processor can interrogate the TS80002 using the I2C interface. The TS80002 acknowledges its I2C Slave Address only if it is powered. No ACK from the TS80002 after its slave address means that power is not applied to the TS80002. TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 5 of 16 Semtech Proprietary & Confidential I2C I2C Signal Pins I2C Protocol ALERT pin (GPIO pin) - optional: • Driven high when an event is active in the internal STATUS register • Driven low when all the internal events are cleared The TS80002 Wireless Power Receiver acts as an I2C slave peripheral to allow communication with an application microcontroller. The slave address (7 bit) is 0x51. The Embedded Controller is an I2C master and initiates every data transfer. Note: The ALERT pin is provided to help with I2C communication, i.e. to signal events to the EC so the EC can interrogate the TS80002 via I2C. The use of the ALERT pin is not mandatory in the application. SCL pin: • Clock pin for the I2C interface. • True open-drain. Needs external pull-ups. The TS80002 implements a set of registers available from the I2C bus. It also implements a set of API functions that receive parameters and return values using the I2C bus. Four transfer types are possible: • • • • SDA pin: • Data pin for the I2C interface. • True open-drain. Needs external pull-ups. Write Register Operations Write Register Read Register Run API Function Read API Function Return Buffer Description START Start of the I2C transfer. M[S Slave Address (7 bits) M[S 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). Register n address (8 bits) Slave ACK Address of the first register M[S Register n Data (8 bits) Slave ACK Write the first register M[S Register n+1 Data (8 bits) Slave ACK Optionally write the following registers ... M[S Register n+k Data (8 bits) Slave ACK STOP Stop of the I2C transfer Read Register Operations START Start of the I2C transfer. M[S Slave Address (7 bits) M[S Register n address (8 bits) 0 (1 bit) Slave ACK Slave ACK START Slave address + 0 as R/nW bit (0x92 as 8-bit). Address of the first register Repeated Start M[S Slave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit). S[M Register n Data (8 bits) Master ACK Read the first register S[M Register n+1 Data (8 bits) Master ACK Optionally read the following registers Master nACK The master should send a nACK after the last data byte was received. ... S[M Register n+k Data (8 bits) STOP TS80002 Final Datasheet March 26, 2015 Stop of the I2C transfer Rev 1.0 www.semtech.com 6 of 16 Semtech Proprietary & Confidential Run API Function Description START Start of the I2C transfer M[S Slave Address (7 bits) M[S 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit). API number (8 bits) Slave ACK API number M[S API input buffer length m (8 bits) Slave ACK API input buffer length. Equal to 0 if no input buffer data is required by the API M[S Input buffer data[0] (8 bits) Slave ACK First byte of the input buffer (optional) M[S Input buffer data[1] (8 bits) Slave ACK Second byte of the input buffer (optional) Slave ACK Last byte of the input buffer (optional) ... M[S Input buffer data[m-1] (8 bits) STOP Stop of the I2C transfer and execute the API function Read API Function Return Buffer Description START Start of the I2C transfer. M[S Slave Address (7 bits) M[S API number (8 bits) 0 (1 bit) Slave ACK Slave ACK START Slave address + 0 as R/nW bit (0x92 as 8-bit). API number. Repeated Start M[S Slave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit). S[M API number (8 bits) Master ACK API number for the following return buffer S[M API return buffer length n (8 bits) Master ACK API return buffer length S[M Output buffer data[0] (8 bits) Master ACK Read the first byte in the output buffer S[M Output buffer data[1] (8 bits) Master ACK Optionally read the following bytes Master nACK The master should send a nACK after the last data byte was received. ... S[M Output buffer data[n-1] (8 bits) STOP TS80002 Final Datasheet March 26, 2015 Stop of the I2C transfer Rev 1.0 www.semtech.com 7 of 16 Semtech Proprietary & Confidential Internal Registers Addresss General Registers Name Type Description 0x00 BOOTFW_REV_L R/W Bootloader Firmware Revision Low Register 0x01 BOOTFW_REV_H R/W Bootloader Firmware Revision High Register 0x02 FW_REV_L R/W Firmware Revision Low Register 0x03 FW_REV_H R/W Firmware Revision High Register 0x04 MODE_L R/W Operating Mode Low Register 0x05 MODE_H R/W Operating Mode High Register 0x06 RESET_L R/W Reset Low Register 0x07 RESET_H R/W Reset High Register 0x08 STATUS R Main Status Register 0x09 STATUS0 R Status0 Register 0x0A STATUS1 R Status1 Register 0x0B STATUS2 R Status2 Register 0x0C STATUS3 R Status3 Register 0x0D-0x7F RESERVED. Will be defined later. Bootloader Firmware Revision Low Register (BOOTFW_REV_L) Address: Reset value: 0x00 Minor version number of the bootloader firmware 7 6 5 4 3 2 1 0 r r r r REV_L[7:0] r r r r Bits 7:0 REV_L[7:0]: Bootloader Firmware Revision Low These bits contain the minor version number of the bootloader firmware. Bootloader Firmware Revision High Register (BOOTFW_REV_H) Address: Reset value: 0x01 Major version number of the bootloader firmware 7 6 5 4 3 2 1 0 r r r r REV_H[7:0] r r r r Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High These bits contain the major version number of the bootloader firmware. TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 8 of 16 Semtech Proprietary & Confidential Firmware Revision Low Register (FW_REV_L) Address: Reset value: 0x02 Minor version number of the user firmware 7 6 5 4 3 2 1 0 r r r r REV_L[7:0] r r r r Bits 7:0 REV_L[7:0]: Firmware Revision Low These bits contain the minor version number of the user firmware. Firmware Revision High Register (BOOTFW_REV_H) Address: Reset value: 0x03 Major version number of the user firmware 7 6 5 4 3 2 1 0 r r r r 1 0 REV_H[7:0] r r r r Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High These bits contain the major version number of the user firmware. Operating Mode Low Register (MODE_L) Address: Reset value: 0x04 Depends on the bootloader mode and the firmware type 7 6 5 4 3 2 BOOTLDR Res r Bits 7:1 Reserved Bit 0 BOOTLDR: Bootloader mode 0: The user firmware is running 1: The controller is in bootloader mode Operating Mode High Register (MODE_H) Address: Reset value: 0x05 Depends on the bootloader mode and the firmware type 7 6 5 4 3 2 1 0 3 2 1 0 w w w Res Bits 7:0 Reserved Reset Low Register (RESET_L) Address: Reset value: 0x06 0x00 7 6 5 4 RESET_KEY_L[7:0] w w w Bits 7:0 TS80002 Final Datasheet March 26, 2015 Rev 1.0 w w RESET_KEY_L[7:0]: Reset Key 0x55: generate a system reset. Both the RESET_L and the RESET_H registers have to be written with the correct key to generate a reset. Any other value: a system reset is not generated. www.semtech.com 9 of 16 Semtech Proprietary & Confidential Reset High Register (RESET_H) Address: Reset value: 0x07 0x00 7 6 5 4 w w w w 3 2 1 0 w w w RESET_KEY_H[7:0] w Bits 7:0 RESET_KEY_H[7:0]: Reset Key 0xAA: generate a system reset. Both the RESET_L and the RESET_H registers have to be written with the correct key to generate a reset. Any other value: a system reset is not generated. Main Status Register (STATUS) Address: Reset value: 0x08 0xC0 7 6 5 CTS CTS_API rw rw Bit 7 TS80002 Final Datasheet March 26, 2015 Rev 1.0 4 Res 3 2 1 0 STATUS3 STATUS2 STATUS1 STATUS0 rw rw rw rw CTS: Clear To Send This bit indicates if a new command can be issued to the controller. 0: The controller is busy processing a previous command. New commands should not be sent to the controller. 1: The controller can accept a new command over the communication interface. Bit 6 CTS_API: Clear to Send for API This bit indicates if a new API call can be issued to the controller. 0: The controller is busy processing a previous API call. New API calls should not be sent to the controller. 1: The controller can accept a new API call over the communication interface. Bits 5:4 Reserved Bit 3 STATUS3: STATUS3 Event Flag 0: No event is signaled in the STATUS3 register 1: An event is signaled in the STATUS3 register Bit 2 STATUS2: STATUS2 Event Flag 0: No event is signaled in the STATUS2 register 1: An event is signaled in the STATUS2 register Bit 1 STATUS1: STATUS1 Event Flag 0: No event is signaled in the STATUS1 register 1: An event is signaled in the STATUS1 register Bit 0 STATUS0: STATUS0 Event Flag 0: No event is signaled in the STATUS0 register 1: An event is signaled in the STATUS0 register www.semtech.com 10 of 16 Semtech Proprietary & Confidential API Functions API Number API Name Description 0x80 BOOTLOADER_UNLOCK_FLASH Allow changes to the FLASH memory 0x81 BOOTLOADER_WRITE_BLOCK Write a page into the FLASH memory 0x82 BOOTLOADER_CRC_CHECK Check the CRC of the user firmware 0x83-0xFE RESERVED. Will be defined later. 0xFF Value returned in the API field when a Read API Function Return Buffer command is issued and the API function called previously has generated an error. API_ERROR Bootloader Unlock Flash (BOOTLOADER_UNLOCK_FLASH) API number: Input buffer size: Output buffer size: 0x80 TBD 1 Buffer Parameter Input buffer TBD Return data buffer ERROR_CODE Length (bytes) Description 1 Bootloader Write Block (BOOTLOADER_WRITE_BLOCK) API number: Input buffer size: Output buffer size: 0x81 66 1 Buffer Input buffer Return data buffer Parameter Length (bytes) Block Number 2 Block Data 64 ERROR_CODE 1 Description Block index. The first block has an index of 0. Data to be written to the FLASH page. Bootloader CRC Check (BOOTLOADER_CRC_CHECK) API number: Input buffer size: Output buffer size: 0x82 0 1 Buffer Parameter Length (bytes) Return data buffer ERROR_CODE 1 Description API Error Codes Error Code Error Code Name Description 0x00 ERROR_GENERIC Generic error. 0x01 0x02 0x03 0x04 ERROR_OK ERROR_INVALID_CRC ERROR_FLASH_UNLOCK_FAILED ERROR_API_NOT_IMPLEMENTED 0x05 ERROR_API_DATA_OVERFLOW 0x06 0x07-0xFF ERROR_API_INVALID_PARAMETERS RESERVED. Will be defined later. Operation succeeded. This is not indicating an error. CRC error. FLASH unlocking has failed. The API number is not implemented. The API input buffer has been filled with more data than its length. At least one of the API parameters is invalid. TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 11 of 16 Semtech Proprietary & Confidential Application Schematic 1 2 VCC5V C3 1uF 6.3V C4 10nF 10V 6 5 C5 1uF 6.3V U1 4 VSS A GND GND GND SCL SDA 2 3 12 RESET DEBUG B 1 15 PWM1_L PWM1_H PWM2_L PWM2_H VDD LDO V_AC I_DC VREF V_DC GPIO1 GPIO2 GPIO3 GPIO4 ALERT SCL SDA NRST DEBUG TS80002 3 10 13 11 14 C7 100nF 10V VCC5V R3 10K 16 17 19 20 18 7 R4 10K GND 8 1 6 4 3 2 DONE SCL SDA 9 8 7 4 VCC5V U2 VDD VIN VIN GND BOOT 10 SW SW 11 12 PGND PGND PGND PGND PAD 5 9 13 14 17 EN HSON nFLT SCL SDA TS51231 15 16 C18 22nF 10V VBAT VBAT VBAT GND GND GND ENABLE DONE SDA SCL NC BATT DC IN 1 2 3 4 5 6 7 8 9 10 11 CHG_EN DONE SMB_SDA SMB_SCL GND 1 2 GND GND J1 D1 330K C19 NP VCC5V R9 TP1 1K C9 1nF 100V GND GND A AC COIL AC 3.0uH TX Coil GND R7 C8 100nF R8 22K 10V C16 4.7nF 50V C6 4.7nF 50V BATT J2 C2 100nF 10V Coil Feedback RESET TP2 DEBUG TP3 SCL TP4 SDA TP5 B TP6 GND R10 10K GND C11 1nF 10V C GND BATT C10 R11 1K R12 10K 4.7nF 100V C RX -> TX Communication GND L1 11 C17 22uF 6.3V D C1 10uF 10V C12 100nF 10V CHG_EN GND 13 15 17 6 9 10 7 U3 1uH 1.1A VIN PGND PGND PAD GND NC NC EN VSW VSW 12 14 VOUT VOUT VOUT VOUT 1 2 3 16 ISEN FB 4 5 PG 8 VCC5V C13 22uF 6.3V C14 22uF 6.3V RESET TS32101 R13 1.2M R14 380K C15 22pF 25V D Title Wireless Power TX 3V-4.2V Low Power GND GND Size: Letter Date: 8/12/2014 1 681 N. Plano Road Suite 121 Richardson, Texas 75081 2 Number: Revision:1.0 Triune Systems Proprietary and Confidential Information Time: 10:13:27 AM Sheet 1 of 1 3 4 Figure 1: TS80002 Application Schematic TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 12 of 16 Semtech Proprietary & Confidential Package Dimensions TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 13 of 16 Semtech Proprietary & Confidential QFN Package (Top marking) Legend: Line 1 Marking: S033 Internal part code Line 2 Marking: SS Assembly site identifier LL Lot trace code D Assembly year WW Assembly week Y Additional marking o Pin 1 Identifier Line 3 Marking: TS80002 Final Datasheet March 26, 2015 Rev 1.0 www.semtech.com 14 of 16 Semtech Proprietary & Confidential Ordering Information Part Number Description TS80002-QFNR Boot Loader Device RoHS and Reach Compliance Triune Systems is fully committed to environmental quality. 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All rights reserved. © Semtech 2015 Contact Information Semtech Corporation 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com TS80002 Final Datasheet March 26, 2015 Rev 1.0 16 of 16 Semtech Proprietary & Confidential