ACS8527 -EVB

EVALUATION BOARD
ACS8527 -EVB
LIne Card Protection Switch
Advanced Communications
Revision 1.0 November 2002
DESCRIPTION
FEATURES
The ACS8527 -EVB is an evaluation kit for exercising
and evaluating the functions of the ACS8527 SETS
(Synchronous Equipment Timing Source) SDH and SONET
clock control and synchronisation device.
· Input and output frequencies set by switches.
The ACS8527 is designed so that it can be configured for
different input and output frequencies
· Kit comprises: 4 layer populated PCB, three SMB/BNC
The board provides connections for two reference clock
inputs and two reference clock outputs simultaneously,
via SMB connectors. SMB to BNC patch cords are
provided for connectivity to standard equipment. The TTL
type inputs can also be optionally terminated via on board
resistor placements, to cater for 50Ω or 75Ω drivers.
· Surface mounted SETS IC for optimum performance
· Access to all I/O's with optional terminations for
On board switches allow for control over power up default
input and output frequencies, SDH or SONET input
frequency rates, reset and input source selection.
· Single 5 V supply connection with on board 3.3 V
source selection by switch.
Input
· On-board TCXO oscillator (12.8MHz) for accurate
output frequency holdover. (Simple XO also possible).
cables.
different electrical interfaces
· Optional strip connections allow "daughter board"
mounting on to another PCB and easy signal access
regulator
Figure 1: ACS8527-EVB Evaluation Board
Semtech reserves the right to change specifications on catalog devices without notice.
© Copyright, Semtech Corp 2000
Advanced Communications
ACS8527 EVB Evaluation Kit
Introduction
Switch settings
This evaluation board is intended to demonstrate the
capabilities of the ACS8527 SETS IC. Different
operating states and frequencies may be tested
through direct control of the operation of the device
via the hardware switches on the PCB.
SW1 allows setting of the pins of the device that
configure the fixed operating states. The ACS8527
data sheet gives details on the effect of the pin settings.
The following settings show a typical setup to aid in
getting started :
Circuit Description
TEST1 - set switch to off. The pin of the IC is pulled
up by its internal pull-up resistor.
A single 5 V supply is required for the board. The
component placements on the board are shown in
Figure 3. The detailed schematic circuit diagram is
shown in Figure 2. The following sections address
each aspect of the design.
TEST2 - set switch to off. The pin of the IC is pulled
up by its internal pull-up resistor.
PORB - set switch to off. The pin of the IC is pulled
up by it's internal pull-up resistor after a
short time delay determined by capacitor
C13, thus allowing the device to be async
reset. Switching the switch to on resets the
device and configures all internal registers to
their power-on default state. Default input
and output frequencies are determined by
the switch settings
Component Options - Signal Terminations
Input signals to the ACS8527 IC may be optionally
terminated by the placement of resistors on the board.
For the CMOS and TTL compatible inputs there are
resistor spaces available to allow for the case where
the signal is being driven from a 50Ω or 75Ω source.
The resistor placements will be left open on supplied
boards to allow this option later.
SDHB - set switch to off for initial selection of SDH
rate frequencies at power up, pin pulled down
by internal pull-down resistor in IC. Will be
overwritten by any subsequent software
register writes to the control register.
To allow for monitoring of the outputs on the
evaluation board, a termination resistor for LVDS type
output is available locally :
IP_Freq(0:2) - set switch according to table 1. Used
to set the input frequency of SEC1 and SEC2.
The switch set to On and Off. For this switch
On = '0', Off = '1'.
The R12 output termination should be placed if local
LVDS termination is needed. i.e. where there is no
end of line termination.
R8, R9, R10 and R11
positions are left open.
Crystal Module
SW2 settings:
For operation at the correct SDH and SONET
frequencies defined in the ACS8527 IC specification,
the IC must be fed with a 12.8MHz clock signal. We
are currently using and recommending several TXCO/
XO modules from Vectron International, CMAC and
others. Contact Semtech for specification information.
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SRCSW - set switch to on to select 'source switching
mode'. When this is high at power up this
mode is set, whereby from now on this pin
selects SEC1 if high (on) or SEC2 input when
low (off/open).
The board is usually fitted with a CMAC E2747 small
form factor stratum 3 TCXO, which may be slighly
overspecified for some simple line card applications.
With this TCXO the IC will have excellent frequency
holdover (output frequency when all inputs have failed)
stability, across temperature within +/- 0.28 ppm.
When good holdover performance is not an issue
cheaper non temperature compensated crystal
oscillators may be used.
O1_Freq(0:2) - set switch according to table 1. Used
to set the output frequency of O1. For this
switch On = '0'.
O2_Freq(0:2) - set switch according to table 1. Used
to set the output frequency of O2. For this
switch On = '0'.
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Advanced Communications
ACS8527 EVB Evaluation Kit
PCB Layout Recommendations
The evaluation board PCB layout follows good layout
practice for minimizing the magnitude and the effects
of noise. Generous ground planes and good supply
decoupling is used, with separate ground and supply
planes and connections being used for the analog and
digital parts of the IC. Gerber plots (PCB layer plots)
are available for all the PCB layers from the evaluation
board, to assist in the development of a customers
own PCB. The following guidelines should be
considered when laying out a custom circuit board for
the ACS8527 SETS IC :
2) Use separate Power and Ground planes to
separate the analog power/ground connections from
the digital power connections on the other pins.
They should be star connected back to a common
source, meeting the decoupling capacitors before
joining with the other power/gnd supplies.
1) A generous ground plane should be provided around
the SETS IC to minimise noise and maximise the
effectiveness of decoupling components.
4) Power supply decoupling capacitors should be
placed as close as possible to the pins of the
SETS IC to decouple all power and ground
connections to the device.
3) Minimise the size of cuts or openings in the
power and ground planes.
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Table 1. Input and output Frequency selection by switch / pin
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Advanced Communications
ACS8527 EVB Evaluation Kit
VDD3
VDD
P1
VDD5v
VDD2
IC2
3 VIN
1 GND
5v
VOUT
2
Power supply and ground
connections to 'star'
connect back to these
decoupling capacitors at
the regulator and only
connect together at this
point
VDDA
0v
EZ1086-3.3V
term_connect
(+)
(+)
C2
100uF
C3
100nF
C5
100nF
C4
10uF_TANT
VDD
AGND
DGND2
ZD2
BZV90C-5.6v
DGND
R16
R19
R20
DGND3
10K
10K
10K
IP_FREQ0
IP_FREQ1
IP_FREQ2
O2
DGND
C14
VDD
VDDA
100nF
C15
100nF
Decoupling capacitor, C16 should be placed
close to the xtal pins that are being decoupled
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R18
150R
C7
100nF
SW1
GND
AGND
X2
DGND
IC1
VDD
DGND
SRCSW
100nF
16
VDD
VDD
7
1
S2
DGND
R22
VDD2
DGND
C9
100nF
S3
R15
optional only needed for 5v
protection
C11
100nF
DGND
PORB
1K
1
2
VDD2
DGND
R8
130
Optional circuit to ensure
SRCSW is high on power-up.
R10
130
R12
R13
50R
R14
50R
DGND2
DGND
100
R9
82
FrSync
MFrSync
O1P
R11
82
O1N
SEC1
SEC2
DGND
DGND2
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Figure 2: ACS8527 EVB Schematic Diagram.
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All decoupling capacitors,
C6,C7,C8,C9,C10,
C11,C12,C14,C15 should be
placed close to the IC1 pins
that are being decoupled
1
DGND
10k
C10
100nF
8
O1_FREQ2
O1_FREQ1
O1_FREQ0
O2_FREQ2
O2_FREQ1
O2_FREQ0
VDD5v
VDD
R21 BSH205
560K
M1
9
VDD
VDD
VDD5v
C16
470nF
SW2
C12 DGND
17 FrSync
18 MFrSync
19 O1POS
20 O1NEG
21 GND_DIFF
22 VDD_DIFF
23 IC3
24 IC4
25 IC5
26 IC6
27 VDD5V
28 IP_FREQ0
29 SEC1
30 SEC2
31 DGND4
32 VDD1
3
NC
2
NC
Op
1
4
5 NC
DGND3
R2
C8
10R 100nF
1
PORB 48
IC9 47
O1_FREQ1 46
O1_FREQ0 45
NC1 44
IC8 43
IC7 42
TMS 41
DGND5 40
VDD2 39
O2_FREQ1 38
TRST 37
O2_FREQ2 36
O2_FREQ0 35
IP_FREQ2 34
IP_FREQ1 33
ACS8527
C13
1nF
16
15
14
13
12
11
10
9
DGND
6 Vs
Optional :C-MAC
CFPT9050
12.8MHz
1 AGND1
2 IC1
3 AGND2
4 VA1+
5 LOS_ALARM
6 REFCLK
7 DGND1
8 VD1+
9 VD2+
10 DGND2
11 DGND3
12 VD3+
13 SRCSW
14 VA2+
15 AGND3
16 IC2
VDD3
DGND
X1
AGND
VDDA
VDD
1
2
3
4
5
6
7
8
NC
OP 5
GND 4
3 NC
2
NC
NC
1
6
7 NC
8 NC
9 VS
10 GNDb
C16
100nF
49 TCK
50 TDO
51 TDI
52 IC10
53 DGND6
54 VDD3
55 NC2
56 O2
57 VA3+
58 AGND4
59 NC3
60 IC11
61 IC12
62 IC13
63 O1_FREQ2
64
SONSDHB
LED
AGND
R1
C6
10R 100nF
C-MAC
E2747_ 12.8MHz
VDD
1
DGND
S4
VDD
LED
16
TEST1
TEST2
PORB
SDHB
S1
DGND
Loss
Alarm
8
1
2
please ensure that there is no 'T'
junction on the output 'O2'
All tcxo options to be placed as close as
possible to IC1, with short output track.
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Advanced Communications
ACS8527 EVB Evaluation Kit
Test Setup
For a quick device setup test, connect a 19.44MHz clock source at TTL levels to input connector SEC1, using
the supplied SMB to BNC cable. Set switch1 IP_Freq0 = 1, IP_Freq1 = 1 and IP_Freq2 = 0. Set switch2
O1_Freq0 = 1, O1_Freq1 = 1, O1_Freq2 = 1, O2_Freq0 = 1, O2_Freq1 = 1, O2_Freq2 = 0 and SRCSW = 1.
1) O2 output produces 19.44MHz.
2) O1 output (O1P and O1N differentially at LVDS levels) produces 155.52MHz.)
These are derived from the internal analog PLL and have a low jitter of around 55ps RMS broadband, 400ps
peak to peak. The output jitter measured according to the ITU G813 spec STM-1 with a 12KHz to 1.3MHz pass
band filter is around 0.005 UI RMS and 0.06 UI peak-to-peak at 155MHz.
Looking at the 19.44MHz input and output clocks on SEC1 and O2 respectively, one should see that the output
is phase locked to the input.
The 155.52MHz output on the O1P and O1N outputs can also be seen. These outputs drive LVDS levels, they
must be terminated with 100 or 50 ohm loads as described on page 2 under section 'component options - signal
terminations'.
Typical Minimal Test Equipment
- 'Flexacom Plus' Analyser / Generator - ICT Electronics
- HP Infinium 8GS/s oscilloscope 54845A
- Wavetek frequency counter and stable clock reference Model 905 (with option 40 OCXO)
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Advanced Communications
ACS8527 EVB Evaluation Kit
ACS8527 Evaluation board component listing.
Instance
Value
Capacitors
C3,C5,C6,C7,C8,C9,C10,C11,C12,C14,C15,C16
C2
C4
C13
100nF Ceramic SMT
100uF Tantalum SMT
10uF Tantalum SMT
1nF Ceramic SMT
Resistors
R7,R12
R15,R16
R1,R2
R13,R14
R18
100Ω SMT
47Ω SMT respak
10Ω SMT
50Ω SMT
150Ω SMT
Semiconductors
IC1
IC2
ZD1
Semtech ACS8527
Semtech EZ1086CT-3.3 voltage regulator 3.3v
ZenerDiode BZV90C5V6
Connectors:
FrSync, MFrSync, O1P,O1N,SEC1,SEC2,O2
S1(optional)
S2(optional)
S3(optional)
S4(optional)
LNK
P1
SMB connector
7 way pin header
11 way pin header
2 way pin header
5 way pin header
3 way pin header
3 way terminal blocks
Misc
SW1,SW2
X1
LED
Piano DIL sw 8 way
12.8MHz CMAC E2747 or C-MAC CPFT9050
L.E.D
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Figure 3: ACS8527 EVB Component Layout of the Evaluation Board (Upper-side).
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Advanced Communications
ACS8527 EVB Evaluation Kit
ORDERING INFORMATION
DEVICE CODE
DESCRIPTION
ACS8527 -EVB
Line Card Protect ACS8527 Evaluation Kit
For additional information, contact the following:
Semtech Corporation Advanced Communications Products
E-mail:
sales@semtech.com acsupport@semtech.com
Internet:
http://www.semtech.com
USA:
Mailing Address:
P.O. Box 6097, Camarillo, CA 93011-6097
Street Address:
200 Flyn Road, Camarillo, CA 93012-8790
Tel: +1 805 498 2111, Fax: +1 805 498 3804
FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.
Tel: +886 2 2748 3380, Fax: +886 2 2748 3390
EUROPE:
Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire,
SO51 9DN, UK
Tel: +44 1794 527600, Fax: +44 1794 527601
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CERTIFIED
Semtech reserves the right to change specifications on catalog devices without notice. © Copyright Semtech Corp 2000
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