SC452 Datasheet

NOT RECOMMENDED FOR NEW DESIGN
SC452
Dual-Phase Single Chip
IMVP-6 Vcore Power Supply
POWER MANAGEMENT
Description
Features
The SC452 is a single chip high-performance PWM controller designed to power advanced IMVP-6™ processors.
On-chip support is provided for all of the IMVP-6 requirements, including Active Voltage Positioning, Geyserville-3
VID transitions, VID-controlled Deeper Sleep voltage setting, PSI# and DPRSL control, fast/slow C4 exit, and default Boot voltage.
Dual-Phase Solution with Integrated Drivers
Hysteretic Control for Fast Transient Response
Combi-Sense Provides Loss-Less Current Sensing
Dynamic Current Sharing
Active Voltage Positioning
True Differential Remote (die) Sensing
On-Chip Support for all IMVP-6 Power Management
Features
VID Programmed Deeper Sleep Voltage
Fast/Slow C4E Break-Event Support
Clock Enable (CLKEN#) Output
Delayed Power Good Signal with Blanking
Programmable Soft-Start and DAC Slew Control
Programmable OCP Threshold
Supports all Ceramic Decoupling Solutions
44 pin MLP (7x7)
Lead-free Package
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
The SC452 implements hysteretic control technology
which provides the fastest possible transient response
while avoiding the stability issues inherent to classical
PWM controllers. Semtech’s proprietary Combi-Sense®
technology provides a loss-less current sensing scheme
which is extremely robust and easy to lay out. Eliminating the sense resistors reduces costs and PCB area, plus
increases system efficiency. Integrated SmartDriver™
technology initially turns on the high side driver with ‘soft’
drive to reduce ringing, EMI, and capacitive turn-on of the
low side MOSFET, while also increasing overall efficiency.
Hysteretic operation adaptively reduces the SC452
switching frequency at light loads. Combined with an
automatic “power-save” mode which prevents negative
current flow in the low-side FET, system efficiency is significantly enhanced during light loading conditions. The
SC452 changes from dual-phase to single-phase operation whenever PSI# asserts, providing optimal efficiency
across the entire power range.
Applications
IMVP-6/6+ Notebook PCs
Embedded Applications
Graphics and Other Processor Cores
A 7-bit DAC, accurate to 0.85%, sets the output voltage
reference, and implements the 0.300V to 1.500V range
required by the processor. The DAC slew rate is externally
programmed to minimize transient currents and audible
noise. True differential remote sensing provides accurate point-of-load regulation at the processor die. Other
features include programmable soft-start, open-drain
IMVP6_PWRGD and CLKEN# outputs, dynamic current
sharing, over-voltage and programmable over-current protection. The SC452 is available in a space-saving 44 pin
MLP package.
February 22, 2006
1
www.semtech.com
To ICH7
or CPU
R7
10K
VCC SENSE
GND SENSE
IMVP PG
PSI#
CLKEN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON
To ICH7 DPRSLPVR
VID6
VID5
VID4
VID3
VID2
VID1
VID0
10K
1nF
2
R13
C12
1
R10
100k
10
R9
R14
10
54.9k
R8
10nF
C23
FB+
FB-
1
1
10nF
C24 2
2
5
6
7
8
9
10
11
CLKEN#1 1
VREF
2
HYS
3
CLSET
4
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CLKEN#1
VREF
HYS
CLSET
2
1
1
100 2
R19
C31
0.1μF/25V
+VDC
100
R3
2
C2 1
0.1μF/25V
1nF
1
C7
2
1
SC452
U1
2
1
0
1μF
2
C32
1
1μF
2
0
R20
29
28
27
26
25
24
23
CS1+
CS1CS2CS2+
ERROUT
VCCA
AGND
DAC
SS
DRP+
DRP-
1μF
C29
2
1
2
1
2
CR1
MBR0530
1
2
1
DAC
SS
1
1
R4
2
100pF
2
+V5S
2
100k
1
C25
2
10K
DRP+
DRP-
1nF
2
100pF
1
C30
1
R18
10nF
1
C13
1
C8
100k
C11
ERROUT
C16
VCCA
CS1N
CS2N
1uF
2
C6
1
BSTRCD1
MBR0530
CR4
CS2P
2
16.2k
33
32
31
30
2 BSTRCD2
1
R16
ISH
R5
2
1
CS1P
TG1
16.2k
DRN1
BG1
TG2
BG2
DRN2
BST2 1
2
C28
1
2
1
C1
1
2
1
1
CRC
R1
2
2
2
1nF
2
10pF
C17
10nF
1
C22
1μF
C14
2
10nF
10k
2
100pF
1
C18
1
R11
2
10.0
R22
1
Q1
No_Pop
2
0.1μF
C15
4
Q7
4
Q5
4
Q3
4
D
Q2
4
Q4
D
Q8
4
Q6
D
4
D
+VDC
Note: Route CS1x, CS2x, DRPx and FBx
as differential pairs.
D
4
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
BST1
VPR1
R2
FB-
+VDC
44
43 VPN1
42
41
40
39
38
37
36
35
34
DPRSL
VPN1
VIN1
BST1
TG1
DRN1
BG1
V5_1
EN
DPRSTP#
ISH1
PWRGD
VPN2
VIN2
BST2
TG2
DRN2
BG2
V5_2
PSI#
FB+
12
VPN2 13
14
15
16
17
18
19
20
21
22
9
8
7
6
5
3
2
1
9
8
7
6
5
D
3
2
1
GND
45
9
8
7
6
5
3
2
1
D
9
8
7
6
5
9
8
7
6
5
3
2
1
D
2
1
1
5
4
2
6
10μF
25V
2
C19
2
5
1
3
0.5μH
L2
10μF
25V
2
C21
1
1
C5
10μF
25V
4
2
6
2
10μF
25V
C20
6
1
7
4
8
2
3
1k
R12
L1
1
C4
10μF
25V
2
1
CR2
MBRS14OL
10μF
25V
2
CR3
MBRS140L
2
1
5
1
3
1
C3
R6
0.0005
R17
0.0005
1
330μF
C9
330μF
C26
330μF
C10
+VCC_Core
[email protected]
48A
Note: Terminate droop
feedback to sense
resistors with Kelvin
connections.
2
3
2
1
9
8
7
6
5
3
2
1
9
8
7
6
5
3
2
1
9
8
7
6
5
3
2
1
1
2
+VDC
1
2
2
VPR2
C27
1
© 2006 Semtech Corp.
2
+V5S
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Typical Application Circuit
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the
Electrical Characteristics section is not implied.
Parameter
Condition
Min
Max
Units
-0.3
6.5
V
Static
-0.3
30
V
Transient <100ns
-0.3
34
V
-0.3
6
V
Static
-2
25
V
Transient <100ns
-5
29
V
DRN 1, 2-0.3
BST1, 2+0.3
V
-0.3
V5_1, 2+0.3
V
-0.3
25
V
VPN1, VPN2 to PGND
-0.3
VIN1, 2+0.3
V
PGND to AGND
-0.3
0.3
V
-0.3
VCCA+0.3
V
Supply Voltages VCCA V5_1, V5_2
BST1, BST2 to PGND
BST1, BST2 to DRN1, DRN2
TG1, TG2 to PGND
BG1, BG2 to PGND
VIN1, VIN2 to PGND
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
DRN1, DRN2 to PGND
All other pins to AGND
Thermal Resistance Junction to Ambient
θJA
Operating Junction Temperature Range
TJ
-40
125
o
TSTG
-65
150
o
TIRreflow
260
o
VESD
2
Storage Temperature Range
Peak IR Reflow (10-40sec)
ESD Rating (Human Body Model)
29
21
C/W
o
C
C
C
kV
Electrical Characteristics
Unless otherwise specified, VccA = V5_1 = V5_2 =5 V. -40<TJ<+125°C.
Parameter
Condition
Min
Typ
Max
Units
VccA,V5_1, V5_2
Operating Range
4.5
5.0
5.5
V
VBAT Operating Range
4.5
24
V
Supplies (VccA, V5_1, V5_2)
VccA, V5_2 UVLO
VccA Current
Rising
4.25
4.4
4.5
V
Hysteresis Falling
50
150
250
mV
10
μA
0.6
1.0
mA
10
15
mA
Disabled
In UVLO
Operating (Static)
© 2006 Semtech Corp.
5
3
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Condition
Min
Typ
Max
Units
8
12
mA
Disabled
10
μA
In UVLO
10
μA
1.2
mA
10
μA
120
200
μA
0.9
1.2
mA
Supplies (VccA, V5_1, V5_2) (Cont.)
VccA Operating Current
Operating (Deeper Sleep)
V5_1 Current
Operating, Static, TG1 Low
V5_2 Current
0.3
0.9
Disabled
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
In ULVO
Operating, Static, TG2 Low
Vin1 and Vin2 Current
0.3
Static TG when respective TG Low
500
μA
Static TG when respective TG High
900
μA
When in Powersave
0
μA
(EN, VID[6:0],
VID[6:0], DPRSLP,
DPRSL, PSI
#)
Logic Inputs (EN,
DPRSTP#,
PSI#)
Enable Threshold
VID[6:0], DRPSLP, DPRSTP, PSI#
VID[6:0], DPRSL, PSI # Threshold
Threshold
Input Impedance
0.8
2.0
V
0.45
0.65
V
40
kΩ
85°C)
Reference (DAC, SS, VREF), (0 < TJ <125°C)
DAC Error + Internal Offset
DAC Sink/Source Ability
SS Slew Current
1.5000V - 0.7625V
-0.85
+0.85
%
0.75V - 0.50V
-7
7
mV
0.4875
- 0.30V
0.50 - 0.30V
-14
14
mV
0.3V < DAC <1.5V
|50|
Start-Up
8
12
16
μA
Operating
102
120
138
μA
Slow DPRSLP Exit
(x = operating ISS)
x/6
x/5
x/4
Discharge (SS = 0.5V)
15
SS Discharge Threshold
μA
mA
50
100
mV
Boot Voltage
1.176
1.2
1.224
V
Boot Delay(1)
10
30
100
us
VREF Accuracy
1.97
2.00
2.03
V
VREF Sink/Source Ability
|1.5|
© 2006 Semtech Corp.
4
mA
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Condition
Min
Typ
Max
Units
Remote Sense (FB+, FB-)
Input Impedance
14
Bandwidth(1)
kΩ
2
MHz
Droop (DRP+, DRP-)
Input Bias Current
Droop Input Offset
μA
DRP+ = 1.5V, DRP- = 1.48V
9.5
10
10.5
V/V
(25°C only)
-0.4
0
0.4
mV
0 to 85°C
-85°C
-0.5
0
0.5
mV
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Gain
±1
Maximum Input Signal(1)
20
mV
Bandwidth(1)
0.8
MHz
Error Amplifier (ERROUT)
Gain
Bandwidth(1)
19
2
MHz
Current Sensing (CS1+, CS1-, CS2+, CS2-, ISH)
CS1, 2 + CS1, 2 Bias Currents
CS+ = CS- = 1.5V
±1
μA
3.3
6.6
V/V
CS Gain for Switchingg
2.7
5.4
Maximum Input Signal(1)
450
mV
2
MHz
CS Bandwidth(1)
Zero-Crossing Detector Offset
-6
Low Pass Filter Corner
Frequency(1)
50
© 2006 Semtech Corp.
5
3.0
6.0
80
6
mV
125
kHz
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Condition
Min
Typ
Max
Units
Current Sharing Open Loop Gain
20
40
30
60
45
90
Current Sharing Range (% relative to VHYS)
26
52
40
80
54
108
%
Current Sharing Offset
-3.0
+3.0
mV
-0.9
-0.35
V
±1
I500I
nA
μA
Current Sensing (CS1+, CS1-, CS2+, CS2-, ISH) (Cont.)
Current Sharing Disable
Threshold Relative to VccA
Voltage on ISH pin
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Hysteresis Setting (HYS, CLSET)
HYS, CLSET Input Bias Current
HYS Error (internal HYS difference from
TG Hi to TG lo as a percentage of
voltage applied at HYS pin)
CLSET Voltage (internal hysteresis
setting relative to voltage applied at
CLSET pin) CLSET = 1.2V
Dual Phase
-18
-24
-20
-16
-22
%
Single Phase
±36
±40
±44
%
TG High
160
200
240
mV
TG Low
128
160
192
mV
Single Phase TG Low
90
120
150
mV
CLKEN#, PWRGD
High Impedance
1
μA
CLKEN#, PWRGD = 0.1V
100
Ω
HYS = 1V
Powergood (CLKEN#, PWRGD)
Leakage
On Resistance
PWRGD Start-Up Delay
Fixed Over-Voltage Protection Threshold
3
6.5
10
ms
1.75
1.8
1.85
V
Power Good Window Upper Threshold
FB Rising Relative DAC
+160
+200
+240
mV
Power Good Window Lower Threshold
FB Falling Relative DAC
-360
-300
-240
mV
Power Good Window Lower Hysteresis
FB Rising Relative DAC
30
50
90
70
mV
© 2006 Semtech Corp.
6
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Condition
Min
Typ
Max
Unit
1.75
2.0
2.25
A
RTG_UP, DRN < 0.5V, 25°C
4.1
5.8
7.5
Ω
RTG_UP, DRN < 0.5V,
-40 to 125°C
3.48
5.8
9.24
Ω
RTG_UP, DRN > 0.5V, 25°C
0.9
1.3
1.7
Ω
RTG_UP, DRN > 0.5V,
-40 to 125°C
0.76
1.3
2.1
Ω
RTG_DN , 25°C
0.42
0.6
0.78
Ω
RTG_DN , -40 to 125°C
0.34
0.6
1.01
Ω
CTG = 3nF
17
22
27
ns
CTG = 3nF
9
12
15
ns
From Hysteretic Comparator
Inputs to Driver Output
30
45
60
ns
10
20
30
ns
3.5
4.0
4.5
A
RBG_UP at 25°C
0.9
1.3
1.7
Ω
RBG_UP at -40 to 125°C
0.76
1.3
2.1
Ω
RBG_DN at 25°C
0.35
0.5
0.65
Ω
RBG_DN at -40 to 125°C
0.28
0.5
0.86
Ω
Rise Time(1, 2)
CBG = 3nF
5
7
9
ns
Fall Time(1, 2)
CBG = 3nF
2.5
3.5
4.5
ns
600
nA
High-Side Driver (TG1, TG2, BST1, BST2, DRN1, DRN2)
Peak Current(1,2)
Rise Time (1,2)
Fall Time
(1,2)
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
On Resistance
Propagation Delay (1,2)
Shoot-Thru Protection Delay (1)
Low-Side Driver (BG1, BG2, V5_1, V5_2, PGND1, PGND2)
Peak Current(1, 2)
On Resistance
VPN (VPN1, VPN2, VIN1, VIN2)
Tri-State Leakage
On Resistance
Propagation Delay(1, 2)
© 2006 Semtech Corp.
-600
Source
100
200
400
Ω
Sink
100
200
400
Ω
From Hysteretic Comparator
Inputs to Driver Output
30
45
60
ns
7
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Pin Configuration
Ordering Information
DRN1
39
38
37
36
35
ISH
TG1
40
DPRSTP#
BST1
41
EN
VIN1
42
V5_1
VPNI
43
BG1
DPRSL
44
Device(2)
VREF 2
HYS 3
CLSET 4
VID6 5
14
15
VPN2
VIN2
BST2
Pin Descriptions
Pin
#
Pin#
16
17
18
Pin
PinName
Name
1
CLKEN#
2
VREF
3
HYS
4
CLSET
5
VID6
6
VID5
7
VID4
8
VID3
9
VID2
10
VID1
11
VID0
12
IMVP6_PWRGD
© 2006 Semtech Corp.
-40°C to +125°C
33
CS1+
32
CS1 -
31
CS2 -
30
CS2+
29
ERROUT
28
VCCA
27
AGND
26
DAC
SC452EVB
Evaluation Board
Notes:
1) Only available in tape and reel packaging. A reel contains 3000
devices.
2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
3) Lead-free package compliant with J-STD-020B. Qualified to support
maximum IR Reflow temperature of 260°C for 30 seconds. This product is fully WEEE and RoHS compliant.
19
20
21
22
25
SS
24
DRP+
23
DRP -
f id
13
FB-
12
PWRGD
VID0 11
FB+
VID1 10
PSI#
9
V5_2
VID2
BG2
8
MLP-44
SC452IMLTRT
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
VID3
DRN2
7
PGND
PAD
TG2
VID5
VID4
Temp Range (TJ)(3)
34
CLKEN# 1
6
Package(1)
Pin
Description
Pin Description
Start Clock Indicator - open drain output. Active low.
Internal reference voltage (2V). Bypass to AGND with a TBD
pF capacitor.
1nF capacitor.
Core comparator hysteresis. A resistor divider on this pin sets the hysteresis voltage.
Current Limit Set. A resistor divider on this pin sets the OCP threshold.
VID MSB.
VID LSB.
IMVP6 Power Good - open drain output.
8
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Pin Descriptions (Cont.)
PinPin#
#
Pin
PinName
Name
PinDescription
Description
Pin
13
VPN2
Virtual Phase Node for Phase 2. Connect an RC between this pin and the output sense
point to enable Combi-Sense operation.
14
VIN2
Input power to the DC-DC converter. Used as supply reference for internal Phase 2
Combi-Sense circuitry.
15
BST2
Phase 2 Bootstrap pin. A capacitor is connected between BST and DRN to develop the
floating voltage for the high-side MOSFET.
16
TG2
Phase 2 output drive for the top (switching) MOSFET.
17
DRN2
18
BG2
Phase 2 output drive signal for the bottom (synchronous) MOSFET.
19
V5_2
Input supply for Phase 2 low-side gate drive. Connect to 5V.
20
PSI#
Platform PSI-2 control signal.
21
FB+
Remote die sense of core voltage. Connect to VCC_SENSE at the CPU socket.
22
FB-
Remote GND sense. Connect to VSS_SENSE at the CPU socket.
23
DRP-
Inverting input to droop amplifier.
24
DRP+
Non-inverting input to droop amplifier.
25
SS
Soft-start. An external cap at this pin defines the soft-start ramp.
26
DAC
DAC output. An external cap at this pin defines VID transition timing.
27
AGND
Analog ground.
28
VCCA
IC supply. Connect to 5V.
29
ERROUT
30
CS2+
Non-inverting input to Phase 2 Combi-Sense amplifier.
31
CS2-
Inverting input to Phase 2 Combi-Sense amplifier.
32
CS1-
Inverting input to Phase 1 Combi-Sense amplifier.
33
CS1+
Non-inverting input to Phase 1 Combi-Sense amplifier.
34
ISH
35
DPRSTP#
36
EN
37
V5_1
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
This pin connects to the junction of the Phase 2 switching and synchronous MOSFETs .
This pin can be subjected to a -2V minimum relative to PGND without affecting operation.
© 2006 Semtech Corp.
Error Amplifier Compensation Pin.
Used for compensation of the ISHARE amplifier.
DPRSTP# control pin for fast/slow C4E event. Active high.
Enable control. Active High.
Input supply for Phase 1 low-side gate drive. Connect to 5V.
9
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Pin Descriptions (Cont.)
PinName
Name
Pin
Pin Description
Pin
Description
38
BG1
39
DRN1
40
TG1
Phase 1 output drive for the top (switching) MOSFET.
41
BST1
Phase 1 Bootstrap pin. A capacitor is connected between BST and DRN to
develop the floating voltage for the high-side MOSFET.
42
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Pin##
Pin
Phase 1 output drive signal for the bottom (synchronous) MOSFET.
This pin connects to the junction of the Phase 1 switching and synchronous
MOSFETs . This pin can be subjected to a -2V minimum relative to PGND without
affecting operation.
VIN1
Input power to the DC-DC converter. Used as supply reference for internal Phase 1
Combi-Sense circuitry.
VPN1
Virtual Phase Node for Phase 1. Connect an RC between this pin and the output sense
point to enable Combi-Sense operation.
44
DPRSL
Deeper Sleep control pin. Active high.
PAD
PGND
Power Ground for Drivers 1 and 2. Pad must be soldered to Power Ground plane.
43
© 2006 Semtech Corp.
10
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Block Diagram
DAC
VID
[6:0]
+
DAC
ERROUT
-
SS
ERROR AMP
FB-
-
FB+
+
HYSTERETIC COMPARATOR
CO
+
DRP+
CO1
-
+
-
DRP-
CO2
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
I-limit
Hys hi
SELECT
CURRENT SENSE AMP
CS1+
CS1-
CS1
+
-
LP
FILTER
Hys_lo
+
CO
CS2+
CS2-
+
SELECT
ISH
CS2
-
PSI#
DPRSTP
CS1
-
CS2
+
CURRENT SENSE AMP
+
DPRSLP
PHASE
PHASE
CONTROL
CONTROL
CS2
-
CS1
CO
-
SELECT
LP
FILTER
SELECT
-
CL hi
+
CL lo
I-limit
CO
EN
REFERENCE
&
UVLO
+
-
VREF
CL_hi
CLSET
VID [6:0]
CL_lo
DAC
CLKEN#
PWRGD
LOGIC
3ms
START UP
TIME
HYS_hi
PWRGD
DRIVERS 1,2
HYS
VIN 1,2
HYS_lo
VPN 1,2
EN
PGNDN
EN
BST 1,2
VccA
VccA
AGND
TG 1,2
CROSS
CONDUCTION
PROTECTION
CO 1 or
CO 2
VS 1,2
CS 1 or
CS 2
© 2006 Semtech Corp.
DRN 1,2
11
ZERO
CROSSING
BG 1,2
PGND 1,2
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information
INTRODUCTION:
Thus, customers can choose the amount of cost and performance they need for any given design.
The SC452 is a new generation of hysteretic converter
which combines the best features of Semtech’s hysteretic converter technology with the benefits of Semtech’s
patented Combi-Sense technology. The SC452 provides a
complete solution to Intel’s IMVP-6 requirements.
The SC452 also provides a full range of features.
All IMVP-6/6+ functions are implemented:
¨ EN
¨ CLKEN#
¨ IMVP-6 PWRGD
¨ DPRSLPVR
¨ DPRSTP#
¨ PSI#
¨ Geyserville-3 VID changes
¨ Fast-C4 Exit
¨ All ‘1s’ soft-OFF state
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
In the SC452, the ripple for the hysteretic switching control is provided by Combi-Sense current feedback. This
provides several advantages over plain voltage-mode hysteretic converters, and other topologies such as constant
on-time which switch on voltage ripple.
• No minimum amount of output ripple is required so
there are no controller-induced limits on capacitor value
or ESR.
• No current sense resistors are required, resulting in
higher converter efficiency.
• The large signal magnitude afforded by Combi-Sense
(4-5 times that of inductor DCR current sensing) makes
the layout much less sensitive to noise.
•
A 2.00V voltage reference is provided
•
Separate hysteresis and current limit settings
•
A full suite of protection features is provided:
¨ Over-current protection (OCP)
¨ Fixed and DAC-referenced over-voltage
protection (OVP)
¨ Over-temperature protection (OTP)
¨ Undervoltage detection via PWRGD
• Full differential feedback of the output voltage from the
CPU die is enabled.
Because the basic control is hysteretic, the SC452 provides the fastest possible transient response without
switching at very high frequencies. This results in higher
efficiency with less expensive parts because switching
losses are reduced. Only the Combi-Sense ripple is used
for the regulation loop, so the load-line accuracy is not affected by tolerances in RDS(ON) or inductor DCR. However, because of the large signal magnitude, the DC is kept
for the current limiting and current sharing functions.
All protection features are latching, and are either reset by
recycling power or toggling the EN signal.
THEORY OF OPERATION
Voltage Regulation:
Referring to the block diagram on the preceding page, the
hysteretic comparator is the heart of the converter. The
“+” input corresponds roughly to the CMPREF node of our
older generations of IC; the “-” input is similar to CMP. In
order to regulate, the hysteretic comparator needs the following information:
Load-line control is provided by a dedicated droop amplifier with uncommitted inputs. This provides users with
maximum flexibility, as the droop source can be any of the
following:
•
•
•
PCB copper trace
Inductor DCR
Sense resistor
© 2006 Semtech Corp.
•
•
•
•
•
12
DAC (reference) voltage
Droop voltage proportional to IOUT
Feedback voltage
Hysteresis voltage
Hysteresis ripple
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
CMPREF receives the reference, voltage feedback and
droop information. The reference is produced by the integrated seven-bit DAC. The feedback voltage is received
by the full differential amplifier from the CPU socket. The
droop amplifier reduces the voltage at the “+” node of the
differential amplifier as the output current increases to
produce the required linear load line. A third amplifier,
labeled the “Error Amplifier”, multiplies the difference
between the “ideal” voltage (DAC minus droop) and the
actual voltage (FB+ minus FB-) for faster response. This
signal is the reference for the hysteretic comparator.
Current Limit Regulation:
In Current Limit, the voltage hysteretic converter is overridden by the current limit hysteretic comparator, and the
TG pulse is terminated when the output of the current
sense amplifier reaches the CL_hi threshold and BG is
terminated at the CL_lo threshold. These thresholds are
set from the CLSET resistor divider:
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
CL_hi = 0.33 * V(clset)
CL_lo = 0.20 * V(clset)
CMP has the ripple signal derived from the Combi-Sense
inputs plus the hysteresis signal. The DC is stripped from
the ripple signals by the combination of low-pass filter and
summing amplifiers. Phase 2 has a current sharing input derived from an averaged difference between the two
phases. The ripple inputs are fed to a summing block via
a multiplexer which is synchronized to the active phase
with the select output. The hysteresis signal is added at
the summing block. The hysteresis voltage is set directly
by the resistor divider from the 2V REF output.
Current limit pulses continue until 32 pulses after the
voltage droops to the PWRGD low threshold; then the controller latches off. This current limit algorithm has been
used in several generations of IMVP controllers and have
been proven to be extremely robust.
Start-Up and Shut-Down Sequences:
For the SC452 to start up, VCCA, V5_1, and V5_2 must
reach their under-voltage lockout (UVLO) thresholds (4.4V
typ.) then the EN signal goes high. The DAC drives 12μA
(typ.) into the soft-start capacitor on the SS pin. The SS
and DAC pins rise slowly until the BOOT voltage (1.2V, fixed
internally) is reached. The controller remains at BOOT
voltage for ~30μs. At the end of the BOOT interval, the
VID(6:0) lines are considered valid and CLKEN# is driven
low. The controller will slew at a 120μA rate to the VID-defined value. Approximately 6ms after the voltage hits the
PWRGD threshold, IMVP-6_PWRGD goes high, and startup is complete.
The figure on Page 14 illustrates the basic switching control. Starting with the Select line (top plot, green trace) on
Phase 2, and both CO signals low. Accordingly, both bottom gate (BG) signals are on and the inductor currents in
both phases are discharging as shown by the Phase 1 (orange) and Phase 2 (blue) ripple signals in the lower plot.
When CMP discharges to CMPREF, the select line toggles,
CO1 turns on, and subtracts V(hys_hi) from CMP. CO1
remains high until CMP again charges to CMPREF. Then,
CO1 switches low, adding V(hys_lo) to CMP. This state is
held until CMP again discharges to CMPREF. Then, the
select line toggles, CO2 turns on, and the cycle repeats.
In a normal shutdown, the EN signal is driven low, the
TG and BG signals are driven low, tri-stating the power
chains. An approximately 100Ω resistor on the FB+ signal
discharges Vcore slowly and prevents normal amounts of
leakage from pulling Vcore high. The DAC and other internal circuitry is shut down, entering a very low power
(<10μA typical) state. A UVLO will also result in this type
of shutdown.
In Dual Phase mode, V(hys_lo) is zero; C0 of the initial
phase remains low while the alternate phase is in control,
so BG of the initial phase remains on through the alternate cycle and, as a result, the second phase will terminate at approximately -V(hys). During single phase operation, V(hys_lo) = -V(hys).
© 2006 Semtech Corp.
13
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
* D:\Products\SC452\Model_04Jun04\SC452_CBM_Top-level.sch
Date/Time run: 06/04/04 16:18:36
(A) SC452_CBM_Top-level.dat (active)
6.0V
IC SIGNALS
Temperature: 27.0
CO2
4.0V
CO1
Phase 1
0V
elect
N
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FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
2.0V
Phase 2
V(HS27.HS19:select)/2
V(HS27.CO1)/4 +3
V(HS27.CO2)/4+4
LOG SIGNALS
1.10V
CMPREF
CMP
1.05V
Ripple - Phase 1
1.00V
Vdac
Vcore
SEL>>
0.96V
220us
V(DAC)
V(Vcore)
V(HS27.CMP)-0.55V
Date: June 04, 2004
© 2006 Semtech Corp.
221us
V(CS2+)-V(CS2-)+1V
Ripple - Phase 2
222us
V(CS1+)-V(CS1-) +1V
Time
Page 1
14
223us
V(HS27.CMPREF)-0.55V
224us
Time: 17:13:48
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
VID
DPRSL
PSI#
Status
Load
SC452
Mode
1
0
Deeper Sleep
Icc < 3A
1-phase
1
1
Deeper Sleep
Icc > 3A
1-phase
0
0
Active; Med.
Power Potential
9A < Icc
<16A
1-phase
Icc > 15A
2-phase
tSFT_START_VCC
VR_ON
-12%
VBOOT
VVID
tBOOT
VCC_CORE
tBOOT-VID-TR
tCPU_UP
CPU_UP
-12%
VCCP
VCCP_UP
tVCCP_UP
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
CLK_ENABLE#
0
tCPU_PWRGD
IMVP6_PWRGD
1
Active; Full
Power Potential
Response to Power Control Inputs:
Figure A - Power On Sequencing Timing Diagram
VR_ON
The SC452 always operates with discontinuous mode
power saving enabled, always saving power at light load
regardless of the status of DPRSL or PSI#. PSI# signal is
used to indicate the expected max level of currents demanded from IMVP6. In essence, as DPRSTP# (DPRSLPVR)
indicates a voltage demand, PSI# indicates a current demand. PSI# signal can be asserted during active (LFM to
HFM) execution. The purpose is to command the voltage
regulator to maximize its efficiency through the widest
range of current loads, (i.e., DeeperSleep to HFM).
tPWRDOWN1
IMVP6_PWRGD
MCH_PWRGD
CPU-UP
VCCP-UP
VCC_CORE
Besides the EN signal, described on Page 13, the SC452
reacts to the other control signals in the following manner:
tPWRDOWN2
PSI# transitions no longer occurs during Deeper Sleep
mode. While in active mode, it is expected that PSI# signal toggle occurs at the same Vcc-core voltage level VID.
The reason to have same VID voltage requirement is that
the superimposed charge current required to charge the
output decoupling to a new level of voltage can overcome
single phase mode of operation (if used), during positive
dv/dt events (such as Enhanced Intel SpeedStep® or
Deeper Sleep exit).
VCCP
VCC_MCH
Figure B - Power Off Sequencing Timing Diagram
© 2006 Semtech Corp.
15
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
In active mode, enhanced Intel SpeedStep transitions can
occur. SC452 can recognize a step-up in voltage transition and revert operation to full power mode to supply the
bulk capacitor charge currents superimposed on the processor active mode current. During Deeper Sleep, PSI#
indicates a very low current state. Regulator can enter
asynchronous mode of operation. In rare occasions, if the
PSI# is deasserted during Deeper Sleep, this is an indication of a high leakage component that may not benefit
from asynchronous operation.
A +/-0.85% 7-bit digital-to-analog converter (DAC) serves
as the programmable reference source of the Core Comparator. Programming is accomplished by logic voltage
levels applied to the DAC inputs. The VID code vs. The
DAC output is shown in the tables below. There are 7 voltage identification pins on mobile processor. These signals
can be used to support automatic selection of Vcc_core
voltages.
They are needed to cleanly support voltage specification
variations on current and future processors. VID [6:0]
are defined in the table below. The VID [6:0] signals are
0V to Vccp CMOS level inputs. These signals are not to
be pulled up externally as this will damage the processor.
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
In the Deeper Sleep state, SC452 recognizes Deeper
Sleep exit state and its associated voltage transitions and
reverts operation to full power mode to allow for the bulk
capacitor charge currents to superimpose with the processor active mode current.
© 2006 Semtech Corp.
16
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Table 1.
VID vs. VCC_CORE Voltage (Active Mode)
Table 2.
VID vs. VCC_CORE Voltage
(Active Mode/Deeper Sleep Dual Mode Region)
VID
VDAC
VID
VDAC
VID
VDAC
VID
VDAC
6 5 4 3 2 1 0
V
6 5 4 3 2 1 0
V
6 5 4 3 2 1 0
V
6 5 4 3 2 1 0
V
0 1 0 1 0 0 0 1.0000 0 1 1 1 1 0 0 0.7500
0 0 0 0 0 0 1 1.4875 0 0 1 0 1 0 1 1.2375
0 1 0 1 0 0 1 0.9875 0 1 1 1 1 0 1 0.7375
0 0 0 0 0 1 0 1.4750 0 0 1 0 1 1 0 1.2250
0 1 0 1 0 1 0 0.9750 0 1 1 1 1 1 0 0.7250
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
0 0 0 0 0 0 0 1.5000 0 0 1 0 1 0 0 1.2500
0 0 0 0 0 1 1 1.4625 0 0 1 0 1 1 1 1.2125
0 1 0 1 0 1 1 0.9625 0 1 1 1 1 1 1 0.7125
0 0 0 0 1 0 0 1.4500 0 0 1 1 0 0 0 1.2000
0 1 0 1 1 0 0 0.9500 1 0 0 0 0 0 0 0.7000
0 0 0 0 1 0 1 1.4375 0 0 1 1 0 0 1 1.1875
0 1 0 1 1 0 1 0.9375 1 0 0 0 0 0 1 0.6875
0 0 0 0 1 1 0 1.4250 0 0 1 1 0 1 0 1.1750
0 1 0 1 1 1 0 0.9250 1 0 0 0 0 1 0 0.6750
0 0 0 0 1 1 1 1.4125 0 0 1 1 0 1 1 1.1625
0 1 0 1 1 1 1 0.9125 1 0 0 0 0 1 1 0.6625
0 0 0 1 0 0 0 1.4000 0 0 1 1 1 0 0 1.1500
0 1 1 0 0 0 0 0.9000 1 0 0 0 1 0 0 0.6500
0 0 0 1 0 0 1 1.3875 0 0 1 1 1 0 1 1.1375
0 1 1 0 0 0 1 0.8875 1 0 0 0 1 0 1 0.6375
0 0 0 1 0 1 0 1.3750 0 0 1 1 1 1 0 1.1250
0 1 1 0 0 1 0 0.8750 1 0 0 0 1 1 0 0.6250
0 0 0 1 0 1 1 1.3625 0 0 1 1 1 1 1 1.1125
0 1 1 0 0 1 1 0.8625 1 0 0 0 1 1 1 0.6125
0 0 0 1 1 0 0 1.3500 0 1 0 0 0 0 0 1.1100
0 1 1 0 1 0 0 0.8500 1 0 0 1 0 0 0 0.6000
0 0 0 1 1 0 1 1.3375 0 1 0 0 0 0 1 1.0875
0 1 1 0 1 0 1 0.8375 1 0 0 1 0 0 1 0.5875
0 0 0 1 1 1 0 1.3250 0 1 0 0 0 1 0 1.0750
0 1 1 0 1 1 0 0.8250 1 0 0 1 0 1 0 0.5750
0 0 0 1 1 1 1 1.3125 0 1 0 0 0 1 1 1.0625
0 1 1 0 1 1 1 0.8125 1 0 0 1 0 1 1 0.5625
0 0 1 0 0 0 0 1.3000 0 1 0 0 1 0 0 1.0500
0 1 1 1 0 0 0 0.8000 1 0 0 1 1 0 0 0.5500
0 0 1 0 0 0 1 1.2875 0 1 0 0 1 0 1 1.0375
0 1 1 1 0 0 1 0.7875 1 0 0 1 1 0 1 0.5375
0 0 1 0 0 1 0 1.2750 0 1 0 0 1 1 0 1.0250
0 1 1 1 0 1 0 0.7750 1 0 0 1 1 1 0 0.5250
0 0 1 0 0 1 1 1.2625 0 1 0 0 1 1 1 1.0125
0 1 1 1 0 1 1 0.7625 1 0 0 1 1 1 1 0.5125
1 0 1 0 0 0 0 0.5000
Table 1 - reflects VID codes to be used in Active state. The voltages represented cover HFM through LFM.
© 2006 Semtech Corp.
Table 2 - reflects VID codes to be used for both Active and Deeper Sleep
states.
17
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
DAC Slew Rate Control:
Table 3.
VID vs. VCC_CORE Voltage (Deeper Sleep/
Extended Deeper Sleep Dual Mode Region)
VID
VDAC
VID
VDAC
6 5 4 3 2 1 0
V
6 5 4 3 2 1 0
V
The DAC has integrated slew-rate control with multiple
current settings to charge and discharge the soft-start capacitor. The slowest setting is used for soft-start, a medium setting for slow C4-exit (DPRSLVR=’1’, DPRSTP#=’1’)
and a fast setting for all other VID transitions.
1 0 1 0 0 0 1 0.4875 1 0 1 1 0 1 0 0.3750
Power Supply Protection:
1 0 1 0 0 1 0 0.4750 1 0 1 1 0 1 1 0.3625
A UVLO circuit consists of a comparator that monitors the
input supply voltage level, 5V. The SC452 is in UVLO mode
when its supply voltage has not ramped above the upper
threshold or has dropped below the lower threshold. The
output of the UVLO comparator, gated with the ENABLE
signal, turns on or off the internal bias, enables or disable the SC452 output, and initiates or resets the softstart timer. If an UVLO occurs, a fault is set and SC452 is
disabled until the system has shut down (and reapplied
power), or the enable input signal to the SC452 has toggled states.
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
1 0 1 0 0 1 1 0.4625 1 0 1 1 1 0 0 0.3500
1 0 1 0 1 0 0 0.4500 1 0 1 1 1 0 1 0.3375
1 0 1 0 1 0 1 0.4375 1 0 1 1 1 1 0 0.3250
1 0 1 0 1 1 0 0.4250 1 0 1 1 1 1 1 0.3125
1 0 1 0 1 1 1 0.4125 1 1 0 0 0 0 0 0.3000
1 0 1 1 0 0 0 0.4000 1 1 1 1 1 1 1
OFF
1 0 1 1 0 0 1 0.3875
Table 3 - reflects VID codes likely to represent Deeper Sleep and extended versions of Deeper Sleep State.
The OVP circuit of SC452 monitors the processor core
VCC_CORE voltage for an over-voltage condition. If the FB
voltage is 200mV greater than the DAC-Droop (i.e., out of
the power good window), the SC452 will latch off and hold
the low-side driver on permanently. Either the Power or
EN must be recycled to clear the latch. The latch is disabled during soft-start and VID/DeeperSleep transitions.
For safety, the latch is enabled if the FB voltage exceeds
1.8V even during VID/DeeperSleep transitions.
DAC Operation Below 0.3000V:
The SC452 responds to DAC codes corresponding to
voltage values below 0.3V by producing voltages less
than 0.3V; however, the tolerance of these signals is not
specified or guaranteed. In the case of the ‘111 1111’
VID code, the SC452 holds BGx and TGx low, preventing
switching from occurring. In addition, a ~50Ω FET connected from VCORE to GND is turned on to prevent system
leakage from charging up the VCORE rail.
© 2006 Semtech Corp.
The device will be disabled and latched off when the internal junction temperature reaches approximately 160°C.
Either the Power or EN must be recycled to clear the
latch.
18
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Design Procedure
(Based on SC452 R2 calculation with DCR Droop and R-Droop
Method. In this design procedure, we are going to use the specifications required by the Intel’s IMVP VI Napa Platform T&L (Yonah)
Processor):
Important requirements and design constants are defined below:
3
3.1415926 , k 103, M 106, mil 10
12,
9,
p 10
n 10
V INMAX
20 ˜ V
V INMIN
10 V
V INNOM
19 ˜ V
V HFM_NL
1.2875
I LKGMAX
1.6 A
I HFM_FL
36 A
R IMVP 2.1
6
P 10
mV
A
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
3 V
VHFM_FL VHFM_NL RIMVP ˜ IHFM_FL
The required droop per phase at full load is:
VDP R IMVP ˜ IHFM_FL
STEP 1: Output Inductor and Capacitor Selection
Output capacitance and ESR values are a function of
transient requirements and output inductor value. Figure 1 illustrates the response of a hysteretic converter
to a positive transient: In a hysteretic converter with
adaptive voltage positioning, like the SC452, two conditions determine if you meet the positive transient requirements since there are no transient specifications
in IMVP IV:
A : ESRMAX d RIMVP
Figure 1 - Hysteretic Converter Response
to a Positive Transient
The first condition is easy to see; if the ESR is too high,
the transient response will fail.
In the second condition, because the hysteretic converter
responds in < 100ns, the capacitor does not droop very
far before the inductor current starts ramping up. (This
is not true of control schemes where time constants in
the error amplifier cause delays.) Once the inductor current starts to rise, the increasing DV of the capacitor is
offset by reduced DV from the ESR, so DV is constant. If
the DV due to the charge taken from the capacitor before the inductor current reaches the load current (see
the shaded area above) is less than VIMVP, then the
transient response will pass.
Since HFM (High Frequency Mode) has the most severe
requirements, the other modes will be satisfied by a design optimized for HFM. The maximum ESR requirement
to meet the transient requirement is:
C : ESRMAX B : VIMVP t deltaV C OUT © 2006 Semtech Corp.
ESR MAX
19
RIMVP
3
2.1000 u 10
:
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
This value of inductance is required up to maximum load.
Inductors with a “swinging choke” characteristic, where the
zero current value of inductance is much less than the full
load current inductance can be used, as long as the above
restriction is met. Then, the worst-case (low input voltage)
response time (the time for the current to reach the new
transient value) is:
1
For the second condition, we need to know the inductor
value, which is a function of the highest desired switching
frequency. The maximum frequency occurs at the highest input voltage. As a reasonable compromise between
efficiency and component size, a maximum switching
frequency of 300kHz or less per phase is desired. Since
we are analyzing the minimum inductance for one phase,
the ripple voltage will actually be twice the amount of the
specified output ripple, since the ripple voltage from each
phase will tend to cancel. Please consult the data for your
specific processor. Note: The desired ripple amount comes
L1 IHFM_FL
dT
VINMIN
ILKGMAX
2
VHFM_NL
VHFM_NL
dMIN
FS
VINMAX
250kHz
VRIPPLE
10m V
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
from Intel’s IMVP-6 Rev 0.5 specs.
dT
ESR MAX
LMIN
dMIN
VINMAX
VHFM_NL
2.1000 10
361.3852 10
9
F. C
MINP
H
CMINP
L2
0.47 μH
© 2006 Semtech Corp.
ILKGMAX
256.6036 10
dT
2 10
7
sec
2 VDP
6
F
Selected COUT = 330µF x 6 to meet transient requirements.
This condition applies only to the positive transient.
Load Step:
0.47 μH
IHFM_FL
Ω
Selected L = 470nH as the next closest value.
L1
s
ESRMAX
FS 2VRIPPLE
3
9
Add ~200ns for the propagation delay from a change at
the output to the MOSFET switch turning on in reaction
due to the minimum on time requirement of the IC. Since
the shaded area is triangular, the total charge taken out
of the capacitor = (dI / dt) / 2. Q = C / dV = (dI / dt) / 2,
therefore;
The current share accuracy is achieved by Semtech’s proprietary Combi-Sense technology and no longer a function
of the current sense resistor values.
D. LMIN
927.8623 10
Load Release:
The worst-case for the transient load release to happen is
when one phase has just reached the maximum hysteresis,
(i.e., it has just turned off the high-side switch). At this point,
the second phase will be declining (approximately) through
the nominal voltage, (i.e., its low-side switch will be on).
20
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
L1
J?
Rcs1
13A
IRIPPLE
Rcu1
Rds_ON1
BG1
See STEP 6 for how to derive the ripple current.
36A
1.6A
ESR_eq
Rcu1_rt
R_LOAD
Rcs2
L2
J?
It0_1
Cout_eq
Rcu2
IHFM_FL
IRIPPLE
2
2
Rds_ON2
BG2
Figure 2 - Load Release Behavior of Dual
Phase Buck Converter
Load is stepping from 36A to 1.6A:
VTRANS_MIN
2
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Rcu2_rt
VTRANS_MIN
IHFM_FL
It0_2
RIMVP IHFM_FL
ILKGMAX
10 m V
0
It0_1
24.5000 10 A
It0_2
18.0000 10 A
0
COUT
330 10
RESR
6m Ω
6
F
We assume for the worst-case condition, at t = 0, one inductor is sitting at its maximum, while the other is sitting at
its nominal. After t = 0, both inductors discharge at a rate
0.082 V
The diagram below shows the response of the converter.
The control circuit quickly turns off TG and turns on both
bottom gates to discharge the inductors as quickly as
possible. The stored energy, once losses in the ESR and
FET RDS is subtracted, is transferred into the output capacitors.
equal to VFL / L. (without the consideration of the secondary
order effect, such as, Rds_on drop, current sense resistor
and miscellaneous trace drop).
What happens in terms of energy: The energy released
from both inductors during load step down will be dissipated through the following means:
TG1
BG1
IL1
IL1 ( t)
It0_1
IL2 ( t)
It0_2
OA
IL2
t
OA
VHFM_FL t
L1
VHFM_FL t
L2
0 50n s 10μ s
t= 0
ICAP ( t)
IL1 ( t)
IL2 ( t)
ILKGMAX
Figure 3 - Waveforms of Figure 2
© 2006 Semtech Corp.
21
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Since both inductors are discharging at the same time
and the same rate, there are two terms contributing to the
increase of the voltage on the output capacitors. First is
due to the ESR of the output capacitor. Second is due to
the added charge contributed by the inductor currents.
VESR ( t N)
G:
1
N
Method I: Current Sense Resistor Droop
2
In an SC452 design, setting the IMVP gain is through the
use of the droop amplifier. This IMVP gain is used to meet
the IMVP load line specification.
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
COUT N
VTOTAL ( t N)
VESR ( t N)
dVCAP ( t N)
The goal here is to use minimum amount of N x COUT to meet
the transient requirement, with some headroom to allow
for component tolerance.
0.15
0.1
V TRANS_MIN
V TOTAL t
V ESR t
dV CAP t
The IMVP load line is defined as the High Frequency Mode
at no-load voltage, minus the High Frequency Mode at
full-load voltage, divided by the maximum (High Frequency
Mode) load current. Since SC452 provides remote sensing for the core voltage, we no longer need to adjust for
the trace loss at full load (such adjustment was needed
for IMVP4 and 4+ core controllers, such as SC450 and
SC451).
V HFM_FL
6
0.05
6
STEP 2: Droop Calculation
SC452 offers 2 droop methods: Method I — Current Sense
Resistor Droop, Method II — DCR Resistive Droop.
RESR
ICAP ( t) t
dVCAP ( t N)
H:
I:
ICAP ( t)
Using Panasonic SPCAP, specified as 330µF at 2.0V with
6mΩ ESR, we see that 6 caps are sufficient for the ESR requirements, and also meet the capacitance requirement.
6
0
0.05
0
0.0000
2 10
10
0
6
4 10
6
6 10
t
6
8 10
6
1 10
10.0000 10
5
RCS1
0.5m Ω
RCS2
0.5m Ω
In order to provide the droop required by IMVP VI application, we will use the Block Diagram on Page 11 to determine
the component values. The reference designators that
are used in this worksheet are from the SC452 evaluation
board schematic.
6
Figure 4 - Simulated (Load Release)
Transient Response
© 2006 Semtech Corp.
1.195V
22
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
R cs2
L2
RCS1 RCS2
R c s = R c s1 || R cs 2
C ou t
+V cc_co re
L1
RCS
R cs1
VDP_CS
R 29
R 30
2 .5k
2.5k
RCS2
RCS1
L -R
RCS IHFM_FL
R 37
0Ω
R 35
2.5 k Ω
R30
2.5 k Ω
R29
G ain = 1 0 V /V
We can calculate the value of R35 by using the equation
as follows:
DRP
TBD
0Ω
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
R33
R35
C alculated a s
show n be lo w
R29
R30
VDP_CS
Figure 5 - Current Sense Resistive Droop Method
Since Rsense, R29, R30, R37 and R33 are pre-determined
to the values shown on the above diagram, we will need to
calculate the value of R35 to give us the correct droop.
VDP_R35
VDP_R35
3
26.2500 10 Ω
R35
Selected R35 = 26.5kΩ as the next closest value.
According to the IMVP-VI droop requirement:
R IMVP
m V
2.1
A
METHOD II: DCR Droop Method
L1
the required droop at full load is therefore,
V DP
92. 4000 10
3
L-R
DRN1
Rsense
R28
18.2kΩ
V
R31
36.0 kΩ
C 60
39nF
Calculated
from Step 10
Since the droop amplifier has a gain of 10V/V, the actual
voltage appears across R35 is only VDP_R35:
VDP_R35
10
DRN2
L-R
V
TH3
33kΩ
R32
47kΩ
R37
0Ω
Gain = 10 V/V
Rsense
R32
47kΩ
R35
TBD.
R36
18.2kΩ
R34
36.0kΩ
V
Calculated
from Step 10
VDP
GDP_AMP
C61
R32
47kΩ
R32
47kΩ
DRP
TH4
33kΩ
39nF
R33
0Ω
Droop Section of the SC452. R35 is the only variable
which is calculated as shown below
Since at full load, the voltage drop across the current sense
resistor is VDP_CS.
© 2006 Semtech Corp.
Cout
L2
0Ω
GDP_AMP
+Vcc_ core
0Ω
Figure 6 - Inductive DCR Droop Method
23
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Using Inductive DCR droop method will also require the
external compensation for the temperature coefficient
of the DCR resistance. We will cover the entire thermal
design in STEP 10. Here we are only interested in deriving the correct value of the droop resistor R35.
The RC filter time constant is set by C60 and parallel
combination of R31 and R28, TH3, R32 and R35.
In order to calculate R35 and C60, use the following
simplified diagram for Phase 1,
DC Voltage Between Two Terminals is:
VDCR = ( I FULL_LOAD / 2 ) x RDCR
To simplify the design process, here we will use the nominal DCR resistance value published in the inductor
vendor’s datasheet.
L1
Rsense
L-R
+Vcc_core
0:
Cout
RDCR
As shown in Figure 6 (Page 23), by moving the regulation
point before the output inductor (at the DRN1 and DRN2
node), droop becomes equal to the average voltage drop
across the output inductor’s DCR as well as any distributed resistance. The DCR droop is simply a RC low-pass
filter placed across the output inductor. This filter must
have the same time constant that the output inductor
and its DCR have. If the DCR value of the inductor is
very low, then care must be given to include any distributed/parasitic impedances on the board.
I FULL_LOAD / 2
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Req = Parallel
Combination of Resistors
shown in the box
In the SC452 evaluation design, this low pass filter is
represented by combination of R31, R28, TH3, C60, R32
and R35 (for phase 1) and R34, R36, TH4, C61, R32
and R35 (for phase 2). For phase 1, resistor combination R28, TH3 and R32, R35 are used to scale the magnitude of the droop. The output of this low pass filter is
summed together with that of the phase 2 and then fed
directly into the droop amplifier. The effects of this filter
on the frequency response is minimal and can be ignored.
From Step 1 we have the inductor and DCR value as:
9
L1
470.0000 u 10
L2
470.0000 u 10
9
H
R32
47k:
DRN1
Voltage
Between these
two terminals is
Veq
R28
18.2k:
Droop
Requirement =
0.21mV/A
R32
47k:
Droop
Requirement =
2.1mV/A
Hence, V R35 = (0.21 mV/A) x Full Load Current
Second Phase Connects
Here With Identical
Component Values
Considering One of the Two Phases of the SC452. The Second Phase Circuit will be exactly identical contributing the
remaining 50% of the full load current
Figure 7 - Inductive DCR Droop Method (Simplifed
Diagram)
According to the IMVP VI droop requirement,:
R IMVP 2.1˜
VDP
m˜V
A
3
92.4000 u 10
V
Since the droop amplifier has a gain of 10V/V, the
actual voltage appears across R35 is only VR35
H
VDP
GDP_AMP
The time constant of the output inductor is given by,
W
Gain = 10 V/V
DRP_AMP
R35
TBD
36k:
VR35 GDP_AMP
L1
IR35
C60
R31
DCR: = 1.2 • m • Ω
W
TH3
33k:
0
10.0000 u 10
DCR
6
391.6667 u 10
© 2006 Semtech Corp.
s
24
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Consider Phase 1
Consider Phase 2
Since
fulldroop
load, amplifi
the voltage
drop
across
DCR is
Sinceat
the
er has
a gain
ofthe
10V/V,
the
VDCR,
actual voltage appears across R35 is only VR35
Since the components and current are identical for phase
2 we get the same expression for voltage across R35,
VR35
VDCR
VDP
VR35_2
GDP_AMP
IR35_1
DCR
equal to IR35
IR35_2
Total voltage across R35 is given as:
IHFM_FL
2
IR35_2 R35
VR35_1
VR35_2
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
VR35
We
calculate
the value of R35 as follows:
R31can 16
k
Substituting equations A,B,C, D, E, F, G into H and simplifying we get the following final expression for R35:
R
16 calculate
•k•
We
the value of R35 as follows:
31:can
18.2 k
R28
TH3
33 k
R32
47 k
TH3
R35_DCR
TH3
R28 R35
2R32
TH3
R28
2R32
R35
So,
Veq
VDCR
Rcombination
Rcombination
Req
Req
VR35_1
R28
C60
Veq
2 R32
R28 R31
TH3
R28
2 R32 R31
R31
3
31.6633 10
1
R32
R32
1
R35_DCR
R31
1
1
R28
TH3
3
11.1125 10
R31
3
Now,
IR35
2 VDCR TH3
TH3
VR35
R35_DCR
Req
R28 2R32
C60
R35
Rcombination
35.2457 10
9
F
IR35_1 R35
© 2006 Semtech Corp.
25
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
We use the standard resistor value of 32K for R35 in the
case of DCR droop method. For C60 and C61, we use
standard capacitor value of 7nF.
66 μF
Cinput
1
L in
2
STEP 3: Calculate Input RMS Current (for input capacitor selection)
n
2
D
VHFM_FL
IHFM_FL VHFM_FL
POUT
43.6284 10 W
9
H
So effective is this that it takes less than 7nH to separate
the phases from each other. This is about 1.5/inch of 250
mil wide trace. If the phases are separated, the following
formula is more accurate:
POUT
IIN_DC
85%
PIN
VINMIN
0
5.1328 10 A
IIN_DC
0
The simplified expression is given as:
IRMS1
6.14 10
PIN
VINMIN
POUT
IRMS1
L in
C input
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
In order to calculate the worst case input RMS current, the
layout is important. If the input capacitors for both phases
are very close together, the following formula is accurate
and provides the lowest input capacitance.
2
FS
( D)
1
n
D IHFM_FL
2
n
2
12 n D
2
IRIPPLE
2
( D)
3
7.93 A
I HFM_FL
I RMS2
n
I RMS 2
9.2970 10 A
2
I IN_DC
n
D
n I IN_DC
2
1
D
0
Selection:
In this case, 6 x 22µF/25V POSCaps (1.5A ripple current
rating) are marginal. A seventh POScap is required if full
load must be sustained indefinitely at VINMIN. Five 10µF/
25V/1210 (2A ripple current rating) ceramic capacitors
will work down to VINMIN.
CI_RMS_POSCAP
1.5A
--> 8 X 22µF/25V POSCaps
(1.5A ripple current rating) (4 per phase).
CI RMS MLCC
2A
--> 6 X 10µF/25V MLCC
(2A ripple current rating) (3 per phase).
If the input capacitors and high side FETs are separated by
a very short distance, the input capacitors and the board
inductance will form an LC filter. Surprisingly, little inductance is required for the pole to be lower than the switching
frequency. In the case of using 6 x 22µF POSCaps, three
near each phase:
© 2006 Semtech Corp.
26
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
STEP 4: Combi-Sense Component Values
Calculation
R IND
Vin
dNOM
Rds_on
0.0012
VHFM_NL
RIMVP IHFM_FL
VINNOM
Lout
Vout
PHASE
DCR
Ccombi
RSENSE
dNOM RHS_FET
RSENSE
3.7658 10
1 dNOM RLS_FET
RIND
VPN
Cout
Rcombi
CS1P
CS1N
Figure 8 - The Equivalent Circuit of
Combi-Sense During On-Time
R SENSE
Lout
Vout
DCR
Ccombi
VPN
Rcombi
Rds_on
The equivalent combi-sense resistance is then given by the
following
equations:
The
equivalent
Comb-Sense resistance is then given by
2
0.004
1.2
2
3
R7
7.5
R4
100 10
10
--->2 X IRF7832 per phase @ 75°C,
3
Note: We assume R7 and R4 to be 7.5k and 100k respectively.
One can vary R4 to have desired gain and the signal for combisense. If thermal compensation is required please refer Step
10.
---> 2 X IRF7821 per phase @
75°C, per datasheet effective Rds-on at 75°C is 1.25 x
8m
R LS _FET
s
In Figures 8 and 9 RCOMBI is the parallel combination of
R4 and R7. R4 is the gain setting resistor and R7 with R4
sets RCOMBI.
R COMBI
the following equations:
1.25
10
CS1N
Figure 9 - The Equivalent Circuit of
Combi-Sense During Off-Time
0.008
1.2481
Cout
CS1P
R HS_FE T
4
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
L1
3
RCOMBI
CCOMBI
per datasheet effective Rds-on at 75°C is 1.2 x 4m .
CCOMBI
1
1
1
R7
R4
3
6.9767 10
L1
RSENSE R7
16.6408 10
9
F
From the above calculation, we determined the values for
the Combi-Sense components: R7, R4, R23, R20, C8 and
C17 ----> where R7 = R23 = 7.5k , 11.5K R4 = R20 =
100K C8 = C17 = 12nF.
© 2006 Semtech Corp.
27
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Using the Taylor Series we can expand the right hand
side.
STEP 5: Hysteresis (Frequency) Setting
The next step is to calculate the desired hysteresis voltage
level for a fixed switching frequency. Since SC452 is a
hysteretic converter with the benefits of Combi-Sense
technology, the ripple for the hysteretic switching control is
provided by the Combi-Sense current feedback.
If we consider only the first term of the Taylor series the
equation is greatly simplified with about a 20% error in
the final value. If first 3 terms are considered the equation
will give virtually zero error,
The ripple inputs are fed to a summer via a multiplexer
which is synchronized to the active phase with the select
ouput. The hysteresis signal is added at the summer. The
hystersisis voltage is set directly by the resistor divider from
the 2V REF output.
Vout
Vcombi ( t)
Rcombi Ccombi
dVcombi ( t)
dt
We can simplify the above equation as follows:
1
Rcombi Ccombi
dt
Vcombi ( Ton)
Rcombi Ccombi
Vin
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
From the circuit in Figure 8 on Page 27, we can write the
following equation for Combi-Sense operation during on
time (high side MOSFETs are on),
Vin
Ton
Vout
( Vin
Vout)
Vcombi ( t( t) )
dVcombi
The feedback voltage essentially contains two components,
the voltage across the output capacitor and the voltage
across the ESR of the output capacitor,
Vfb( t)
1
i esr
Cout
Hence, the solution for the above equation is:
Rcombi Ccombi
ln [ ( Vin
Vout)
Vcombi ( t) ]
Vini
In the above equation Vini is the initial value of voltage
across the capacitor. Let us assume it to be equal to
Vhys_low voltage. This is a fair assumption because of the
architecture of the hysteretic comparator. We can rewrite
the above equation as follows:
Ton
Rcombi Ccombi
© 2006 Semtech Corp.
ln [ ( Vin
Vout)
Vcombi ( t) ]
Vhys_low
Rcombi Ccombi
For more accuracy we have to consider more than the
first term of the Taylor series for the hysteretic frequency
prediction.
Since we are interested in the end point for this waveform
we simplify the equation with t = tON.
Ton
Ton
The Feedback
1
Vin
Vcombi ( Ton)
Vhys_low
Vout
i dt
In the above equation, i is the output inductor current
ripple defined by the equation below for on-time,
i( t)
Vin
Vout
2Lout
t
Again we are interested in the end point where t = tON, so
the above equation simplifies to,
Vhys_low
Vfb( Ton)
28
Vin
Vout
2 Lout
Ton esr
1
Ton
Cout
2
2
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
The Droop
Example Showing Variation with VHYS_LOW Voltage:
The droop circuit is the simple inductor sense feedback for
the SC452 with a gain of 0.00021.
Vin
Vdrp( Ton)
Vout
2 Lout
Ton 0.00021
LOUT
0.47 μ H
C OUT
330.0000 10
2 Vcombi ( Ton)
10 Vdrp( Ton)
Vfb( Ton)
3
2
To n
To n
2 Vhys_low
2
0.0252
6 e sr
Rco mb i Cco mb i
2 L ou t
L ou t
0
0.0126 Ω
R calc
12
Substituting 1, 2 and 3 in the above equation we get the
following final result for tON,
L ou t Co u t
MAX
Ton V HYS_LO
L OUT
Ton V HYS _LO
399.7341 10
3
4 10
3.5 10
3 10
Where,
(Hz)
2.5 10
Fs V HYS _LO
2 10
D
1.5 10
Ton
1 10
Vout
6 ESR
d NOM
Fs V HYS_LO
Since the converter is operating in continuous conduction
mode we can write the expression for Frequency in terms
of tON only. Finding the expresssion for tOFF is a similar procedure as we have for tON but for CCM mode
we need not care.
D
s
RCALC is a constant obtained from equation 4 above. It
enables better presentation of the solution of equation 4
as follows:
2L OUT
Fs
6
116.0988 10
COMBI
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Final Expresssion
F
RCOMBI CCOMBI
COMBI
Equations 1, 2 and 3 can be used to obtain the final expression for the on-time for SC452 architechture.
6
Iout Rdrop
5 10
Vin
46.8798 10
COMBI R calc
COMBI R calc
2L OUT
L OUT
COMBI
2
COMBI
2
4
3
L OUT C OUT 6
2V HYS _LO
3
L OUT C OUT 6
5
5
5
5
5
5
5
4
3
0
0.005
0.005
0.01
0.015
0.02
0.025
0.03
V HYS _LO
(V )
0.035
0.04
Figure 10 - Hysteresis Setting vs.
Switching Frequency
© 2006 Semtech Corp.
29
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
STEP 6: Current Limit Calculation
In current limit, the voltage hysteretic converter is over-ridden by the current limit hysteretic comparator, and the TG
pulse is terminated when the output of the current sense
amplifier reaches the CL_hi threshold and BG terminated
at the CL_lo threshold. These thresholds are set from the
CLSET resistor divider:
Setting the threshold for current limit is a relatively straightforward process. To do this we must calculate the peak
current based on the maximum DC value plus the worstcase ripple current. Because the SC452 has a current-limit
comparator for each phase, the following calculations apply
for a single phase.
Worst-case ripple occurs at the highest input voltage. Since
ripple is also inversely proportional to inductance, it is recommended that the minimum inductance value be used
based on the manufacturer’s specified tolerance:
64. 3750 10
LMIN
3
L T OL
V INMAX
I RIPPLE_MAX
I RIPP LE _MA X
20%
IPEAK
IPEAK
1
2
V HFM_NL
d MIN
ICC_MAX 1
GaCS_CL
VCLSET
VCLSET
IHFM_FL
I_SHR TOL
IRIPPLE_MAX
© 2006 Semtech Corp.
ICLIM
3
Ω
2
V
GaCLSET
V
1 V
3 V
RSENSE ICLIM GaCS_CL
GaCLSET
3
635.4477 10
V
We calculate R14 and R13 based on the VCLSET voltage,
2
25.5667A
1.10 IPEAK
3.7658 10
Per phase current limit is set by ICLIM, Rsense (Combi-Sense),
current sense amplifier gain in current limit mode and CLSET gain, therefore the dual phase current limit is set by
the following equation:
13. 3333A
5% ICC_MAX
28.1233A
RSENSE
It is recommended that the current limit be set at 110%
of the peak value to allow for inductor current overshoot
during load transients:
ICLIM
0.20 V( clset )
ICLIM
To calculate the maximum DC value of current we must
make an adjustment for the dynamic current-sharing tolerance. We then add the maximum DC current and the
maximum ripple value to obtain peak current.
I_SHR TOL
CL_lo
Current limit pulses continue until 32 pulses after the voltage droops to the PWRGD low threshold; then the controller
latches off.
L MIN F S
0.3760 μH
0.33 V( clset )
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
d MIN
CL_hi
28.1233A
3
R14
100 10 Ω
R13
46568.2149Ω
R13
VCLSET R14
2V
VCLSET
We use 46.5K for R13 and 100K for R14.
30
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
1. Start-Up:
STEP 7: OVP
12 μ A
iSS_STARTUP
No calculations are necessary for Over Voltage Protection.
The OVP circuit of SC452 monitors the processor core
Vcc_core voltage for an over-voltage condition. If the FB
voltage is 200mV greater than the DAC_Droop (i.e., out of
the powergood window), the SC452 will latch off and hold
the low-side driver on permanently. Either the Power or EN
must be recycled to clear the latch. The latch is disabled
during soft-start and VID/DeeperSleep transitions. For
safety, the latch is enabled if the FB voltage exceeds 1.8V
even during VID/DeeperSleep transition.
dV
iSS_STARTUP
VHFM_NL
dt
iSS_STARTUP dt
CSS
CSS
dV
CSS
dV
dt
3m s
27.9612 10
9
F
120 μ A
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
iSS_GVIII
2. During GV-III Transition:
STEP 8: Thermal Protection
iSS_GVIII
SC452 will be disabled and latched off when the internal
junction temperature reaches approximately 160°C. Either
the Power or EN must be recycled to clear this fault.
CSS
dV
dt
Slew_Rate GVIII
STEP 9: Soft-Start/DAC Slew Control
dV
dt
The soft-start cap C12 in the SC452 eval board design
serves two purposes: 1) define the soft-start ramp 2)
define the DAC slew rate during DeeperSleep and VID
transition. During VID/DeeperSleep transitions, the SS
current is normally 120µA. During start-up, the SS current
is normally 12µA.
3.2
mV
μ s
Slew_Rate GVIII
3. During fast C4 exit:
C S S_GVIII
Resistance of the node is set to provide a fixed gain of
10; as a result, only 0.21mW of resistance is required to
produce the Intel-defined load line of 2.1mV/A.
C S S_GVIII
iSS_C4E
According to Intel’s IMVP-VI Timing Requirements, the
maximum t_SFT_START_CC is specified at 3ms(max). And
the slew rate for CPU_UP due to,
dV
dt
1) GV-III VID change is 3.2mV/μsec
2) Deeper Sleep exit is specified at 10mV/μsec
Slew_Rate GVIII
C S S_C 4
9
37. 5000 10
120 μ A
i S S_C4E
F
iSS_C4E
Slew_Rate C4E
C S S_C4
We will be doing three soft-start exercises based on the
above three conditions:
1
i S S_GVIII
CSS
Slew_Rate C4E
dV
dt
10
mV
μ s
1
Slew_Rate C4E
12. 0000 10
9
F
Taking into consideration of component tolerance, we use
Css = 10nF to meet all three requirements.
STEP 10: DCR Droop Thermal Compensation
Note: (contact your local Semtech Representative for details)
© 2006 Semtech Corp.
31
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Applications Information (Cont.)
Manufacturer
Series or Part Number
High Side MOSFET, HSFET
International Rectifier
Fairchild Semiconductor
Siliconix
Infenion Technologies
IRF7821, IRF6602,
SSC3002S,
Si4860DY,Si4410BDY
Low Side MOSFET, LSFET
International Rectifier
Fairchild Semiconductor
Siliconix
Infenion Technologies
Depends on Application
Boost Capacitor, Cbst
Various
X5R or better
Various
Schottky, 200mA or greater
Panasonic / NEC TOKIN
0.5μH
Decoupling Capacitors
Various
X5R or better
Current Sense Resistor
IRC, Panasonic
ERJ-M1WTJ
Output Bulk Capacitors
Panasonic / NEC-TOKIN SPCAP
330μF, max ESR 6mΩ
Boost Diode, Dbst
Output Inductor, L
Company
International Rectifier
Panasonic
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Component
Contact
Web: http://www.irf.com/product-info/
Phone: (310) 726-8000
Web: http://www.panasonic.com/pic/ecg/
Phone: (201) 348-7522
IRC
Web: http://www.irctt.com
Phone: (888) 472-4376
Kernet
Web: http://www.kernet.com/
Phone: (864) 963-6300
Sanyo
Web: http://www.sanyovideo.com/
Phone: (619) 661-6835
TDK
Web: http://www.component.tdk.com/components/components.html
Phone: (847) 390-4373
Vishay/Dale
Web: http://www.vishay.com/brands/dale
Phone: (402) 564-3131
Vishay/Siliconix
Web: http://www.vishay.com/brands/siliconix
Phone: (800) 554-5565
© 2006 Semtech Corp.
32
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Typical Characteristics
High Frequency Line and Load Regulation
VOUT = 1.2875V, IOUT = 0A to 36A (Spec bounds @ 25C)
Low Frequency Line and Load Regulation
VOUT = 0.8375V, IOUT = 0A to 9.5A (Spec bounds @ 25C)
0.855
1.320
0.850
1.300
0.845
0.840
1.280
V
OUT
(V)
1.240
20Vin ( 40C)
10Vin (-40C)
20Vin (25C)
10Vin (25C)
20Vin (125C)
10Vin (125C)
Spec Nom.
Spec Min.
Spec Max.
0.835
20Vin ( 40C)
10Vin (-40C)
20Vin (25C)
10Vin (25C)
20Vin (125C)
10Vin (125C)
Spec Nom.
Spec Min.
Spec Max.
1.260
0.830
V
OUT
(V)
0.825
0.820
0.815
1.220
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
0.810
1.200
0.805
0.800
1.180
0.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
I
OUT
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
36.0
4.5
5.0
I
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
(A)
OUT
(A)
Deeper Sleep Line and Load Regulation
VOUT = 0.7625V, IOUT = 0A to 3.5A (Spec bounds @ 25C)
SC452 High Frequency Mode Output Power Efficiency
VOUT=1.2875V, IOUT=2A to 36A
95.0%
0.780
90.0%
0.775
85.0%
0.770
80.0%
20V Input ( 40C)
10V Input (-40C)
20V Input (25C)
10V Input (25C)
20V Input (125C)
10V Input (125C)
Spec Nom.
Spec Min.
Spec Max.
0.765
VOUT (V) 0.760
0.755
0.750
20Vin ( 40C)
10Vin (-40C)
20Vin (25C)
10Vin (25C)
20Vin (125C)
10Vin (125C)
75.0%
EFF (%)
70.0%
65.0%
60.0%
0.745
55.0%
0.740
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
I
OUT
2.00
2.25
2.50
2.75
3.00
3.25
50.0%
0.0
3.50
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
SC452 Low Frequency Mode Output Power Efficiency
VOUT=0.8375V, IOUT=1A to 9.5A
18.0
I
(A)
OUT
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
(A)
SC452 Deeper Sleep (C4) Mode Output Power Efficiency
VOUT=0.7625V, IOUT=0.25A to 3.5A
95.0%
100.0%
90.0%
95.0%
85.0%
90.0%
80.0%
85.0%
20Vin ( 40C)
10Vin (-40C)
20Vin (25C)
10Vin (25C)
20Vin (125C)
10Vin (125C)
75.0%
EFF (%)
70.0%
80.0%
EFF (%)
20Vin ( 40C)
10Vin (-40C)
20Vin (25C)
10Vin (25C)
20Vin (125C)
10Vin (125C)
75.0%
70.0%
65.0%
65.0%
60.0%
60.0%
55.0%
55.0%
50.0%
0.00
50.0%
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
I
OUT
© 2006 Semtech Corp.
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
0.25
0.50
0.75
1.00
1.25
1.50
1.75
I
(A)
OUT
33
2.00
2.25
2.50
2.75
3.00
3.25
3.50
(A)
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Typical Characteristics (Cont.)
Phase 1 vs. Phase 2 Current Share Balance
(specified at IOUT > 50% load)
50.0%
45.0%
40.0%
35.0%
20Vin -40C
10Vin -40C
20Vin 25C
10Vin 25C
20Vin 125C
10Vin 125C
5% Limit
30.0%
EFF (%)
25.0%
20.0%
15.0%
5.0%
0.0%
0.0
2.0
4.0
6.0
8.0
10.0
12.0
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
10.0%
14.0
16.0
18.0
20.0
22.0
24.0
26.0
28.0
30.0
32.0
34.0
36.0
IOUT (A)
© 2006 Semtech Corp.
34
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
Typical Characteristics (Cont.)
© 2006 Semtech Corp.
35
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Outline Drawing - MLP-44
D
B
PIN 1
INDICATOR
(LASER MARK)
DIMENSIONS
MILLIMETERS
INCHES
DIM
MIN NOM MAX MIN NOM MAX
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
tia
A2
A
1.00
0.80
0.00
0.05
- (0.20) 0.30
0.25
0.18
6.90 7.00 7.10
5.00 5.15 5.25
6.90 7.00 7.10
5.00 5.15 5.25
0.50 BSC
0.45 0.55 0.65
44
0.08
0.10
O RE
R C
N O
EW M
M
D EN
ES D
IG ED
N
E
- .040
.031
.000
.002
- (.008) .007 .010 .012
.271 .275 .279
.197 .203 .207
.271 .275 .279
.197 .203 .207
.020 BSC
.017 .021 .025
44
.003
.004
l
A
A1
en
SEATING
PLANE
aaa C
C
D1
id
LxN
nf
E1
E/2
N
C
O
T
F o
2
1
N
NOTES:
bxN
bbb
e
C A B
D/2
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
© 2006 Semtech Corp.
36
United States Patent No. 6,441,597
NOT RECOMMENDED FOR NEW DESIGN
SC452
POWER MANAGEMENT
Land Pattern - MLP-44
H
DIMENSIONS
K
Z
G
INCHES
(.268)
.228
.207
.207
.021
.011
.039
.307
N
O
FO T R
R EC
N O
EW M
M
D EN
ES D
IG ED
N
(C)
DIM
C
G
H
K
P
X
Y
Z
Y
MILLIMETERS
(6.80)
5.80
5.25
5.25
0.50
0.30
1.00
7.80
X
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Taiwan Branch
Korea Branch
Shanghai Office
Tel: 886-2-2748-3380
Fax: 886-2-2748-3390
Semtech Switzerland GmbH
Japan Branch
Tel: 81-3-6408-0950
Fax: 81-3-6408-0951
Tel: 82-2-527-4377
Fax: 82-2-527-4376
Semtech Limited (U.K.)
Tel: 44-1794-527-600
Fax: 44-1794-527-601
Tel: 86-21-6391-0830
Fax: 86-21-6391-0831
Semtech France SARL
Tel: 33-(0)169-28-22-00
Fax: 33-(0)169-28-12-98
Semtech Germany GmbH
Tel: 49-(0)8161-140-123
Fax: 49-(0)8161-140-124
Semtech International AG is a wholly-owned subsidiary of
Semtech Corporation, which has its headquarters in the
U.S.A.
www.semtech.com
© 2006 Semtech Corp.
37
United States Patent No. 6,441,597