Migrating from the ACS8510 to the ACS8520 A primary objective in the design of the ACS8520 was to provide a simple software migration path from the ACS8510. To this aim as far as possible, the registers of the ACS8510 have been maintained. To a large extent the ACS8520 register set is a super-set of the ACS8510. However, this has not been possible in the case of every register. Where the new (ACS8520) functionality offers more options than the previous (ACS8510) functionality, and there are not enough bits assigned within the register map of the ACS8510, a new register has to be assigned. This is mainly true in the case of the output frequencies and their selection. The ACS8510 registers that have equivalent functionality in the ACS8520 but are at different locations are listed in the table below: ACS8510 location (Hex [bits]) 03[5] 04[5:3] 04[2:0] 35[5] 38[0] 38[1] 38[2] 38[3] 38[4] ACS8510 original function ACS8520 ACS8520 replacement function location (Hex [bits]) 32.768MHz to APLL 65[2:0] New options include automatic reThis was an option to de-jitter the configuration of the APLL to multiple E1 rates using the APLL improve performance Also see datasheet for other options for generating multiple E1/DS1 rates. configuration of the phase error limit 73[2:0] Equivalent functionality, but see required to cause loss of lock datasheet for many more phase indictaion detector options for high performance and jitter tolerance. Phase detector gain control 6B[6:4], With new options for analog 6D[6:4], feedback etc, more controls are 6D[2:0] offered to control phase detector gain in different modes. T4 squelch control 64[6], T4 can now be automatically 64[2:0] squelched on input reference failure. Also T4 squelched is offered as one of the new operating frequencies of the T4 DPLL TO5 output enable- fixed frequency 62[3:0] TO5 now has options of many 77.76 MHz output. difference frequencies. Disable is included in the frequency selection register TO4 output enable- fixed frequency 61[7:4] TO4 now has options of many 38.88 MHz output. difference frequencies. Disable is included in the frequency selection register TO3 output enable- fixed frequency 61[3:0] TO3 now has options of many 19.44 MHz output. difference frequencies. Disable is included in the frequency selection register TO2 output enable- one of 4 60[7:4] TO2 now has options of many frequencies selected in reg 39[3:2]. difference frequencies. Disable is included in the frequency selection register TO1 output enable- one of 4 60[3:0] TO1 now has options of many frequencies selected in reg 39[1:0]. difference frequencies. Disable is included in the frequency selection ACS8510 location (Hex [bits]) 38[7] 39[1:0] 39[3:2] 3A[5:4] 3A[7:6] 3B[2:0] 3B[6:4] ACS8510 original function ACS8520 ACS8520 replacement function location (Hex [bits]) register TO6 311.04 MHz output select 62[7:4] TO6 now has options of many difference frequencies. 311.04 MHz is included in the frequency selection register TO1 frequency selection (1 of 4) 60[3:0] TO1 now has options of many more difference frequencies TO2 frequency selection (1 of 4) 60[7:4] TO2 now has options of many more difference frequencies TO6 frequency selection (1 of 4) 62[7:4] TO6 now has options of many more difference frequencies TO7 frequency selection (1 of 4) 63[3:0] TO7 now has options of many more difference frequencies T0DPLL locked bandwidth (1 of 4) 67[3:0] T0DPLL now has 10 bandwidth options T0DPLL acquisition bandwidth (1 of 67[3:0] T0DPLL now has 10 bandwidth 4) options ACS8520 14-Jun-02 Parameter name Ad Def chip_id (read only- decimal value 8520) 00 48 Chip id (7:0) 01 21 Chip id (15:8) chip_revision (read only- value 0) 02 00 test_register1 (read/write) 03 00 Register map migration from ACS8510 Data Bits 7(msb) 6 5 Chip revision (7:0) Disable 180o See reg 65 lock 4 3 2 1 0 (lsb) Enable alog.resync Fast seconds msmt comp/ invert divinp pll lock Hold sts bits test_register2 (read/write) 04 22 phase_alarm (read only) force sync accum sts_interrupts (read/write) writing ‘1s’ will reset appropriate bits 05 FF status I8 status I7 status I6 status I5 status I4 status I3 status I2 status I1 06 FF Main ref fail 08 00 Oper. mode ExtSync phase alarm ExtSync phase alarm status I14 Phasemon Alarm T0 freq limit soft alarm status I13 T4 inputs failed T4 freq limit soft alarm status I12 Ami2 Viol status I11 Ami2 LOS status I10 Ami1 Viol status I9 Ami1 LOS See register 6A-6D and Register 73 T4 Locked sts_operating_mode (read only) 09 01 sts_priority_table (read only) 0A 00 0B sts_current_DPLL_frequency (read only) 19 bit signed integer 0C 0D 00 Current DPLL frequency (15:8) 07 00 0E 00 0F 00 10 11 12 13 14 15 16 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 30 66 66 66 66 66 66 66 32 54 76 98 BA DC FE 00 00 00 00 03 03 03 03 03 03 02 01 01 01 FF sts_sources_valid (read only) sts_reference_sources (read/write) status bit 0 = phase lock alarm status bit 1 = no activity alarm status bit 2 = out-of-band alarm 1 (hard) status bit 3 = out-of-band alarm 2 (soft) cnfg_ref_selection_priority (read/write) Lower no = higher priority 0 = do not use 1-15 = priority all priorities are relative Can be set independently for T0 and T4 cnfg_ref_source_frequency (read/write) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 = 8 kHz = 1544/2048 kHz2 = 6.48 MHz = 19.44 MHz = 25.92 MHz = 38.88 MHz = 51.84 MHz = 77.76 MHz = 155.52 MHz = 2 kHz = 4 kHz cnfg_sts_remote_sources_valid (read/write) 00 3rd highest priority valid source 2nd highest priority valid source 00 Current DPLL frequency (7:0) 31 3F 32 00 force_select_reference_source (read/write) 33 0F cnfg_mode (read/write) 34 C4 cnfg_T4_path (read/write) 35 40 cnfg_differential_inputs (read/write) 36 02 cnfg_uPsel_pins1 (read only) 37 38 Current DPLL frequency (18:16) I8 I7 I6 I5 I4 I3 I2 I1 I14 I13 I12 I11 I10 I9 status <I2> status <I4> status <I6> status <I8> status <I10> status <I12> status <I14> programmed_priority <I2> programmed_priority <I4> programmed_priority <I6> programmed_priority <I8> programmed_priority <I10> programmed_priority <I12> programmed_priority <I14> Set to 0 Set to 0 bucket_id<I1>(1:0) Set to 0 Set to 0 bucket_id<I2>(1:0) divn lock8k bucket_id<I3>(1:0) divn lock8k bucket_id<I4>(1:0) divn lock8k bucket_id<I5>(1:0) divn lock8k bucket_id<I6>(1:0) divn lock8k bucket_id<I7>(1:0) divn lock8k bucket_id<I8>(1:0) divn lock8k bucket_id<I9>(1:0) divn lock8k bucket_id<I10>(1:0) divn lock8k bucket_id<I11>(1:0) divn lock8k bucket_id<I12>(1:0) divn lock8k bucket_id<I13>(1:0) divn lock8k bucket_id<I14>(1:0) Remote status, channels <8:1> Forced operating mode force_select_reference_source Auto Ext Sync En Lock to T0 DPLL Ph Alarm timeout en T4 digital feedback Clock edge Manual Holdover en See reg 64 TO8,9 Outputs from T0(1)/T4(0) Ext Sync Sync en Sonet/ SDH i/p Master/ Slave Reversion mode Force T1 input source selection I6PECL 1=Sonet 0=SDH for Dig2 7F see reg 62 39 08 Digital2(1:0) (Sonet/SDH) 00=1.544/2.048MHz 01=3.088/4.096MHz 10=6.176/8.192MHz 11=12.352/16.384MHz 3A C6 3B 75 1=Sonet 0=SDH for Dig1 see registers 60-62 Digital1(1:0) (Sonet/SDH) 00=1.544/2.048MHz 01=3.088/4.096MHz 10=6.176/8.192MHz 11=12.352/16.384MHz see register 60 see registers 62 &63 T07 LVDS enable see register 69 Limit (freeze) integral path when DPLL limits * = default cnfg_bandwidth (read/write) cnfg_holdover_frequency (read/write) 19 bit signed integer <I3> (3:0) <I4> (3:0) <I5> (3:0) <I6> (3:0) <I7> (3:0) <I8> (3:0) <I9> (3:0) <I10> (3:0) <I11> (3:0) <I12> (3:0) <I13> (3:0) <I14> (3:0) Remote status, channels <14:9> cnfg_differential_outputs (read/write) cnfg_nominal_frequency (read/write) 16 bit unsigned integer status <I1> status <I3> status <I5> status <I7> status <I9> status <I11> status <I13> programmed_priority <I1> programmed_priority <I3> programmed_priority <I5> programmed_priority <I7> programmed_priority <I9> programmed_priority <I11> programmed_priority <I13> Set to 0000 Set to 0000 reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency reference_source_frequency I5PECL Micro-Processor type cnfg_digital_frequencies (read/write) * = default Operating mode (2:0) Currently selected reference source cnfg_operating_mode (read/write) cnfg_dig_outputs_sonsdh (read/write) T4 Locked Highest priority valid source Auto b/w switch Acq/lock 3C 99 Nominal Frequency (7:0) 3D 99 Nominal Frequency (15:8) 3E 00 Holdover Frequency (7:0) 3F 00 cnfg_holdover_modes (read/write) T07 PECL enable T06 LVDS enable T06 PECL enable see register 67 Holdover Frequency (15:8) Auto holdover averaging Fast/Slow averaging Mini-holdover selection Read back 01-instant averaged value 00-full 10-fast aver. 11-slow aver. Holdover Frequency (18:16) 40 88 cnfg_DPLL_freq_limit (read/write) 10 bit unsigned integer 41 76 42 00 cnfg_interrupt_mask (read/write) setting to 0 will mask the interrupt 43 FF status 8 status 7 Status 6 status 5 status 4 Status 3 status 2 status1 44 FF Main ref failed Status 14 status 13 status 12 Status 11 status 10 status 9 45 7F Oper. mode ExtSync phase alarm Phasmon T4 ref failed Ami2 Viol Ami2 LOS Ami1 Viol DPLL Frequency offset limit (7:0) DPLL Offset limit (9:8) T4 Status Ami1 LOS Parameter name Ad Def Data Bits 7(msb) cnfg_freq_divn (read/write) 14 bit integer to pre-scale selected inputs 46 FF 47 3F cnfg_monitors (read/write) 48 05 6 5 4 3 2 1 0 (lsb) Divide-input-by-n ratio (7:0) Monitor clock from Xtal Flag ref loss on TDO Ultra-fast switching Divide-input-by-n ratio (13:8) External prot. Freeze phase Switch en. buildout Phase buildout en Soft Frequency HardFrequency monitors enable monitors enable cnfg_freq_mon_threshold (read/write) 49 23 Soft Frequency alarm threshold for standby sources (3:0) Hard frequency alarm threshold for standby sources (3:0) cnfg_freq_threshold_current_src (r/w) 4A 23 Hard frequency alarm threshold for selected source (3:0) cnfg_freqmeas (read/write) 4B 00 Soft Frequency alarm threshold for selected source (3:0) T4/T0B dual reg. select. sts_freq_meas (read only) 4C 00 cnfg_freq_soft_limit (read/write) 4D 8E cnfg_upper_threshold0(read/write) 50 06 Leaky bucket configuration 0: Activity alarm set threshold cnfg_lower_threshold0(read/write) 51 04 Leaky bucket configuration 0: Activity alarm reset threshold (7:0) cnfg_bucket_size0(read/write) 52 08 Leaky bucket configuration 0: Activity alarm bucket size (7:0) cnfg_decay_rate0(read/write) 53 01 cnfg_upper_threshold1(read/write) 54 06 Leaky bucket configuration 1: Activity alarm set threshold (7:0) cnfg_lower_threshold1(read/write) 55 04 Leaky bucket configuration 1: Activity alarm reset threshold (7:0) cnfg_bucket_size1(read/write) 56 08 Leaky bucket configuration 1: Activity alarm bucket size (7:0) cnfg_decay_rate1(read/write) 57 01 cnfg_upper_threshold2(read/write) 58 06 Leaky bucket configuration 2: Activity alarm set threshold (7:0) Frequency measurement Channel select (3:0) Frequency measurement result (7:0) En. Phaseloss on DPLL limit DPLL Frequency Soft Alarm Limit (6:0) Resolution = 0.628 ppm (7:0) Cfg 0: decay_rate (1:0) Cfg 1: decay_rate (1:0) cnfg_lower_threshold2(read/write) 59 04 Leaky bucket configuration 2: Activity alarm reset threshold (7:0) cnfg_bucket_size2(read/write) 5A 08 Leaky bucket configuration 2: Activity alarm bucket size (7:0) cnfg_decay_rate2(read/write) 5B 01 cnfg_upper_threshold3(read/write) 5C 06 Leaky bucket configuration 3: Activity alarm set threshold (7:0) cnfg_lower_threshold3(read/write) 5D 04 Leaky bucket configuration 3: Activity alarm reset threshold (7:0) cnfg_bucket_size3(read/write) 5E 08 Leaky bucket configuration 3: Activity alarm bucket size (7:0) cnfg_decay_rate3(read/write) 5F 01 60 85 Output_frequency <T02> 61 86 Output_frequency (1011 = T4_155M) <T04> 62 8A Output_frequency (0011 = T0_155M <T06> 0101 = T0_311M) 63 F6 cnfg_output_frequencies (read/write) 0000 disabled 0001 2kHz 0010 8kHz 0011 digital2 0100 digital1 0101 T0_6M 0110 T0_19M 0111 T0_25M 1000 T0_38M 1001 T0_51M 1010 T0_77M 1011 T4_5M 1100 T4_6M 1101 T4_19M 1110 T4_38M 1111 T4_77M cnfg_T4_DPLL_frequency AMI duty cycle 0 = 50/50 1 = 5/8 64 11 65 01 66 00 67 0B cnfg_T0_DPLL_acq_bandwidth (r/w) 69 0F cnfg_T4_DPLL_damping (read/write) 6A 10 cnfg_T0_DPLL_frequency (all digital feedback except “001”) Cfg 2: decay_rate (1:0) Cfg 3: decay_rate (1:0) MfrSync enable FrSync enable T09 enable T08 enable Output_frequency <T01> Output_frequency <T03> Output_frequency (1011 = T4_155M) <T05> Output_frequency (0100 = T0_155M) <T07> T4 DPLL frequency 000- Squelched 001-OC-N 011- 16E1 100- 12T1 110- E3 111- T3 Sonet/SDH Auto Disable T4 AMI Duty cycle T4 selection o/p (pre T0/T4 mux) T4 for measuring T4 APLL for T0 T0 phase E1/T1 T0 DPLL frequency 000- OC-N 001- OC-N 011- 16E1 100- 12T1 110- R.F.U. 111- R.F.U. T0 Freq to T4 APLL 00 = 12E1 01 = 16E1 10 = 12T1 11 = 16T1 cnfg_T4_DPLL_bandwidth (read/write) 010- 12E1 101- 16T1 010- 12E1 101- 16T1 T4 bandwidth (1:0) 00 = 18Hz 01 = 35Hz 10 = 70Hz cnfg_T0_DPLL_locked_bandwidth (read/write) T0 Locked bandwidth (3:0) 1000 = 0.1 Hz 1001 = 0.3 Hz 1010 = 1011 = 1.2 Hz 1100 = 2.5 Hz 1101 = 1110 = 8 Hz 1111 = 18 Hz 0000 = 0001 = 70 Hz 0.6 Hz 4 Hz 35 Hz T0 Acquisition bandwidth (3:0) T4 phase detector gain Analog 8K (2:0) T4 Damping factor (2:0) cnfg_T0_DPLL_damping (read/write) T0 Damping factor (2:0) 001 = 1.2 010 = 2.5 100 = 10 101 = 20 T0 phase detector gain Analog 8K (2:0) 011 = 5 6B 10 cnfg_T4_DPLL_pd_gain (read/write) 6C C2 Enable T4 phase detector gain Analog (2:0) T4 phase detector gain (2:0) cnfg_T0_DPLL_pd_gain (read/write) 6D C2 Enable T0 phase detector gain Analog (2:0) T0 phase detector gain (2:0) cnfg_phase_offset (read/write) 70 00 Phase Offset (7:0) 71 00 Phase Offset (15:8) cnfg PBO_phase_offset_ (read/write) 72 00 Phase Buildout Phase Offset (5:0) cnfg_phase_loss_coarse_limit (read/write) 74 cnfg_input_noise_window 76 Fine limit no_activity for Phaseloss phase loss enable (1) Coarse limit Wide range Phaseloss 85 enable enable (2) 06 noise window en. sts_current_phase (read only) 16 bit signed integer 77 00 Current Phase (7:0) 78 00 Current Phase (15:8) cnfg_phase_alarm_timeout (read/write) 79 32 cnfg_sync_pulses (read/write) 7A cnfg_sync_phase (read/write) 7B cnfg_phase_loss_fine_limit (read/write) 73 84 Signed integer, Resolution = 6.284 ps, Range = +- 205.914 ns Lockingfr as reset Enable Multi Phase resp. Phase loss fine limit(2:0) (default = 2§-180o) (n(3:0)+1) Phase loss coarse limit in 2 7C Timeout value in 2s intervals (5:0) 2k/8k out from 8k invert T4 Indep Sync OC rates 00 MFr/FrSync 2B Fastsync Accums Sync monitor window 7D 02 cnfg_protection (read/write) 7E 85 cnfg_uPsel (read/write) 7F cnfg_sync_monitor (read/write) cnfg_interrupt (read/write) 00 Register in both ACS8510 & ACS8520 8k pulse en -1 = Uip-p 2k invert 2k pulse en ExtSync phase Sync reference source Interrupt Interrupt general purpose tristate o/p Interrupt polarity Protection value(7:0)- 85h = fully unprotected, 86h = single unprotected Micro-Processor type Register in ACS8510 & not ACS8520 Register not in ACS8510 but in ACS8520