Very Low Power/Voltage CMOS SRAM 512K X 8 bit WS628512 GENERAL DESCRIPTION The WS628512 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 4.5 to 5.5V supply voltage. Advanced 0.15um CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.5uA and maximum access time of 55/70ns in 5.0V operation. The WS628512 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The WS628512 is available in JEDEC standard 32-pin sTSOP 1 -8x13.4 mm, TSOP 1 -8x20mm, TSOP 2 -400mil, SOP -450 mil and PDIP –600mil packages. . FEATURES Low operation voltage: 4.5 ~ 5.5V Ultra low power consumption : 7mA＠1MHz (Max.) operating current 0.5 uA (Typ.) CMOS standby current High speed access time : 55/70ns (Max.) at Vcc = 5.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible Data retention voltage: 1.5V(Min.) Product Family Product Family Operating Standby (Typ. ) Temp (Vcc = 5.0V) Vcc. Range Speed (ns) 32L SOP WS628512LLFP WS628512LLST 0~70oC 0.5 uA 32L STSOP 1 4.5~5.5 WS628512LLT WS628512LLTE Package Type -40~85oC 55 / 70 0.5 uA WS628512LLP 1 WS reserves the right to change product or specification without notice. 32L TSOP 1 32L TSOP 2 32L PDIP Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM 2 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) PIN DESCRIPTIONS Name Type A0 – A18 Input Function Address inputs for selecting one of the 524,288 x 8 bit words in the RAM /CE is active LOW. Chip enables must be active when data read from or write to Input /CE the device. If either chip enable is not active, the device is deselected and in a standby power down mode. The Write enable input is active LOW. It controls read and write operations. With Input /WE the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip Input /OE is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. DQ0~DQ7 I/O These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Power Supply Vss Power Ground No connection NC TRUTH TABLE MODE /CE /WE /OE DQ0~7 Vcc Current Standby H X X High Z ICCSB, ICCSB1 Output Disabled L H H High Z ICC Read L H L DOUT ICC Write L L X DIN ICC Note: X means don’t care. (Must be low or high state) (1) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit VIN, VOUT Voltage on any pin relative to Vss -0.5 to 6.0 V VCC Voltage on Vcc supply relative to Vss -0.5 to 6.0 V PD Power Dissipation 1.0 W 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) OPERATING RANGE Range Ambient Temperature Vcc Commercial 0~70oC 4.5V ~ 5.5V o -40~85 C Industrial 4.5V ~ 5.5V 1. Overshoot : Vcc +1.0V in case of pulse width ≦20ns. 2. Undershoot : - 1.0V in case of pulse width ≦20ns. 3. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 8 pF CDQ Input/Output Capacitance VI/O=0V 10 pF 1. This parameter is guaranteed and not tested. DC ELECTRICAL CHARACTERISTICS Parameter Parameter Name o ( TA = 0 to + 70 C , Vcc = 5.0V ) Test Conduction MIN Guaranteed Input Low VIL Voltage (2) Guaranteed Input High VIH Voltage (2) IIL Input Leakage Current VCC=MAX, VIN=0 to VCC IOL Output Leakage VCC=MAX, /CE=VIH, or /OE=VIH , or Current /WE= VIL, VIO=0V to VCC VOL Output Low Voltage VCC=MAX, IOL = 2.1mA VOH Output High Voltage VCC=MIN, IOH = -1.0mA ICC Operating Power /CE=VIL, IIO=0mA, F=FMAX(3), Supply Current ICCSB ICCSB1 100%duty, VIN= VIL or VIH Standby Supply - TTL Standby -CMOS TYP(1) -0.5 0.6 2.2 Vcc+0.5 -1 1 -1 1 0.4 2.4 55 55 70 45 1 other pins= VIL or VIH Current /CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN Unit V V uA uA V V /CE=VIH, IUO=0mA, ≦0.2V MAX 0.5 20 mA mA uA o 1. Typical characteristics are at TA = 25 C and not 100% tested. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. 4 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) o DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70 C) Parameter Name Parameter VDR VCC for Data Retention ICCDR Data Retention Current Test Conduction /CE≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V Retention Time Operation tRDR Recovery TYP MAX 2.0 /CE≧VCC-0.2V, VCC=2.0V Unit V 0.5 VIN≧VCC-0.2V or VIN≦0.2V Chip Deselect to Data tSDR MIN 7 uA 0 ns tRC (1) ns See Retention Waveform Time 1.Read Cycle Time LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled ) AC TEST CONDITIONS Input Pulse Levels: Vcc/0V Input Rise and Fall Times: 1V/ns Input and Output Timing Reference Level: 0.5Vcc Output Load (See right) CL(1): 100pF + 1TTL(70ns) CL(1): 30pF + 1 TTL(55ns) Note: 1. Including scope and jig capacitance 2. R1=1800 ohm, R2=990 ohm 3. VTM= VCC 4. L= 5pF + 1 TTL (measurement with tLZ, tOLZ, tOHZ, tWHZ) 5 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) KEY TO SWITCHING WAVEFORMS WAVEFORMS INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE o AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70 C , Vcc = 5.0V ) [READ CYCLE] JEDEC Parameter Name Name Description 55 MIN 70 MAX 55 MIN MAX 70 Unit tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tCO Chip Select Access Time (/CE) 55 70 ns tGLQV tOE Output Enable to Output Valid 30 35 ns tELQX tLZ Chip Select to Output Low Z (/CE) 10 10 ns tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tHZ Chip Deselect to Output in High Z (/CE) 0 20 0 25 ns tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 25 ns tAXOX tOH Out Disable to Address Change 10 10 ns ns SWITCHING WAVEFORMS READ CYCLE (1) (Address Transition Controlled) 6 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) READ CYCLE (2) (/OE Controlled) NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. o AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70 C , Vcc = 5.0V ) [WRITE CYCLE] JEDEC Parameter Name Name Description 55 MIN 70 MAX MIN Unit MAX tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR Write Recovery Time (/CE, /WE) 0 0 ns tWLQZ tWHZ Write to Output in High Z 0 tDVWH tDW Data to Write Time Overlap 25 30 ns tWHDX tDH Data Hold from Write Time 0 0 ns tWHOX tOW End of Write to Output Active 5 5 ns 20 0 7 WS reserves the right to change product or specification without notice. 20 ns Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) SWITCHING WAVEFORMS WRITE CYCLE (1) (/WE Controlled, /OE High During WRITE) WRITE CYCLE (2) (/CE Controlled) 8 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) WRITE CYCLE (3) (/WE Controlled, /OE LOW) NOTES: 1. A write occurs during the overlap(tWP) of low /CE and low /WE. A write begins at the latest transition among /CE goes low and /WE goes low. A write ends at the earliest transition when /CE goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CE going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE or /WE going high. 9 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) ORDER INFORMATION WS628512 LL FP I -70 SPEED 55: 55ns 70: 70ns GRADE BLANK: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE FP: SOP TE: TSOP 2 ST: STSOP T: TSOP P: PDIP Note: Package material code “G” meets ROHS 10 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) 11 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) 12 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) 13 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) 14 WS reserves the right to change product or specification without notice. Rev. 2.1 WS628512 Low Power CMOS SRAM (512K x 8 bit) 15 WS reserves the right to change product or specification without notice. Rev. 2.1