74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state Rev. 5 — 15 December 2011 Product data sheet 1. General description The 74LVCH32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. Pin nOE controls the outputs so that the buses are effectively isolated. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. To ensure the high-impedance state during power-up or power-down, pin nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 2.3 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when VCC = 0 V All data inputs have bus hold Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C Packaged in plastic fine-pitch ball grid array package 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVCH32245AEC 74LVCH32245A Product data sheet 40 C to +125 C Description Version LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 5.5 1.05 mm All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 SOT536-1 © NXP B.V. 2011. All rights reserved. 2 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 4. Functional diagram A3 1DIR H3 1OE A5 A6 E5 4B5 T6 4B6 T5 3B7 R1 4A6 M2 3A7 R2 4A5 L1 3A6 3B6 M6 4B4 R6 P1 4A4 L2 3A5 3B5 M5 4B3 R5 P2 4A3 K1 3A4 3B4 L6 4B2 P6 N1 4A2 K2 3A3 3B3 L5 4B1 P5 N2 4A1 J1 3A2 3B2 K6 4B0 N6 T4 4A0 J2 3A1 3B1 K5 4OE N5 H2 4DIR J4 3A0 3B0 J6 2B7 T3 H1 2A7 D1 3DIR 3OE J5 2B6 H5 G1 2A6 D2 1A7 1B7 J3 2B5 H6 G2 2A5 C1 1A6 1B6 D6 2B4 G6 F1 2A4 C2 1A5 1B5 D5 2B3 G5 F2 2A3 B1 1A4 1B4 C6 2B2 F6 E1 2A2 B2 1A3 1B3 C5 2B1 F5 E2 2A1 A1 1A2 1B2 B6 2B0 E6 H4 2A0 A2 1A1 1B1 B5 2OE A4 1A0 1B0 2DIR T1 4A7 M1 4B7 T2 mna476 Fig 1. Logic symbol 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state VCC data input to internal circuit mna705 Fig 2. Bus hold circuit 5. Pinning information 5.1 Pinning mna475 Fig 3. 6 1A1 1A3 1A5 1A7 2A1 2A3 2A5 2A6 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A6 5 1A0 1A2 1A4 1A6 2A0 2A2 2A4 2A7 3A0 3A2 3A4 3A6 4A0 4A2 4A4 4A7 4 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 3 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 2 1B0 1B2 1B4 1B6 2B0 2B2 2B4 2B7 3B0 3B2 3B4 3B6 4B0 4B2 4B4 4B7 1 1B1 1B3 1B5 1B7 2B1 2B3 2B5 2B6 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B6 A B C D E F G H J K L M N P R T Pin configuration 5.2 Pin description Table 2. Pin description Symbol Ball Description nDIR (n = 1 to 4) A3, H3, J3, T3 direction control nOE (n = 1 to 4) A4, H4, J4, T4 output enable input (active LOW) 1A[0:7] A5, A6, B5, B6, C5, C6, D5, D6 input or output 1B[0:7] A2, A1, B2, B1, C2, C1, D2, D1 input or output 2A[0:7] E5, E6, F5, F6, G5, G6, H6, H5 input or output 2B[0:7] E2, E1, F2, F1, G2, G1, H1, H2 input or output 3A[0:7] J5, J6, K5, K6, L5, L6, M5, M6 input or output 3B[0:7] J2, J1, K2, K1, L2, L1, M2, M1 input or output 4A[0:7] N5, N6, P5, P6, R5, R6, T6, T5 input or output 4B[0:7] N2, N1, P2, P1, R2, R1, T1, T2 input or output GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V) M3, M4, N3, N4, R3, R4 VCC C3, C4, F3, F4, L3, L4, P3, P4 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 supply voltage © NXP B.V. 2011. All rights reserved. 4 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 6. Functional description Table 3. Function selection[1] Input Output nOE nDIR nAn nBn L L A=B inputs L H inputs B=A H X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 V output voltage VO Min IO output current ICC supply current [3] - 200 mA IGND ground current [3] 200 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 1000 mW [1] VO = 0 V to VCC Tamb = 40 C to +125 C [4] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] All supply and ground pins connected externally to one voltage source. [4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions functional Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V VI input voltage VO output voltage output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 2.3 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 3.6 V - - 10 ns/V 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL HIGH-level VCC = 1.2 V input voltage V = 1.65 V to 1.95 V CC LOW-level output voltage 40 C to +125 C Max Min Max Unit 1.08 - - 1.08 - V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - - 0.12 - 0.12 V - - 0.35 VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V LOW-level VCC = 1.2 V input voltage V = 1.65 V to 1.95 V CC HIGH-level output voltage Typ[1] 0.35 VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A - 0.1 5 - 20 A II input leakage current VCC = 3.6 V; VI = 5.5 V or GND [2] IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; [2] IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 40 - 160 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 6 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHL 40 C to +85 C Conditions [3][4] bus hold VCC = 1.65; VI = 0.58 V LOW current V = 2.3; V = 0.7 V CC I VCC = 3.0; VI = 0.8 V IBHH IBHLO IBHHO bus hold HIGH current VCC = 1.65; VI = 1.07 V bus hold LOW overdrive current VCC = 1.95 V bus hold HIGH overdrive current VCC = 1.95 V [3][4] VCC = 2.3; VI = 1.7 V 40 C to +125 C Unit Min Typ[1] Max Min Max 10 - - 10 - A 30 - - 25 - A 75 - - 60 - A 10 - - 10 - A 30 - - 25 - A 75 - - 60 - A 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A VCC = 3.0; VI = 2.0 V [3][5] [3][5] [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] Valid for data inputs only. Control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data inputs holds the input below the specified VI level. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter tpd propagation delay Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions nAn to nBn; nBn to nAn; see Figure 4 enable time VCC = 1.2 V Min Max - 13.0 - - - ns 1.5 5.2 12.2 1.5 13.8 ns VCC = 2.3 V to 2.7 V 1.0 2.8 6.0 1.0 6.7 ns VCC = 2.7 V 1.0 2.7 4.7 1.0 6.0 ns 1.0 2.4 4.5 1.0 6.0 ns - 15.0 - - - ns 1.5 5.9 15.0 1.5 16.9 ns nOE to nAn, nBn: see Figure 5 VCC = 1.65 V to 1.95 V Product data sheet Max VCC = 1.65 V to 1.95 V VCC = 1.2 V 74LVCH32245A Typ[1] [2] VCC = 3.0 V to 3.6 V ten Min [2] VCC = 2.3 V to 2.7 V 1.0 3.3 7.9 1.0 8.8 ns VCC = 2.7 V 1.5 3.5 6.7 1.5 8.5 ns VCC = 3.0 V to 3.6 V 1.0 2.7 5.5 1.0 7.0 ns All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 7 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter tdis disable time Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions nOE to nAn, nBn; see Figure 5 Max Min Max - 11.0 - - - ns VCC = 1.65 V to 1.95 V 1.5 4.9 13.1 1.5 14.7 ns VCC = 2.3 V to 2.7 V 0.5 2.7 7.1 0.5 7.9 ns VCC = 2.7 V 1.5 3.4 6.6 1.5 8.5 1.5 3.3 5.6 1.5 7.0 ns - - 1.0 - 1.5 ns VCC = 3.0 V to 3.6 V tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per buffer; VI = GND to VCC [4] [2] Typ[1] [2] VCC = 1.2 V [1] Min ns VCC = 1.65 V to 1.95 V - 11.5 - - - pF VCC = 2.3 V to 2.7 V - 15.2 - - - pF VCC = 3.0 V to 3.6 V - 18.5 - - - pF Typical values are measured at Tamb = 25 C and VCC = 1.2, 1.8, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs. 11. Waveforms VI nAn, nBn input VM GND t PHL t PLH VOH nBn, nAn output VM VOL mna477 VM = 1.5 V at VCC 2.7 V. VM = 0.5 VCC at VCC < 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. The input (nAn, nBn) to output (nBn, nAn) propagation delays 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 8 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled mna362 VM = 1.5 V at VCC 2.7 V. VM = 0.5 VCC at VCC < 2.7 V. VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.15 V at VCC 2.7 V. VY = VOH 0.3 V at VCC 2.7 V; VY = VOH 0.15 V at VCC 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. 3-state enable and disable times. 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 9 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Table 8. Load circuitry for switching times Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 10 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 1/2 C e ∅v M e ∅w M b T R P N M L K J H G F E D C B A ball A1 index area y1 C C A B C y e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 SOT536-1 Fig 7. Package outline SOT536-1 (LFBGA96) 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 11 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVCH32245A v.5 20111215 Product data sheet - 74LVCH32245A v.4 Modifications: 74LVCH32245A v.4 Modifications: 74LVCH32245A v.3 • Maximum propagation delay value for VCC = 1.65 V to 1.95 V at +125 C changed from 12.9 ns to 13.8 ns • Maximum enable time value for VCC = 1.65 V to 1.95 V at +125 C changed from 15.8 ns to 16.9 ns • Maximum disable time value for VCC = 1.65 V to 1.95 V at +125 C changed from 13.7 ns to 14.7 ns 20111109 • Product data sheet - 74LVCH32245A v.3 Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges. 20070820 Product data sheet - 74LVCH32245A v.2 74LVCH32245A v.2 20040511 Product specification - 74LVC_LVCH32245A v.1 74LVC_LVCH32245A v.1 19990901 Product specification - - 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 12 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 13 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVCH32245A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 15 December 2011 © NXP B.V. 2011. All rights reserved. 14 of 15 74LVCH32245A NXP Semiconductors 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 December 2011 Document identifier: 74LVCH32245A