AN10273 Power MOSFET single-shot and repetitive avalanche ruggedness rating Rev. 02 — 27 March 2009 Application note Document information Info Content Keywords Power MOSFET, single-shot, avalanche, ruggedness, safe operating condition Abstract Power MOSFETs are normally measured based on single-shot Unclamped Inductive Switching (UIS) avalanche energy. This note describes in detail the avalanche ruggedness performance, fundamentals of UIS operation and appropriate quantification method for the safe operating condition. AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating Revision history Rev Date Description 02 20090327 Updated Modifications: 01 20030901 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. Initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 2 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 1. Introduction Electronic applications have progressed significantly in recent years and have inevitably increased the demand for an intrinsically rugged power MOSFET. Device ruggedness is defined by the capacity of a device to sustain an avalanche current during an unclamped inductive load switching event. However, the avalanche ruggedness performance of a power MOSFET is normally measured within the industry as a single-shot Unclamped Inductive Switching (UIS) avalanche energy or EAS. Whilst this provides an easy and quick method of quantifying the robustness of a MOSFET in avalanche, it does not necessarily reflect the true device avalanche capability (see Ref. 1, Ref. 2 and Ref. 3) in an application. This note explains the fundamentals of UIS operation and reviews the appropriate method of quantifying the safe operating condition for a power MOSFET subjected to UIS operating condition. The note also covers the much-discussed repetitive avalanche ruggedness capability and how this operation can be quantified to operate safely. 2. Understanding power MOSFET single-shot avalanche events Single-shot avalanche capability of a device has been well established by both researchers and the industry (see Ref. 1, Ref. 2 and Ref. 3). The test can be carried out on a simple unclamped inductive load switching circuit as shown in Figure 1. 1 L drain 2 gate gate voltage R source Vs 001aaj764 Fig 1. Unclamped inductive load test circuit for MOSFET ruggedness evaluation 2.1 Single-shot UIS operation A voltage pulse is applied to the gate to turn the MOSFET ON as shown in Figure 2. This allows the load current to ramp up according to the inductor value (L) and the drain supply voltage (VS) as shown in Figure 3 and Figure 4. At the end of the gate pulse, the MOSFET is turned OFF. The current in the inductor continues to flow causing the voltage across the MOSFET to rise sharply. This overvoltage is clamped at breakdown voltage (VBR) until the load current reaches zero as illustrated in Figure 3. Typically VBR is: V BR ≈ 1.3 × BV DSS (1) The peak load current passing through the MOSFET before turn OFF will be the single-shot avalanche current (IAS) of the UIS event as illustrated in Figure 4. The rate at which the avalanche current decays is dependent on inductor value and can be determined by: AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 3 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating dI AS V BR – V S ----------- = – ---------------------dt AV L (2) The peak avalanche power (PAV(pk)) dissipated in the MOSFET shown in Figure 5 is a product of the breakdown voltage (VBR) and the avalanche current (IAS) as shown in Figure 3 and Figure 4, respectively. The avalanche energy dissipated is the area under the PAV waveform and can be estimated from the following expression: P AV ( pk ) × t AV E AS = --------------------------------2 (3) or V BR 1 2 E AS = --- ⋅ ---------------------- ⋅ LI AS 2 V BR – V S (4) Another crucial parameter involved in a MOSFET avalanche event is the junction temperature. The transient junction temperature rise during device avalanching at a time after the beginning of the avalanche event (τ) can be determined by the following expression: τ dZ th ( τ – t ) T jrise ( τ ) = ∫ P AV ( t ) ---------------------- dt dt (5) 0 where Zth is the power MOSFET transient thermal impedance. Alternatively, the maximum Tjrise can be approximated by: 2 T jrise ( max ) ≈ --- P av ( pk ) Z th ( t ⁄ 2 ) AV 3 (6) Assuming Tj(max) occurs at tAV/2 where Z th ( t AV ⁄ 2) is the device transient thermal impedance at half the tAV period. The maximum junction temperature resulting from the avalanche event will therefore be: T j ( max ) ≈ T jrise ( max ) + T j (7) where Tj refers to the junction temperature prior to turn OFF. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 4 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 2.1.1 Single-shot UIS waveforms VDS VGS VBR BVDSS ON VS OFF VS time Fig 2. Gate pulse, VGS Fig 3. Fig 4. 001aaj766 MOSFET Drain-Source Voltage, VDS ID P IAS PAV(pk) tAV time tAV 001aaj765 time area in PAV triangle = avalanche energy (EAS) dissipated time tAV 001aaj767 Current passing through MOSFET, ID Fig 5. 001aaj768 Peak avalanche power, PAV(pk) Tj Tj(max) Tjrise(max) Tj tAV time 001aaj769 Fig 6. Transient junction temperature profile of MOSFET during an avalanche event 2.2 Single-shot avalanche ruggedness rating The failure mechanism for a single-shot avalanche event in a power MOSFET is known to be due to the junction exceeding a maximum temperature above which catastrophic damage is done to the MOSFET. If the transient temperature resulting from an avalanche event, as illustrated in Figure 6, rises beyond a recommended rated value, the device risks being degraded. The recommended rated value is derated from the maximum temperature for optimum reliability. Blackburn (see Ref. 2) has discussed a general guideline in detail on the appropriate method of quantifying the single-shot avalanche capability of a device by taking avalanche current and initial junction temperature into consideration. Safe operation for a device single-shot UIS event can be defined by a maximum allowed avalanche current as a function of avalanche time. The maximum allowed avalanche current is set so that a safe maximum junction temperature, Tj(max) of 175 °C, is never exceeded. Using Equation 7, Figure 7 can be plotted. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 5 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 001aaj770 102 Tj = 25 °C Iav (A) Tj = 150 °C 10 1 10−2 10−1 1 10 tav (ms) Fig 7. Single-shot avalanche ruggedness SOAR curves of BUK764R0-55B limited to a Tj(max) of 175 °C Figure 7 shows the SOAR curves of a device single-shot avalanche capability. The 25 °C junction temperature curve shows the maximum allowable IAS for a given tAV at an initial Tj of 25 °C. This maximum IAV will give rise to a maximum junction temperature, Tjrise(max) of 150 °C resulting in a Tj(max) of 175 °C. The area under the SOAR curve will be the safe operating area (SOA). Similarly the 150 °C junction temperature curve will be the maximum operating limit for an initial Tj of 150 °C. The IAS(max) will induce a Tjrise(max) of 25 °C resulting in a Tj(max) of 175 °C. Again the area under the curve will be the SOA. The maximum junction temperature resulting in catastrophic device avalanche failure is approximately 380 °C, which is well in excess of the rated Tj(max) of 175 °C. However, operating beyond the rated Tj(max) may induce long-term detrimental effects to the power MOSFET and is not recommended. 3. Understanding power MOSFET repetitive avalanche events Repetitive avalanching simply refers to an operation involving repeated single-shot avalanche events as discussed earlier. Until recently, most manufacturers have avoided the issues pertaining to the power MOSFET repetitive avalanche capability. This is primarily due to the complexity in such operation and the difficulties in identifying the underlying physical degradation process in the device. Due to the traumatic nature of the avalanche event, a repetitive avalanche operation can be hazardous for a MOSFET, even when individual avalanche events are well below the single-shot UIS rating. This type of operation involves additional parameters such as the frequency, duty cycle and the thermal resistance (Rth) of the application during the repetitive avalanche event. However, it is possible to derate the single-shot rating to define a repetitive avalanche safe operating area. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 6 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 3.1 Repetitive UIS operation Referring to Figure 1, in a repetitive UIS test the gate is fed with a train of voltage pulses at frequency, f for a duty cycle as shown in Figure 8. The resulting breakdown voltage (VBR) and current passing through the load (ID) are the same as for a single-shot UIS except that the peak ID will now be denoted as repetitive avalanche current (IAR) as shown in Figure 9. To obtain the average repetitive avalanche power dissipated (PAV(R)) resulting from the repetitive UIS operation as shown in Figure 10. It is necessary to first calculate the EAS for a single avalanche event using Equation 3. Subsequently substituting EAS into the expression gives: P AV ( R ) = E AS × f (8) 3.1.1 Repetitive UIS waveforms VGS VBR BVDSS IAR VS tAV time time 001aaj772 001aaj771 Fig 8. Gate pulse, VGS Fig 9. MOSFET drain-source voltage, VDS and repetitive avalanche current, IAR Tj P ∆Tj To PAV(pk) PAV(R) tAV tAV time 001aaj773 Fig 10. Repetitive avalanche power PAV(R) Tj(avg) Tmb time 001aaj774 Fig 11. Transient junction temperature components of MOSFET during repetitive avalanching 3.2 Temperature Components The temperature rise from the repetitive avalanching mode in the power MOSFET can be defined as shown in Figure 11. The temperature (To) comprises the mounting base temperature (Tmb) and the temperature rise resulting from any ON state conduction (Tcond). (9) T O = T mb + T cond In addition there is a steady-state average junction temperature rise (∆Tj) resulting from the average repetitive avalanche power loss. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 7 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating ∆T j = P AV ( R ) × R th ( j – amb ) (10) where Rth(j-amb) is the thermal resistance of the device in the application. The summation of equations Equation 9 and Equation 10 will give the average junction temperature, Tj(avg) of a power MOSFET in repetitive UIS operation. T j ( avg ) = T O + ∆T j (11) 4. Repetitive avalanche ruggedness rating Following extensive investigation, it is clear that there is more than one failure or wear-out mechanism involved in repetitive avalanching. Temperature is not the only limiting factor to a repetitive avalanche operation. However, by limiting the temperature together with the repetitive avalanche current (IAR) it is possible to define an operating environment such that the avalanche conditions do not activate any device degradation. This allows the power MOSFET to operate under repetitive UIS conditions safely. Figure 12 shows the avalanche SOAR curves for BUK764R0-55B where ‘Rep. Ava’ represents the repetitive avalanche SOAR curve. 001aaj775 102 Tj = 25 °C Iav (A) Tj = 150 °C 10 Rep. Ava 1 10−2 10−1 1 10 tav (ms) Fig 12. Single-shot (initial Tj = 25 °C and 150 °C) and repetitive (Rep. Ava) avalanche ruggedness SOAR curves of BUK764R0-55B limited to a Tj(max) of 175 °C and Tj(avg) of 170 °C, respectively The two conditions which must be satisfied for safe operation of a power MOSFET under repetitive avalanching mode are as follows: 1. IAR should not exceed the Repetitive Avalanche SOAR Curve 2. Tj(avg) should not exceed 170 °C AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 8 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 5. Conclusion Power MOSFETs can sustain single-shot and repetitive avalanche events. Simple design rules and SOAR regions have been provided. 6. Examples The following examples examine cases of avalanche operation acceptance evaluation. 6.1 Single-shot avalanche case • • • • Device: BUK764R0-55B refer to Figure 12 L = 2 mH IAS = 40 A Rth(j-amb) = 5 K/W 6.1.1 Calculation steps 1. Using the above information, tAV can be determined using Equation 2, which in this case is 1.11 ms. Transferring the IAV and tAV conditions onto Figure 12. The operating point is under the Tj = 25 °C SOAR curve but over the Tj = 150 °C SOAR curve suggesting the operating condition maybe feasible. 2. To check, calculate the Tjrise(max) using Equation 6, where Zth(556 µs) on the data sheet is approximately 0.065 K/W. This will give a Tjrise(max) of 124.8 °C. Based upon the above calculations, the operating condition is acceptable if the device Tj < 50 °C. 6.2 Repetitive avalanche case • • • • • • Device: BUK764R0-55B refer to Figure 12 L = 0.5 mH IAR = 6 A f = 3 kHz Rth(j-amb) = 5 K/W TO = 100 °C 6.2.1 Calculation steps 1. tAV can be determined from the above information using Equation 2 which in this case is ~0.042 ms. Transferring the IAV and tAV conditions onto Figure 12. The operating point is under the boundary of the ‘Rep. Ava’ SOAR curve suggesting the operating condition is acceptable. Therefore, condition 1 is achieved. 2. Calculate the Single-shot avalanche energy dissipation (EAS) using Equation 3 (EAS = 9 mJ). 3. Calculate the average repetitive avalanche power (PAV(R)) using Equation 8 (PAV(R) = 27 W). AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 9 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 4. Calculate the average ∆Tj rise from repetitive avalanche (∆Tj) using Equation 10 (∆Tj = 135 °C). 5. Determine the average junction maximum temperature in repetitive avalanche operation (Tj(avg)) using Equation 11 (Tj(avg) = 235 °C). Therefore, condition 2 is not achieved. Based on the above calculations, the operating conditions satisfied the first but not the second requirement for safe repetitive avalanche operation. This was because the maximum Tj(avg) exceeded 170 °C. To make the above operation viable, the design engineer has to achieve the 2nd condition by reducing the Tj(avg). This can be achieved simply by improving the heat sinking of the device. Reducing the Rth(j-amb) from 5 K/W to 2.5 K/W will give a Tj(avg) of 167.5 °C satisfying condition 2 for safe repetitive avalanche operation. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 10 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 7. Appendix A The following table describes the symbols used throughout this application note. Table 1. Description of symbols Symbol Description BVDSS device rated breakdown voltage EAS single-shot avalanche energy ID MOSFET drain current IAS single-shot avalanche current IAR repetitive avalanche current IAV avalanche current L inductor PAV(pk) peak avalanche power PAV(R) average repetitive avalanche power Rth device thermal resistance Rth(j-amb) device junction to ambient thermal resistance To initial temperature Tcond ON-state conduction temperature Tj junction temperature Tjrise junction temperature rise Tjrise(max) maximum junction temperature rise Tj(max) maximum Junction temperature Tj(avg) average junction temperature Tmb mounting base/case temperature ∆Tj average temperature rise from average tAV avalanche period/duration VBR breakdown voltage VDS MOSFET drain-source voltage VGS MOSFET gate-source voltage Zth device Transient thermal impedance Z th ( t VS AV ⁄ 2) device transient thermal impedance Remark summation of Tmb and Tcond for repetitive avalanche measured at half the avalanche period supply voltage 8. References [1] Turn-off Failure of Power MOSFETs — D.L. Blackburn, Proc. 1985 IEEE Power Electronics Specialists Conference, pp 429-435, June 1985. [2] Power MOSFET Failure Revisited — D.L. Blackburn, Proc. 1988 IEEE Power Electronics Specialists Conference, pp 681-688, April 1988. [3] Boundary of Power-MOSFET, Unclamped Inductive-Switching (UIS) Avalanche-Current Capability — Rodney R. Stoltenburg, Proc. 1989 Applied Power Electronics Conference, pp 359-364, March 1989. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 11 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 9. Legal information 9.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 9.2 Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. AN10273_2 Application note © NXP B.V. 2009. All rights reserved. Rev. 02 — 27 March 2009 12 of 13 AN10273 NXP Semiconductors Power MOSFET single-shot/repetitive avalanche ruggedness rating 10. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Unclamped inductive load test circuit for MOSFET ruggedness evaluation . . . . . . . . . . . . . . . . . . . . . .3 Gate pulse, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . .5 MOSFET Drain-Source Voltage, VDS . . . . . . . . . . .5 Current passing through MOSFET, ID . . . . . . . . . .5 Peak avalanche power, PAV(pk) . . . . . . . . . . . . . . .5 Transient junction temperature profile of MOSFET during an avalanche event . . . . . . . . . . . . . . . . . . .5 Single-shot avalanche ruggedness SOAR curves of BUK764R0-55B limited to a Tj(max) of 175 C . . . . .6 Fig 8. Fig 9. Gate pulse, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MOSFET drain-source voltage, VDS and repetitive avalanche current, IAR . . . . . . . . . . . . . . . . . . . . . . 7 Fig 10. Repetitive avalanche power PAV(R) . . . . . . . . . . . . 7 Fig 11. Transient junction temperature components of MOSFET during repetitive avalanching. . . . . . . . . 7 Fig 12. Single-shot (initial Tj = 25 C and 150 C) and repetitive (Rep. Ava) avalanche ruggedness SOAR curves of BUK764R0-55B limited to a Tj(max) of 175 C and Tj(avg) of 170 C, respectively. . . . . . . . . 8 11. Contents 1 2 2.1 2.1.1 2.2 3 3.1 3.1.1 3.2 4 5 6 6.1 6.1.1 6.2 6.2.1 7 8 9 9.1 9.2 9.3 10 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Understanding power MOSFET single-shot avalanche events . . . . . . . . . . . . . . . . . . . . . . . . 3 Single-shot UIS operation. . . . . . . . . . . . . . . . . 3 Single-shot UIS waveforms. . . . . . . . . . . . . . . . 5 Single-shot avalanche ruggedness rating. . . . . 5 Understanding power MOSFET repetitive avalanche events . . . . . . . . . . . . . . . . . . . . . . . . 6 Repetitive UIS operation . . . . . . . . . . . . . . . . . . 7 Repetitive UIS waveforms. . . . . . . . . . . . . . . . . 7 Temperature Components . . . . . . . . . . . . . . . . 7 Repetitive avalanche ruggedness rating . . . . . 8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Single-shot avalanche case . . . . . . . . . . . . . . . 9 Calculation steps . . . . . . . . . . . . . . . . . . . . . . . 9 Repetitive avalanche case . . . . . . . . . . . . . . . . 9 Calculation steps . . . . . . . . . . . . . . . . . . . . . . . 9 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 March 2009 Document identifier: AN10273_2