BF1218 Dual N-channel dual gate MOSFET Rev. 01 — 14 April 2010 Product data sheet 1. Product profile 1.1 General description The BF1218 is a combination of two dual gate MOSFET amplifiers with shared source and gate2 leads and an integrated switch. The integrated switch is operated by the gate1 bias of amplifier B. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during Automatic Gain Control (AGC). Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features and benefits Two low noise gain controlled amplifiers in a single package. One with a fully integrated bias and one with a partly integrated bias Internal switch to save external components Superior cross modulation performance during AGC High forward transfer admittance High forward transfer admittance to input capacitance ratio 1.3 Applications Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage digital and analog television tuners professional communication equipment BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 1.4 Quick reference data Table 1. Quick reference data Per MOSFET unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - - 6 V - - 30 mA - - 180 mW amplifier A; ID = 19 mA 26 31 41 mS amplifier B; ID = 15 mA 25 30 40 mS VDS drain-source voltage DC ID drain current DC Ptot total power dissipation Tsp 109 C yfs forward transfer admittance f = 100 MHz; Tj = 25 C Ciss(G1) input capacitance at gate1 f = 100 MHz amplifier A [2] - 2.1 2.6 pF amplifier B [2] - 2.1 2.6 pF [2] - 20 - fF amplifier A; f = 400 MHz - 0.9 1.5 dB amplifier B; f = 800 MHz - 1.4 2.0 dB Crss reverse transfer capacitance f = 100 MHz NF noise figure Xmod [1] YS = YS(opt) cross modulation input level for k = 1 %; fw = 50 MHz; funw = 60 MHz at 40 dB AGC amplifier A [3] 102 105 - dBV amplifier B [4] 102 105 - dBV - - 150 C junction temperature Tj [1] Tsp is the temperature at the soldering point of the source lead. [2] Calculated from S-parameters. [3] Measured in Figure 33 test circuit. [4] Measured in Figure 34 test circuit. 2. Pinning information Table 2. Discrete pinning Pin Description 1 gate1 (AMP A) 2 gate2 3 gate1 (AMP B) 4 drain (AMP B) 5 source 6 drain (AMP A) Simplified outline 6 5 Graphic symbol 4 AMP A G1A 1 2 3 DA G2 S G1B DB AMP B sym089 BF1218_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 3. Ordering information Table 3. Ordering information Type number BF1218 Package Name Description Version - plastic surface-mounted package; 6 leads SOT363 4. Marking Table 4. Marking codes Type number Marking code BF1218 M7 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per MOSFET VDS drain-source voltage DC - 6 V ID drain current DC - 30 mA IG1 gate1 current - 10 mA IG2 gate2 current - 10 mA Ptot total power dissipation - 180 mW Tstg storage temperature 65 +150 C Tj junction temperature - 150 C [1] Tsp 109 C [1] Tsp is the temperature at the soldering point of the source lead. 001aac193 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Tsp (˚C) Fig 1. BF1218_1 Product data sheet Power derating curve All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Typ Unit 225 K/W 7. Static characteristics Table 7. Static characteristics Tj = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit amplifier A 6 - - V amplifier B 6 - - V Per MOSFET; unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0 V; ID = 10 A V(BR)G1-SS gate1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 - 10 V V(BR)G2-SS gate2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 - 10 V VF(S-G1) forward source-gate1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 - 1.5 V VF(S-G2) forward source-gate2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 - 1.5 V VG1-S(th) gate1-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 A 0.3 - 1.0 V VG2-S(th) gate2-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 A 0.4 - 1.0 V IDS drain-source current VG2-S = 4 V; VDS(B) = 5 V; RG1 = 86 k IG1-S IG2-S gate1 cut-off current gate2 cut-off current 14 - 24 mA amplifier B [2] 10 - 20 mA amplifier A; VG1-S(A) = 5 V; ID(B) = 0 A - - 50 nA amplifier B; VG1-S(B) = 5 V; VDS(B) = 0 V - - 50 nA - - 20 nA VG2-S = 4 V; VG1-S(B) = 0 V; VG1-S(A) = VDS(A) = VDS(B) = 0 V RG1 connects gate1 (B) to VGG = 0 V (see Figure 3). [2] RG1 connects gate1 (B) to VGG = 5 V (see Figure 3). Product data sheet [1] VG2-S = VDS(A) = 0 V [1] BF1218_1 amplifier A; VDS(A) = 5 V All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag356 20 ID (mA) 16 (1) G1A DA (2) 12 G2 S (3) G1B 8 RG1 (4) (5) (6) 4 DB VGG 001aac205 0 0 1 2 3 4 5 VGG (V) (1) ID(B); RG1 = 68 k. VGG = 5 V: amplifier A is off; amplifier B is on. (2) ID(B); RG1 = 86 k. VGG = 0 V: amplifier A is on; amplifier B is off. (3) ID(B); RG1 = 100 k. (4) ID(A); RG1 = 100 k. (5) ID(A); RG1 = 86 k. (6) ID(A); RG1 = 68 k. Fig 2. Drain currents of MOSFET A and B as a function of VGG Fig 3. Functional diagram 8. Dynamic characteristics 8.1 Dynamic characteristics for amplifier A Table 8. Dynamic characteristics for amplifier A[1] Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA; unless otherwise specified. Symbol Parameter Conditions yfs forward transfer admittance f = 100 MHz; Tj = 25 C Min Typ Max Unit 26 31 41 mS Ciss(G1) input capacitance at gate1 f = 100 MHz [2] - 2.1 2.6 pF Ciss(G2) input capacitance at gate2 f = 100 MHz [2] - 3.4 - pF f = 100 MHz [2] - 0.8 - pF [2] - 20 - fF f = 200 MHz; GS = 2 mS; GL = 0.5 mS 32 36 40 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 28 32 36 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 24 28 33 dB Coss output capacitance Crss reverse transfer capacitance f = 100 MHz Gtr transducer power gain BS = BS(opt); BL = BL(opt) NF noise figure BF1218_1 Product data sheet f = 11 MHz; GS = 20 mS; BS = 0 S - 3.0 - dB f = 400 MHz; YS = YS(opt) - 0.9 1.5 dB f = 800 MHz; YS = YS(opt) - 1.1 1.7 dB All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET Table 8. Dynamic characteristics for amplifier A[1] …continued Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA; unless otherwise specified. Symbol Parameter Xmod Conditions cross modulation Min Typ Max Unit at 0 dB AGC 90 - - dBV at 10 dB AGC - 90 - dBV at 20 dB AGC - 99 - dBV at 40 dB AGC 102 105 - dBV [3] input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] For the MOSFET not in use: VG1-S(B) = 0 V; VDS(B) = 0 V. [2] Calculated from S-parameters. [3] Measured in Figure 33 test circuit. 8.1.1 Graphics for amplifier A 001aaa554 30 001aaa555 32 (1) ID (mA) (2) ID (mA) (3) (1) (2) (4) 24 (3) 20 (4) (5) 16 (5) (6) 10 (7) (6) 8 (8) (9) (7) 0 0 0 0.4 0.8 1.2 1.6 2 VG1-S (V) 0 2 6 VDS (V) (1) VG2-S = 4 V. (1) VG1-S(A) = 1.8 V. (2) VG2-S = 3.5 V. (2) VG1-S(A) = 1.7 V. (3) VG2-S = 3 V. (3) VG1-S(A) = 1.6 V. (4) VG2-S = 2.5 V. (4) VG1-S(A) = 1.5 V. (5) VG2-S = 2 V. (5) VG1-S(A) = 1.4 V. (6) VG2-S = 1.5 V. (6) VG1-S(A) = 1.3 V. (7) VG2-S = 1 V. (7) VG1-S(A) = 1.2 V. VDS(A) = 5 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 C. 4 (8) VG1-S(A) = 1.1 V. (9) VG1-S(A) = 1 V. VG2-S = 4 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 C. Fig 4. Amplifier A: transfer characteristics; typical values BF1218_1 Product data sheet Fig 5. Amplifier A: output characteristics; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaa556 40 yfs (mS) ID(A) (mA) 16 (1) (2) 30 001aac206 20 12 20 (3) 8 (4) 10 4 (5) (6) 0 0 0 8 16 24 0 32 20 40 60 ID(B) (μA) ID (mA) (1) VG2-S = 4 V. VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 5 V; VG1-S(B) = 0 V; Tj = 25 C. (2) VG2-S = 3.5 V. ID(B) = internal gate1 current = current in pin drain (AMP B) if MOSFET (B) is switched off. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. VDS(A) = 5 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 C. Fig 6. Amplifier A: forward transfer admittance as a function of drain current; typical values BF1218_1 Product data sheet Fig 7. Amplifier A: drain current as a function of internal gate1 current; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaa558 20 ID (mA) 16 001aaa559 32 ID (mA) 24 (1) 12 (2) (3) 16 (4) (5) 8 (6) 8 4 0 0 0 1 2 3 4 5 0 2 4 Vsup (V) 6 VG2-S (V) VDS(A) = VDS(B) = Vsup; VG2-S = 4 V; Tj = 25 C; RG1 = 86 k (connected to ground); see Figure 3. (1) VDS(B) = 5 V. (2) VDS(B) = 4.5 V. (3) VDS(B) = 4 V. (4) VDS(B) = 3.5 V. (5) VDS(B) = 3 V. (6) VDS(B) = 2.5 V. VDS(A) = 5 V; VG1-S(B) = 0 V; gate1 (AMP A) is open; Tj = 25 C. Fig 8. Amplifier A: drain current of amplifier A as a function of supply voltage of A and B amplifier; typical values 001aac195 120 Vunw (dBμV) Fig 9. Amplifier A: drain current as a function of gate2 voltage; typical values 001aac196 0 gain reduction (dB) 10 110 20 100 30 90 40 80 50 0 10 20 30 40 50 gain reduction (dB) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 C; see Figure 33. Fig 10. Amplifier A: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values BF1218_1 Product data sheet 0 1 2 3 4 VAGC (V) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; see Figure 33. Fig 11. Amplifier A: gain reduction as a function of AGC voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aac197 28 001aaa564 102 bis, gis (mS) ID (mA) 10 20 bis 1 12 gis 10−1 10−2 4 0 10 20 30 40 50 gain reduction (dB) 10 001aag358 102 ϕfs (deg) Yfs Yfs (mS) −102 −10 10 103 f (MHz) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; Tamb = 25 C; see Figure 33. Fig 12. Amplifier A: drain current as a function of gain reduction; typical values 102 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA Fig 13. Amplifier A: input admittance as a function of frequency; typical values 001aaa566 103 103 −ϕrs (deg) yrs (mS) −ϕrs 102 102 ϕfs yrs 1 10−1 10 102 f (MHz) −1 10 −10−1 103 1 Fig 14. Amplifier A: forward transfer admittance and phase as a function of frequency; typical values Product data sheet 10 1 103 102 f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA BF1218_1 10 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA Fig 15. Amplifier A: reverse transfer admittance and phase as a function of frequency; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag360 10 bos, gos (mS) 1 bos 10−1 gos 10−2 102 10 f (MHz) 103 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA Fig 16. Amplifier A: output admittance as a function of frequency; typical values 8.1.2 Scattering parameters for amplifier A Table 9. Scattering parameters for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 C; typical values. F (MHz) s11 Magnitude (ratio) Angle (degree) s21 Magnitude (ratio) Angle (degree) s12 Magnitude (ratio) Angle (degree) s22 Magnitude (ratio) Angle (degree) 40 0.9927 4.10 3.1833 175.69 0.0006 92.99 0.9927 1.24 100 0.9897 7.68 3.1743 171.77 0.0011 81.72 0.9923 2.54 200 0.9852 15.36 3.1494 163.56 0.0023 79.23 0.9912 5.09 300 0.9758 22.84 3.1146 155.46 0.0033 74.65 0.9904 7.60 400 0.9655 30.19 3.0718 147.53 0.0042 70.46 0.9890 10.10 500 0.9513 37.55 3.0156 139.61 0.0049 66.38 0.9874 12.60 600 0.9341 44.85 2.9482 131.74 0.0056 62.22 0.9853 15.11 700 0.9160 51.99 2.8755 124.04 0.0061 58.44 0.9832 17.61 800 0.8964 58.99 2.8003 116.41 0.0064 54.48 0.9806 20.12 900 0.8737 65.84 2.7206 108.93 0.0066 50.78 0.9793 22.57 1000 0.8499 72.51 2.6352 101.62 0.0067 46.49 0.9776 25.05 8.1.3 Noise data for amplifier A Table 10. Noise data for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 C; typical values; unless otherwise specified. f (MHz) BF1218_1 Product data sheet NFmin (dB) opt rn (ratio) (ratio) (degree) 400 0.9 0.77 22.7 0.65 800 1.1 0.73 45.75 0.62 All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 8.2 Dynamic characteristics for amplifier B Table 11. Dynamic characteristics for amplifier B[1] Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. Symbol Parameter Conditions yfs f = 100 MHz; Tj = 25 C forward transfer admittance Min Typ Max Unit 25 30 40 mS Ciss(G1) input capacitance at gate1 f = 100 MHz [2] - 2.1 2.6 pF Ciss(G2) input capacitance at gate2 f = 100 MHz [2] - 3.4 - pF f = 100 MHz [2] - 0.85 - pF Crss reverse transfer capacitance f = 100 MHz [2] - 20 - fF Gtr transducer power gain f = 200 MHz; GS = 2 mS; GL = 0.5 mS 31 35 39 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 28 32 36 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 26 30 34 dB f = 11 MHz; GS = 20 mS; BS = 0 S - 3 - dB f = 400 MHz; YS = YS(opt) - 1.1 1.7 dB - 1.4 2.0 dB at 0 dB AGC 90 - - dBV at 10 dB AGC - 90 - dBV at 20 dB AGC - 98 - dBV at 40 dB AGC 102 105 - dBV Coss NF output capacitance noise figure BS = BS(opt); BL = BL(opt) f = 800 MHz; YS = YS(opt) Xmod cross modulation input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] For the MOSFET not in use: VG1-S(A) = 0 V; VDS(A) = 0 V. [2] Calculated from S-parameters. [3] Measured in Figure 34 test circuit. BF1218_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 [3] © NXP B.V. 2010. All rights reserved. 11 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 8.2.1 Graphics for amplifier B 001aag361 30 (1) (2) (3) ID (mA) 001aag362 24 (1) ID (mA) (4) 20 (2) 16 (3) (5) (4) (5) 10 8 (6) (6) (7) (7) 0 0 0 0.4 0.8 1.2 1.6 2.0 VG1-S (V) 0 2 (1) VG1-S(B) = 1.6 V. (2) VG2-S = 3.5 V. (2) VG1-S(B) = 1.5 V. (3) VG2-S = 3 V. (3) VG1-S(B) = 1.4 V. (4) VG2-S = 2.5 V. (4) VG1-S(B) = 1.3 V. (5) VG2-S = 2 V. (5) VG1-S(B) = 1.2 V. (6) VG2-S = 1.5 V. (6) VG1-S(B) = 1.1 V. (7) VG2-S = 1 V. (7) VG1-S(B) = 1 V. Fig 17. Amplifier B: transfer characteristics; typical values BF1218_1 Product data sheet 6 VDS (V) (1) VG2-S = 4 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C. 4 VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C. Fig 18. Amplifier B: output characteristics; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag363 100 IG1 (μA) 001aag364 40 Yfs (mS) (1) 80 (1) 32 (2) (2) (3) 60 (3) 24 40 (4) 16 (4) (5) (5) 20 8 (6) (6) (7) (7) 0 0 0 0.4 0.8 1.2 1.6 2.0 VG1-S (V) 0 8 (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (7) VG2-S = 1 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C. 001aag365 20 ID (mA) 24 32 ID (mA) (1) VG2-S = 4 V. Fig 19. Amplifier B: gate1 current as a function of gate1 voltage; typical values 16 VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C. Fig 20. Amplifier B: forward transfer admittance as a function of drain current; typical values 001aag366 20 ID (mA) 16 16 12 12 8 8 4 4 0 0 0 10 20 30 40 50 IG1 (μA) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C. Fig 21. Amplifier B: drain current as a function of gate1 current; typical values BF1218_1 Product data sheet 0 1 2 3 4 5 VGG (V) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C; RG1 = 86 k (connected to VGG); see Figure 3. Fig 22. Amplifier B: drain current as a function of gate1 supply voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag367 25 ID (mA) ID (mA) (1) 20 001aag368 24 (2) (1) 16 (2) (3) (4) (5) (6) (7) (8) 15 10 (3) (4) (5) 8 (9) 5 0 0 0 1 2 3 4 5 VGG = VDS (V) 0 2 4 6 VG2-S (V) (1) RG1 = 47 k. (1) VGG = 5.0 V. (2) RG1 = 56 k. (2) VGG = 4.5 V. (3) RG1 = 68 k. (3) VGG = 4.0 V. (4) RG1 = 82 k. (4) VGG = 3.5 V. (5) RG1 = 86 k. (5) VGG = 3.0 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C; RG1 = 86 k (connected to VGG); see Figure 3. (6) RG1 = 100 k. (7) RG1 = 120 k. (8) RG1 = 150 k. (9) RG1 = 180 k. VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C; RG1 is connected to VGG; see Figure 3. Fig 23. Amplifier B: drain current as a function of gate1 supply voltage and drain supply voltage; typical values BF1218_1 Product data sheet Fig 24. Amplifier B: drain current as a function of gate2 voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aag369 50 IG1 (μA) 001aag370 120 (1) Vunw (dBμV) (2) 110 40 (3) 30 (4) 100 (5) 20 90 10 0 80 0 2 4 6 0 20 VG2-S (V) 40 60 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 86 k (connected to VGG); fw = 50 MHz; funw = 60 MHz; Tamb = 25 C; see Figure 34. (1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 C; RG1 = 86 k (connected to VGG); see Figure 3. Fig 25. Amplifier B: gate1 current as a function of gate2 voltage; typical values 001aag371 0 gain reduction (dB) 10 Fig 26. Amplifier B: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aag372 24 ID (mA) 18 20 12 30 6 40 0 50 0 1 2 3 4 0 VAGC (V) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 86 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Figure 34. Fig 27. Amplifier B: gain reduction as a function of AGC voltage; typical values BF1218_1 Product data sheet 20 40 60 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 86 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Figure 34. Fig 28. Amplifier B: drain current as a function of gain reduction; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 15 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaa581 102 001aag374 102 −102 bis, gis (mS) Yfs (mS) 10 ϕfs (deg) Yfs bis −10 10 1 ϕfs gis 10−1 10−2 10 102 10 f (MHz) Fig 29. Amplifier B: input admittance as a function of frequency; typical values 001aaa583 103 −ϕrs (deg) yrs (μS) −ϕrs 102 102 f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA 103 −1 103 1 103 102 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA Fig 30. Amplifier B: forward transfer admittance and phase as a function of frequency; typical values 001aag376 10 bos, gos (mS) 1 bos 10−1 gos yrs 10 10 1 10 1 103 102 10−2 10 f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA Fig 31. Amplifier B: reverse transfer admittance and phase as a function of frequency; typical values BF1218_1 Product data sheet 102 f (MHz) 103 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA Fig 32. Amplifier B: output admittance as a function of frequency; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 16 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 8.2.2 Scattering parameters for amplifier B Table 12. Scattering parameters for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 15 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) Magnitude (ratio) Angle (degree) 40 0.9841 4.20 2.9772 175.44 0.0005 106.03 0.9923 1.40 100 0.9799 7.68 2.9694 171.40 0.0011 88.52 0.9927 2.88 200 0.9775 15.24 2.9472 162.86 0.0023 87.60 0.9914 5.77 300 0.9706 22.70 2.9147 154.41 0.0034 85.98 0.9902 8.61 400 0.9632 30.08 2.8754 146.10 0.0046 85.09 0.9888 11.43 500 0.9515 37.46 2.8213 137.77 0.0056 84.03 0.9870 14.26 600 0.9377 44.80 2.7560 129.44 0.0065 83.30 0.9839 17.16 700 0.9229 52.10 2.6865 121.24 0.0075 82.99 0.9810 20.05 800 0.9062 59.33 2.6119 113.09 0.0084 82.08 0.9777 22.93 900 0.8864 66.35 2.5318 105.04 0.0091 81.36 0.9754 25.77 1000 0.8650 73.21 2.4437 97.11 0.0098 80.34 0.9714 28.64 8.2.3 Noise data for amplifier B Table 13. Noise data for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 15 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 C; typical values; unless otherwise specified. BF1218_1 Product data sheet f (MHz) NFmin (dB) opt (ratio) (degree) 400 1.1 0.72 22.83 0.66 800 1.4 0.68 46.42 0.64 All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 rn () © NXP B.V. 2010. All rights reserved. 17 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 9. Test information VDS(A) 5V VAGC 4.7 nF 10 kΩ 4.7 nF RGEN 50 Ω G2 4.7 nF Vi RL 50 Ω S BF1218 G1B 50 Ω 4.7 nF DA G1A 4.7 nF 50 Ω L1 2.2 μH DB L2 2.2 μH RG1 4.7 nF VDS(A) 5V VGG 0V 001aak331 Fig 33. Cross modulation test set-up for amplifier A VDS(A) 5V VAGC 4.7 nF 10 kΩ 4.7 nF 50 Ω DA G1A 4.7 nF G2 4.7 nF RGEN 50 Ω L1 2.2 μH BF1218 G1B 50 Ω S DB RG1 4.7 nF L2 2.2 μH RL 50 Ω 4.7 nF Vi VGG 5V VDS(A) 5V 001aak332 Fig 34. Cross modulation test set-up for amplifier B BF1218_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 18 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 10. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 35. Package outline SOT363 BF1218_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 19 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 11. Abbreviations Table 14. Abbreviations Acronym Description AGC Automatic Gain Control DC Direct Current MOSFET Metal-Oxide Semiconductor Field-Effect Transistor UHF Ultra High Frequency VHF Very High Frequency 12. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes BF1218_1 20100414 Product data sheet - - BF1218_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 20 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or BF1218_1 Product data sheet malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 21 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] BF1218_1 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 © NXP B.V. 2010. All rights reserved. 22 of 23 BF1218 NXP Semiconductors Dual N-channel dual gate MOSFET 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.2 8.2.1 8.2.2 8.2.3 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics for amplifier A. . . . . . . 5 Graphics for amplifier A . . . . . . . . . . . . . . . . . . 6 Scattering parameters for amplifier A . . . . . . . 10 Noise data for amplifier A . . . . . . . . . . . . . . . . 10 Dynamic characteristics for amplifier B. . . . . . 11 Graphics for amplifier B . . . . . . . . . . . . . . . . . 12 Scattering parameters for amplifier B . . . . . . . 17 Noise data for amplifier B . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 April 2010 Document identifier: BF1218_1