BF908WR N-channel dual-gate MOS-FET

DISCRETE SEMICONDUCTORS
DATA SHEET
BF908WR
N-channel dual-gate MOS-FET
Preliminary specification
1995 Apr 25
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
FEATURES
PINNING
 High forward transfer admittance
 Short channel transistor with high forward transfer
admittance to input capacitance ratio
 Low noise gain controlled amplifier up to 1 GHz.
PIN
SYMBOL
1
s, b
2
d
drain
3
g2
gate 2
4
g1
gate 1
APPLICATIONS
 VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
communications equipment.
DESCRIPTION
source
d
3
4
g2
DESCRIPTION
g1
Depletion type field effect transistor in a plastic
microminiature SOT343R package. The transistor is
protected against excessive input voltage surges by
integrated back-to-back diodes between gates and
source.
2
1
s,b
Top view
MAM198
CAUTION
Marking code: MD.
The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.
Fig.1 Simplified outline (SOT343R) and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
drain-source voltage


12
V
ID
drain current


40
mA
Ptot
total power dissipation


300
mW
Tj
operating junction temperature


150
C
yfs
forward transfer admittance
36
43
50
mS
Cig1-s
input capacitance at gate 1
2.4
3.1
4
pF
Crs
reverse transfer capacitance
f = 1 MHz
20
30
45
fF
F
noise figure
f = 800 MHz

1.5
2.5
dB
1995 Apr 25
2
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
drain-source voltage

12
V
ID
drain current

40
mA
IG1
gate 1 current

10
mA
IG2
gate 2 current

10
mA
Ptot
total power dissipation

300
mW
Tstg
storage temperature
65
+150
C
Tj
operating junction temperature

+150
C
up to Tamb = 45 C; see Fig.2;
note 1
Note
1. Device mounted on a printed-circuit board.
MLD154
400
handbook, halfpage
Ptot
(mW)
300
200
100
0
0
50
100
150
200
Tamb ( oC)
Fig.2 Power derating curve.
1995 Apr 25
3
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth j-a
thermal resistance from junction to ambient
note 1
350
K/W
Rth j-s
thermal resistance from junction to soldering point
Ts = 87 C; note 2
210
K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.

MAX.
UNIT
V(BR)G1-SS
gate 1-source breakdown voltage
VG2-S = VDS = 0; IG1-S = 10 mA
8
V(BR)G2-SS
gate 2-source breakdown voltage
VG1-S = VDS = 0; IG2-S = 10 mA
8

20
V
V(P)G1-S
gate 1-source cut-off voltage
VG2-S = 4 V; VDS = 8 V; ID = 20 A 

2
V
V(P)G2-S
gate 2-source cut-off voltage
VG1-S = 4 V; VDS = 8 V; ID = 20 A 

1.5
V
IDSS
drain-source current
VG2-S = 4 V; VDS = 8 V; VG1-S = 0
3
15
27
mA
IG1-SS
gate 1 cut-off current
VG2-S = VDS = 0; VG1-S = 5 V


50
nA
IG2-SS
gate 2 cut-off current
VG1-S = VDS = 0; VG2-S = 5 V


50
nA
20
V
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VDS = 8 V; VG2-S = 4 V; ID = 15 mA; unless otherwise specified.
SYMBOL
PARAMETER
yfs
forward transfer admittance
CONDITIONS
pulsed; Tj = 25 C
MIN.
36
TYP.
43
MAX.
50
UNIT
mS
Cig1-s
input capacitance at gate 1
f = 1 MHz
2.4
3.1
4
pF
Cig2-s
input capacitance at gate 2
f = 1 MHz
1.2
1.8
2.5
pF
Cos
drain-source capacitance
f = 1 MHz
1.2
1.7
2.2
pF
Crs
reverse transfer capacitance
f = 1 MHz
20
30
45
fF
F
noise figure
f = 200 MHz; GS = 2 mS; BS = BSopt

0.6
1.2
dB
f = 800 MHz; GS = GSopt; BS = BSopt

1.5
2.5
dB
1995 Apr 25
4
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
MRC282
MRC281
40
handbook, halfpage
30
handbook, halfpage
VG2-S = 4 V
ID
(mA)
ID
(mA)
3V
30
VG1-S = 0.3 V
0.2 V
2V
20
0.1 V
1.5 V
1V
20
0V
0.5 V
10
−0.1 V
10
−0.2 V
−0.3 V
0V
0
−0.6
−0.4
0
−0.2
0
0.2
0.4
0
0.6
4
8
12
16
VDS (V)
VG1-S (V)
VDS = 8 V.
Tj = 25 C.
VG2-S = 4 V.
Tj = 25 C.
Fig.3 Transfer characteristics; typical values.
Fig.4 Output characteristics; typical values.
MRC280
50
Yfs
(mS)
40
MRC276
60
4V
3V
2V
Yfs
(mS)
1.5 V
40
30
1V
20
20
0.5 V
10
VG2-S = 0 V
0
0
0
5
10
15
20
40
25
I D (mA)
0
40
80
120
160
T j (o C)
VDS = 8 V.
Tj = 25 C.
Fig.5
Forward transfer admittance as a function
of drain current; typical values.
1995 Apr 25
Fig.6
5
Forward transfer admittance as a function
of junction temperature; typical values.
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
PACKAGE OUTLINE
Plastic surface-mounted package; reverse pinning; 4 leads
D
SOT343R
E
B
A
X
HE
y
v M A
e
3
4
Q
A
A1
c
2
w M B
1
bp
Lp
b1
e1
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
b1
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.4
0.3
0.7
0.5
0.25
0.10
2.2
1.8
1.35
1.15
1.3
1.15
2.2
2.0
0.45
0.15
0.23
0.13
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
97-05-21
06-03-16
SOT343R
1995 Apr 25
EUROPEAN
PROJECTION
6
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
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information supplied prior to the publication hereof.
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sale of NXP Semiconductors.
1995 Apr 25
7
NXP Semiconductors
Preliminary specification
N-channel dual-gate MOS-FET
BF908WR
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Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
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1995 Apr 25
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R77/01/pp9
Date of release: 1995 Apr 25