74LVC1G66 Bilateral switch

74LVC1G66
Bilateral switch
Rev. 9 — 15 January 2015
Product data sheet
1. General description
The 74LVC1G66 provides one single pole, single-throw analog switch function. It has two
input/output terminals (Y and Z) and an active HIGH enable input pin (E). When E is LOW,
the analog switch is turned off.
Schmitt-trigger action at the enable input makes the circuit tolerant of slower input rise and
fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
 Wide supply voltage range from 1.65 V to 5.5 V
 Very low ON resistance:
 7.5  (typical) at VCC = 2.7 V
 6.5  (typical) at VCC = 3.3 V
 6  (typical) at VCC = 5 V
 Switch current capability of 32 mA
 High noise immunity
 CMOS low power consumption
 TTL interface compatibility at 3.3 V
 Latch-up performance meets requirements of JESD78 Class I
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Enable input accepts voltages up to 5.5 V
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G66GW
40 C to +125 C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G66GV
40 C to +125 C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
74LVC1G66GM
40 C to +125 C
XSON6
plastic extremely thin small outline package; no leads;
6 terminals; body 1  1.45  0.5 mm
SOT886
74LVC1G66
NXP Semiconductors
Bilateral switch
Table 1.
Ordering information …continued
Type number
Package
Temperature range Name
Description
Version
74LVC1G66GF
40 C to +125 C
XSON6
plastic extremely thin small outline package; no leads;
6 terminals; body 1  1  0.5 mm
SOT891
74LVC1G66GN
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74LVC1G66GS
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G66GW
VL
74LVC1G66GV
V66
74LVC1G66GM
VL
74LVC1G66GF
VL
74LVC1G66GN
VL
74LVC1G66GS
VL
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
(
=
<
PQD
DDJ
Fig 1.
Logic symbol
;
Fig 2.
IEC logic symbol
=
<
(
9&&
Fig 3.
DDP
Logic diagram
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Bilateral switch
6. Pinning information
6.1 Pinning
/9&*
/9&*
<
=
*1'
9&&
<
9&&
=
QF
*1'
(
(
<
9&&
=
QF
*1'
(
DDJ
DDJ
7UDQVSDUHQWWRSYLHZ
7UDQVSDUHQWWRSYLHZ
DDG
Fig 4.
/9&*
Pin configuration
SOT353-1 and SOT753
Fig 5.
Pin configuration SOT886
Fig 6.
Pin configuration SOT891
and SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT353-1, SOT753 SOT886, SOT891, SOT1115 and SOT1202
Y
1
1
independent input or output
Z
2
2
independent output or input
GND
3
3
ground (0 V)
E
4
4
enable input (active HIGH)
n.c.
-
5
not connected
VCC
5
6
supply voltage
7. Functional description
Table 4.
Function table[1]
Input E
Switch
L
OFF-state
H
ON-state
[1]
H = HIGH voltage level; L = LOW voltage level
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Bilateral switch
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
[1]
VI
input voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
ISK
switch clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[2]
Min
Max
Unit
0.5
+6.5
V
0.5
+6.5
V
50
-
mA
-
50
mA
0.5
VCC + 0.5
V
VSW
switch voltage
enable and disable mode
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V
-
50
mA
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
Tamb = 40  C to +125 C
[3]
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3]
For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VSW
Conditions
[1]
switch voltage
Tamb
ambient temperature
t/V
input transition rise and
fall rate
Min
Typ
Max
Unit
1.65
-
5.5
V
0
-
5.5
V
0
-
VCC
V
40
-
+125
C
VCC = 1.65 V to 2.7 V
[2]
-
-
20
ns/V
VCC = 2.7 V to 5.5 V
[2]
-
-
10
ns/V
[1]
To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Y. In this case, there is no limit
for the voltage drop across the switch.
[2]
Applies to control signal levels.
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Bilateral switch
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
VCC = 1.65 V to 1.95 V
Typ[1]
40 C to +125 C Unit
Max
Min
Max
0.65VCC
-
-
0.65VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
0.7VCC
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
0.35VCC V
-
-
0.3VCC
-
0.3VCC V
-
0.1
5
-
100
A
II
input leakage pin E; VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
[2]
IS(OFF)
OFF-state
leakage
current
VCC = 5.5 V; see Figure 7
[2]
-
0.1
5
-
200
A
IS(ON)
ON-state
leakage
current
VCC = 5.5 V; see Figure 8
[2]
-
0.1
5
-
200
A
ICC
supply
current
VI = 5.5 V or GND;
VSW = GND or VCC;
VCC = 1.65 V to 5.5 V
[2]
-
0.1
10
-
200
A
ICC
additional
supply
current
pin E; VI = VCC  0.6 V;
VSW = GND or VCC; VCC = 5.5 V
[2]
-
5
500
-
5000
A
CI
input
capacitance
-
2.0
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
6.5
-
-
-
pF
CS(ON)
ON-state
capacitance
-
11
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 C.
[2]
These typical values are measured at VCC = 3.3 V.
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
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Bilateral switch
10.1 Test circuits
9&&
9&&
(
9,/
=
9,
(
9,+
<
,6
*1'
,6
92
=
<
*1'
9,
DDP
DDP
VI = VCC or GND and VO = GND or VCC.
Fig 7.
92
VI = VCC or GND and VO = open circuit.
Test circuit for measuring OFF-state leakage
current
Fig 8.
Test circuit for measuring ON-state leakage
current
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol
Parameter
RON(peak) ON resistance (peak)
RON(rail)
ON resistance (rail)
40 C to +85 C
Conditions
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
34.0
130
-
195

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
12.0
30
-
45

ISW = 12 mA; VCC = 2.7 V
-
10.4
25
-
38

ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
7.8
20
-
30

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
6.2
15
-
23

ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
8.2
18
-
27

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.1
16
-
24

ISW = 12 mA; VCC = 2.7 V
-
6.9
14
-
21

ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
6.5
12
-
18

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
5.8
10
-
15

ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
10.4
30
-
45

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.6
20
-
30

ISW = 12 mA; VCC = 2.7 V
-
7.0
18
-
27

ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
6.1
15
-
23

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
4.9
10
-
15

VI = GND to VCC; see Figure 9
VI = GND; see Figure 9
VI = VCC; see Figure 9
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Bilateral switch
Table 8.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol
RON(flat)
Parameter
40 C to +85 C
Conditions
ON resistance
(flatness)
40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
26.0
-
-
-

ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
5.0
-
-
-

ISW = 12 mA; VCC = 2.7 V
-
3.5
-
-
-

ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
2.0
-
-
-

ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
1.5
-
-
-

[2]
VI = GND to VCC
[1]
Typical values are measured at Tamb = 25 C and nominal VCC.
[2]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
PQD
521
ȍ
96:
9&&
(
9,+
<
=
9,
*1'
,6:
RON = VSW/ISW.
9,9
DDP
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 9.
Test circuit for measuring ON resistance
74LVC1G66
Product data sheet
Fig 10. Typical ON resistance as a function of input
voltage; Tamb = 25 C
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Bilateral switch
DDD
521
ȍ
DDD
521
ȍ
9,9
(1) Tamb = 125 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
Fig 11. ON resistance as a function of input voltage;
VCC = 1.8 V
DDD
9,9
521
ȍ
Fig 12. ON resistance as a function of input voltage;
VCC = 2.5 V
DDD
521
ȍ
9,9
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(4) Tamb = 40 C.
74LVC1G66
Product data sheet
9,9
(1) Tamb = 125 C.
Fig 13. ON resistance as a function of input voltage;
VCC = 2.7 V
Fig 14. ON resistance as a function of input voltage;
VCC = 3.3 V
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LVC1G66
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Bilateral switch
DDD
521
ȍ
9,9
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter
tpd
40 C to +85 C
Conditions
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
-
0.8
2.0
-
3.0
ns
VCC = 2.3 V to 2.7 V
-
0.4
1.2
-
2.0
ns
VCC = 2.7 V
-
0.4
1.0
-
1.5
ns
VCC = 3.0 V to 3.6 V
-
0.3
0.8
-
1.5
ns
-
0.2
0.6
-
1.0
ns
[2][3]
propagation delay Y to Z or Z to Y;
see Figure 16
VCC = 4.5 V to 5.5 V
ten
enable time
74LVC1G66
Product data sheet
40 C to +125 C Unit
Typ[1]
E to Y or Z; see Figure 17
[4]
VCC = 1.65 V to 1.95 V
1.0
5.3
12
1.0
15.5
ns
VCC = 2.3 V to 2.7 V
1.0
3.0
6.5
1.0
8.5
ns
VCC = 2.7 V
1.0
2.6
6.0
1.0
8.0
ns
VCC = 3.0 V to 3.6 V
1.0
2.5
5.0
1.0
6.5
ns
VCC = 4.5 V to 5.5 V
1.0
1.9
4.2
1.0
5.5
ns
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Rev. 9 — 15 January 2015
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NXP Semiconductors
Bilateral switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter
40 C to +85 C
Conditions
Min
tdis
disable time
40 C to +125 C Unit
Max
Min
Max
[5]
E to Y or Z; see Figure 17
VCC = 1.65 V to 1.95 V
1.0
4.2
10
1.0
13
ns
VCC = 2.3 V to 2.7 V
1.0
2.4
6.9
1.0
9.0
ns
VCC = 2.7 V
1.0
3.6
7.5
1.0
9.5
ns
VCC = 3.0 V to 3.6 V
1.0
3.4
6.5
1.0
8.5
ns
1.0
2.5
5.0
1.0
6.5
ns
VCC = 2.5 V
-
9.8
-
-
-
pF
VCC = 3.3 V
-
12.0
-
-
-
pF
VCC = 5.0 V
-
17.3
-
-
-
pF
VCC = 4.5 V to 5.5 V
power dissipation
capacitance
CPD
Typ[1]
[6]
CL = 50 pF; fi = 10 MHz;
VI = GND to VCC
[1]
Typical values are measured at Tamb = 25 C and nominal VCC.
[2]
tpd is the same as tPLH and tPHL
[3]
propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4]
ten is the same as tPZH and tPZL
[5]
tdis is the same as tPLZ and tPHZ
[6]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + {(CL + CS(ON)) VCC2  fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
{(CL + CS(ON))  VCC2  fo} = sum of the outputs.
11.1 Waveforms and test circuit
9,
90
<RU=LQSXW
*1'
W 3/+
W 3+/
92+
90
=RU<RXWSXW
92/
PQD
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Input (Y or Z) to output (Z or Y) propagation delays
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
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Bilateral switch
9,
(
90
*1'
W 3=/
W 3/=
9&&
<RU=
RXWSXW
/2:WR2))
2))WR/2:
90
9;
92/
W 3=+
W 3+=
<RU=
RXWSXW
+,*+WR2))
2))WR+,*+
92+
9<
90
*1'
VZLWFK
HQDEOHG
VZLWFK
GLVDEOHG
VZLWFK
HQDEOHG
PQD
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH  0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH  0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH  0.3 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
VOH  0.3 V
74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
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NXP Semiconductors
Bilateral switch
9(;7
9&&
9,
*
5/
92
'87
57
&/
5/
PQD
Test data is given in Table 11.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 18. Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
 2.0 ns
30 pF
1 k
open
GND
2VCC
2.3 V to 2.7 V
VCC
 2.0 ns
30 pF
500 
open
GND
2VCC
2.7 V
2.7 V
 2.5 ns
50 pF
500 
open
GND
6V
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF
500 
open
GND
6V
4.5 V to 5.5 V
VCC
 2.5 ns
50 pF
500 
open
GND
2VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
THD
total harmonic distortion
RL = 10 k; CL = 50 pF; fi = 1 kHz;
see Figure 19
Min
Typ
Max
Unit
VCC = 1.65 V
-
0.032
-
%
VCC = 2.3 V
-
0.008
-
%
VCC = 3.0 V
-
0.006
-
%
VCC = 4.5 V
-
0.001
-
%
VCC = 1.65 V
-
0.068
-
%
VCC = 2.3 V
-
0.009
-
%
VCC = 3.0 V
-
0.008
-
%
VCC = 4.5 V
-
0.006
-
%
RL = 10 k; CL = 50 pF; fi = 10 kHz;
see Figure 19
74LVC1G66
Product data sheet
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Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
f(3dB)
3 dB frequency response
RL = 600 ; CL = 50 pF;
see Figure 20
Min
Typ
Max
Unit
VCC = 1.65 V
-
135
-
MHz
VCC = 2.3 V
-
145
-
MHz
VCC = 3.0 V
-
150
-
MHz
VCC = 4.5 V
-
155
-
MHz
VCC = 1.65 V
-
 500
-
MHz
VCC = 2.3 V
-
 500
-
MHz
VCC = 3.0 V
-
 500
-
MHz
VCC = 4.5 V
-
 500
-
MHz
VCC = 1.65 V
-
200
-
MHz
VCC = 2.3 V
-
350
-
MHz
VCC = 3.0 V
-
410
-
MHz
VCC = 4.5 V
-
440
-
MHz
VCC = 1.65 V
-
46
-
dB
VCC = 2.3 V
-
46
-
dB
VCC = 3.0 V
-
46
-
dB
VCC = 4.5 V
-
46
-
dB
VCC = 1.65 V
-
37
-
dB
VCC = 2.3 V
-
37
-
dB
VCC = 3.0 V
-
37
-
dB
VCC = 4.5 V
-
37
-
dB
VCC = 1.65 V
-
69
-
mV
VCC = 2.3 V
-
87
-
mV
VCC = 3.0 V
-
156
-
mV
VCC = 4.5 V
-
302
-
mV
RL = 50 ; CL = 5 pF; see Figure 20
RL = 50 ; CL = 10 pF; see Figure 20
iso
isolation (OFF-state)
RL = 600 ; CL = 50 pF; fi = 1 MHz;
see Figure 21
RL = 50 ; CL = 5 pF; fi = 1 MHz;
see Figure 21
Vct
crosstalk voltage
74LVC1G66
Product data sheet
between digital input and switch;
RL = 600 ; CL = 50 pF; fi = 1 MHz;
tr = tf = 2 ns; see Figure 22
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol
Parameter
Conditions
Qinj
charge injection
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ;
fi = 1 MHz; RL = 1 M; see Figure 23
Min
Typ
Max
Unit
VCC = 1.8 V
-
3.3
-
pC
VCC = 2.5 V
-
4.1
-
pC
VCC = 3.3 V
-
5.0
-
pC
VCC = 4.5 V
-
6.4
-
pC
VCC = 5.5 V
-
7.5
-
pC
11.3 Test circuits
9&&
9&&
(
9,+
5/
<=
IL
—)
=<
92
ȍ
'
&/
DDP
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 19. Test circuit for measuring total harmonic distortion
9&&
(
9,+
—)
IL
9&&
<=
5/
=<
ȍ
92
&/
G%
DDP
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
74LVC1G66
Product data sheet
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Bilateral switch
9&&
9&&
(
5/ 9,/
—)
IL
9&&
5/
<=
=<
92
&/ G%
ȍ
DDP
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
9&&
(
<=
*
ORJLF
LQSXW
ȍ
=<
92
5/
ȍ
9&&
&/
9&&
DDP
Fig 22. Test circuit for measuring crosstalk between digital input and switch
9&&
(
5JHQ
*
ORJLF
LQSXW
<=
=<
92
5/
0ȍ
9JHQ
&/
Q)
DDP
ORJLF
LQSXW(
RII
RQ
RII
92
ǻ92
DDP
Qinj = VO  CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
74LVC1G66
Product data sheet
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12. Package outline
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Product data sheet
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Product data sheet
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Rev. 9 — 15 January 2015
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NXP Semiconductors
Bilateral switch
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74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LVC1G66
NXP Semiconductors
Bilateral switch
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74LVC1G66
Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LVC1G66
NXP Semiconductors
Bilateral switch
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Product data sheet
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Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74LVC1G66
NXP Semiconductors
Bilateral switch
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74LVC1G66
Product data sheet
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© NXP Semiconductors N.V. 2015. All rights reserved.
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13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
TTL
Transistor-Transistor Logic
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
DUT
Device Under Test
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G66 v.9
20150115
Product data sheet
-
74LVC1G66 v.8
Modifications:
74LVC1G66 v.8
Modifications:
•
SOT886 (XSON6) package outline drawing modified.
20111202
•
Product data sheet
-
74LVC1G66 v.7
Legal pages updated.
74LVC1G66 v.7
20100730
Product data sheet
-
74LVC1G66 v.6
74LVC1G66 v.6
20070827
Product data sheet
-
74LVC1G66 v.5
74LVC1G66 v.5
20070807
Product data sheet
-
74LVC1G66 v.4
74LVC1G66 v.4
20040413
Product specification
-
74LVC1G66 v.3
74LVC1G66 v.3
20021115
Product specification
-
74LVC1G66 v.2
74LVC1G66 v.2
20020529
Product specification
-
74LVC1G66 v.1
74LVC1G66 v.1
20011030
Product specification
-
-
74LVC1G66
Product data sheet
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC1G66
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 15 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
23 of 25
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NXP Semiconductors
Bilateral switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet
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NXP Semiconductors
Bilateral switch
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.2
11.3
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms and test circuit . . . . . . . . . . . . . . . 10
Additional dynamic characteristics . . . . . . . . . 12
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information. . . . . . . . . . . . . . . . . . . . . 24
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 January 2015
Document identifier: 74LVC1G66