UM2002 Bidirectional Voltage Level Translator for Open-Drain and Push-Pull Applications UM2002S8 SOP8 UM2002U8 TSSOP8 General Description The UM2002 is a bidirectional voltage level translator operational from 1.0V to 3.6V (Vref(A)) and 1.8V to 5.5V (Vref(B)), which allows bidirectional voltage translations between 1.0V and 5V without the need for a direction pin in open-drain or push-pull applications. Bit widths ranging from 1-bit or 2-bit are offered for level translation application with transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a pull-up of 197Ω. The translators provide excellent ESD protection to lower voltage devices, and at the same time protect less ESD-resistant devices. Applications Features SPI, MICROWIRE and I2C Level Translation Low-Voltage ASIC Level Translation Smart Card Readers Cell-Phone Cradles Portable POS Systems Portable Communication Devices Low-Cost Serial Interfaces Cell-Phones GPS Telecommunications Equipment Consumer Electronics Household Appliances Provides Bidirectional Voltage Translation with No Direction Pin Less than 1.5ns Maximum Propagation Delay Allows Voltage Level Translation between: 1). 1.0V Vref(A) and 1.8V, 2.5V, 3.3V or 5V Vref(B) 2). 1.2V Vref(A) and 1.8V, 2.5V, 3.3V or 5V Vref(B) 3). 1.8V Vref(A) and 3.3V or 5V Vref(B) 4). 2.0V Vref(A) and 5V Vref(B) 5). 3.3V Vref(A) and 5V Vref(B) Low 3.5Ω ON-State Connection between Input and Output Ports Provides Less Signal Distortion 5V Tolerant I/O Ports to Support Mixed-Mode Signal Operation High-Impedance An and Bn Pins for EN=LOW Lock-up Free Operation Flow through Pinout for Ease of Printed-Circuit Board Trace Routing ESD Protection Exceeds: 4kV HBM per JESD22-A114 200V MM per JESD22-A115 1000V CDM per JESD22-C101 Packages Offered: SOP8, TSSOP8 ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 1/12 UM2002 Pin Configurations Top View (Top View) 8 GND 1 8 EN VREFA 2 7 VREFB A1 3 6 B1 7 5 4 5 UM2002 S8 XX 1 A2 6 2 3 4 B2 XX: Week Code UM2002S8 SOP8 (Top View) 1 GND 1 8 EN 2 VREFA 2 7 VREFB 3 A1 3 6 B1 4 A2 4 5 B2 8 7 2002U8 XX 6 5 XX: Week Code UM2002U8 TSSOP8 Pin Description Pin Number Symbol Function 1 2 GND VREFA 3,4 A1,A2 5,6 B1,B2 7 VREFB 8 EN Ground (0V) Low-voltage side reference supply voltage for An Low-voltage side; connected to VREFA through a pull-up resistor High-voltage side; connected to VREFB through a pull-up resistor High-voltage side reference supply voltage for Bn Switch enable input; connected to VREFB and pulled-up through a high resistor Ordering Information Part Number Packaging Type Marking Code UM2002S8 SOP8 UM2002S8 UM2002U8 TSSOP8 2002U8 Shipping Qty 2500pcs/13Inch Tape & Reel 3000pcs/13Inch Tape & Reel ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 2/12 UM2002 Absolute Maximum Ratings (Note 1) Over operating free-air temperature range (unless otherwise noted) Symbol Parameter Vref(A) Reference Voltage (A) Vref(B) Reference Voltage (B) VI VI/O Value -0.5 to +6 -0.5 to +6 Unit V V Input Voltage -0.5(Note 2) to +6 V Voltage on an input/output pin -0.5(Note 2) to +6 V +128 mA -50 -65 to +150 mA °C Ich Channel Current (DC) IIK Tstg Input Clamp Current Storage Temperature VI＜0V Note 1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Note 2: The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed. Recommended Operating Conditions Symbol Parameter Conditions Min Max Unit VI/O Voltage on an input/output pin An, Bn 0 5.5 V Vref(A) (Note 3) Reference Voltage (A) VREFA 0 5.4 V Vref(B) (Note 3) Reference Voltage (B) VREFB 0 5.5 V VI(EN) Input Voltage on pin EN 0 5.5 V Isw(pass) Pass Switch Current 64 mA Tamb Ambient Temperature +85 °C Operating in free-air -40 Note 3: Vref(A) ≤ Vref(B) −1 V for best results in level shifting applications. ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 3/12 UM2002 Electrical Characteristics Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VIK IIH Ci(EN) Parameter Conditions Input Clamping Voltage HIGH-level Input Current Input Capacitance on pin EN Off-state input/output capacitance On-state input/output capacitance II = −18mA; VI(EN) = 0V VI= 5V; VI(EN) = 0V VI= 0V or 3V Min Typ (Note 4) 12 Max Unit -1.2 V 5 μA pF An, Bn; VO= 0V or 3V ; 10 12 pF VI(EN) = 0V An, Bn; 12.5 Cio(on) VO= 0V or 3V ; 8 pF (Note 5) VI(EN) = 3V An, Bn; VI = 0V; IO = 64mA; 1 2.5 5.0 ON-state VI(EN) = 4.5V(Note 7) Ron resistance Ω An, Bn; (Note 6) VI = 2.4V; IO = 15mA; 4.5 7.5 VI(EN) = 4.5V Note 4: All typical values are at Tamb = 25°C. Note 5: Not production tested, maximum value based on characterization data of typical parts. Note 6: Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two terminals. Note 7: Guaranteed by design. Cio(off) ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 4/12 UM2002 Switching Characteristics (translating down) Over recommended operating free-air temperature range(unless otherwise noted). Values guaranteed by design. CL=50pF CL=30pF CL=15pF Test Symbol Parameter Unit Conditions Min Max Min Max Min Max VI(EN) = 3.3V; VIH = 3.3V; VIL = 0V; VM =1.15V(see Figure 1). tPLH tPHL LOW to HIGH propagation delay HIGH to LOW propagation delay 0 3.5 0 2.7 0 2.2 ns 0 3.5 0 3.0 0 2.3 ns from (input) Bn to (output) An. VI(EN) =2.5V; VIH = 2.5V; VIL = 0V; VM = 0.75V (see Figure 1). tPLH tPHL LOW to HIGH propagation delay HIGH to LOW propagation delay 0 3.5 0 2.7 0 2.2 ns 0 4.0 0 3.0 0 2.3 ns from (input) Bn to (output) An. Switching Characteristics (translating up) Over recommended operating free-air temperature range(unless otherwise noted). Values guaranteed by design. CL=50pF CL=30pF CL=15pF Test Symbol Parameter Unit Conditions Min Max Min Max Min Max VI(EN) = 3.3V; VIH = 2.3V; VIL = 0V; VTT = 3.3V; VM = 1.15V; RL = 300Ω(see Figure 1). tPLH tPHL LOW to HIGH propagation delay HIGH to LOW propagation delay 0 3.35 0 2.5 0 2.0 ns 0 4.35 0 3.25 0 2.4 ns from (input) An to (output) Bn. VI(EN) =2.5V; VIH = 1.5V; VIL = 0V; VTT = 2.5V; VM = 0.75V; RL = 300Ω (see Figure 1). tPLH tPHL LOW to HIGH propagation delay HIGH to LOW propagation delay 0 3.35 0 2.5 0 2.0 ns 0 4.5 0 3.5 0 2.5 ns from (input) An to (output) Bn. ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 5/12 UM2002 VIH VTT input VM VM VIL RL S1 from output under test S2(OPEN) CL VOH output VM VM VOL a. Load circuit B. Timing diagram; high-impedance scope probe used S1 = translating up; S2 = translating down. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 5 ns; tf ≤ 5 ns. The outputs are measured one at a time, with one transition per measurement. Fig 1. Load circuit for outputs Applications Information Detail Description The UM2002 is a bidirectional voltage level translator operational from 1.0V to 3.6V (Vref(A)) and 1.8V to 5.5V (Vref(B)), which allows bidirectional voltage translations between 1.0V and 5V without the need for a direction pin in open-drain or push-pull applications. When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. Assuming the higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is limited to the voltage set by Vref(A). When the An port is HIGH, the Bn port is pulled to the drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The EN input circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during power-up or power-down, EN must be LOW. All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 6/12 UM2002 Enable and Disable Vpu(D)=3.3V(1) 200kΩ Vref(1)=1.8V (1) UM2002 8 EN VREF1 2 RPU 7 RPU RPU VREF2 RPU Vcc A1 I/O I2C-BUS MASTER A2 I/O 3 4 GND SW SW 6 5 Vcc B1 I/O I2C-BUS DEVICE B2 I/O GND 1 GND (1) The applied voltages at Vref(1) and Vpu(D) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation. Fig 2. Typical application circuit (switch always enabled) Vpu(D)=3.3V(1) 3.3V enable signal(1) on off 200kΩ Vref(1)=1.8V (1) UM2002 8 EN VREF1 2 RPU Vcc A1 I/O GND RPU RPU I/O I2C-BUS MASTER 7 RPU VREF2 A2 3 4 SW SW 6 5 B1 B2 Vcc I/O I2C-BUS DEVICE I/O GND 1 GND (1) In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(1) should be such that Vbias(ref)(2) is at least 1 V higher than Vref(1) for best translator operation. Fig 3. Typical application circuit (switch enable control) ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 7/12 UM2002 5V 1.8V 1.5V 1.2V 1.0V 200kΩ UM20XX EN totem pole or open-drain I/O VREFB VREFA VCORE A1 SW B1 CPU I/O VCC CHIPSET I/O A2 SW B2 3.3V A3 A4 A5 A6 SW SW SW SW B3 B4 VCC CHIPSET I/O B5 B6 ... An SW Bn GND Fig 4. Bidirectional translation to multiple higher voltage levels Bidirectional translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled to HIGH side Vpu(D) through a pull-up resistor (typically 200kΩ). This allows VREFB to regulate the EN input. A filter capacitor on VREFB is recommended. The master output driver can be totem pole or open-drain (pull-up resistors may be required) and the slave device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu(D)). However, if either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no direction control is needed. The reference supply voltage (Vref(A)) is connected to the processor core power supply voltage. When VREFB is connected through a 200kΩ resistor to a 3.3V to 5.5V Vpu(D) power supply, and Vref(A) is set between 1.0V and (Vpu(D) −1V), the output of each An has a maximum output voltage equal to VREFA, and the output of each Bn has a maximum output voltage equal to Vpu(D). ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 8/12 UM2002 Application operating conditions Refer to Figure 4 Symbol Parameter Vref(B) VI(EN) Vref(A) Isw(pass) Iref Reference Bias Voltage (B) Input Voltage on pin EN Reference Voltage (A) Pass Switch Current Reference Current Conditions Transistor Operating Tamb Ambient Temperature in free-air Note 8: All typical values are at Tamb = 25 °C. Min Vref(A) + 0.6 Vref(A) + 0.6 0 -40 Typ (Note 8) 2.1 2.1 1.5 14 5 Max Unit 5 5 4.4 V V V mA μA +85 °C Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15mA. This ensures a pass voltage of 260mV to 350mV. If the current through the pass transistor is higher than 15mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15mA, the pull-up resistor value is calculated as: RPU V pu( D ) 0.35V 0.015 A The table below summarizes resistor reference voltages and currents at 15mA, 10mA, and 3mA. The resistor values shown in the +10 % column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less. The external driver must be able to sink the total current from the resistors on both sides of the UM2002 device at 0.175V, although the 15mA only applies to current flowing through the UM2002 device. Pull-up resistor values Calculated for VOL = 0.35V; assumes output driver VOL = 0.175V at stated current. Pull-up resistor value (Ω) 15mA 10mA 3mA Vpu(D) +10 % +10 % +10 % Nominal Nominal Nominal (Note 9) (Note 9) (Note 9) 5V 310 341 465 512 1550 1705 3.3V 197 217 295 325 983 1082 2.5V 143 158 215 237 717 788 1.8V 97 106 145 160 483 532 1.5V 77 85 115 127 383 422 1.2V 57 63 85 94 283 312 Note 9: +10 % to compensate for VCC range and resistor tolerance. ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 9/12 UM2002 Package Information UM2002S8 SOP8 Outline Drawing c L D E E1 Symbol 1 2 θ e Top View A A2 End View A1 b Side View A A1 A2 b c D E E1 e L θ DIMENSIONS MILLIMETERS Min Max 1.350 1.750 0.100 0.250 1.350 1.550 0.33 0.51 0.170 0.250 4.700 5.100 3.800 4.000 5.800 6.200 1.270 (BSC) 0.400 1.270 0° 8° INCHES Min Max 0.053 0.069 0.004 0.010 0.053 0.061 0.013 0.020 0.006 0.010 0.185 0.200 0.150 0.157 0.228 0.244 0.050 (BSC) 0.016 0.050 0° 8° 4.95 1.30 Land Pattern 1.27 0.50 NOTES: 1. Compound dimension: 4.90×3.90； 2. Unit: mm; 3. General tolerance ±0.05mm unless otherwise specified; 4. The layout is just for reference. Tape and Reel Orientation UM2002 S8 XX ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 10/12 UM2002 UM2002U8: TSSOP8 Outline Drawing E E1 D INDEX Φ10.6±0.05 0.05±0.05 DEP e b L2 A A2 A3 θ2 L 0.10 θ1 A1 L1 θ3 DIMENSIONS MILLIMETERS INCHES Symbol Min Max Min Max A 1.200 0.048 A1 0.050 0.150 0.002 0.006 A2 0.900 1.050 0.036 0.042 A3 0.340 0.540 0.014 0.022 b 0.200 0.280 0.008 0.011 c 0.100 0.190 0.004 0.008 D 2.830 3.030 0.113 0.121 E 6.200 6.600 0.248 0.264 E1 4.300 4.500 0.172 0.180 e 0.650BSC 0.026BSC L 0.450 0.750 0.018 0.030 L1 1.000REF 0.040REF L2 0.250BSC 0.010BSC θ1 0° 8° 0° 8° θ2 10° 14° 10° 14° θ3 10° 14° 10° 14° Land Pattern 5.75 1.40 0.35 NOTES: 1. Compound dimension: 2.93×4.40; 2. Unit: mm; 3. General tolerance ±0.05mm unless otherwise specified; 4. The layout is just for reference. 0.65 Tape and Reel Orientation 2002U8 XX ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 11/12 UM2002 IMPORTANT NOTICE The information in this document has been carefully reviewed and is believed to be accurate. Nonetheless, this document is subject to change without notice. Union assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or organization of any update. Union reserves the right to make changes, at any time, in order to improve reliability, function or design and to attempt to supply the best product possible. Union Semiconductor, Inc Add: Unit 606, No.570 Shengxia Road, Shanghai 201210 Tel: 021-51093966 Fax: 021-51026018 Website: www.union-ic.com ________________________________________________________________________ http://www.union-ic.com Rev.05 Nov.2014 12/12