BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 Data Sheet SHANGHAI BELLING CO.,LTD BL55076 Universal LCD Driver & Controller DOCNO: BLSPEC55076E1.1 DEPT: CBU UPDATE: 2005.11 1 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 BL55076 LCD Driver for 160 Display Units BL55076 General Description The BL55076 is a peripheral device, which interfaces to almost any Liquid Crystal Display (LCD) having low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four back planes and up to 40 segments and can easily be cascaded for larger LCD applications. The BL55076 is compatible with most microprocessors/micro controllers and communicates via a two-line bi-directional IIC -bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware sub addressing and by display memory switching (static and duplex drive modes). Features • • • • • Single-chip LCD controller/driver Selectable back plane drive figuration: static or2, 3or 4backplane multiplexing Selectable display bias configuration: static,1/2 or 1/3 Internal LCD bias generation with voltage-follower buffers 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements • • • • • • • • 40×4-bit RAM for display data storage • • • • • • IIC -bus interface • • • Space-saving 64 lead plastic very small outline package (LQFP64) Auto-incremented display data loading across device sub address boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes LCD and logic supplies may be separated 2.5 to 6V power supply range Low power consumption Power saving mode for extremely low power consumption in battery-operated and telephone applications TTL/CMOS compatible Compatible with any 4-bit, 8-bit or 16-bit microprocessors/micro controllers May be cascaded for large LCD applications (up to 1536 segments possible) Ascendable with the 24segment LCD driver BL55066 Optimized pinning for single plane wiring in both single and multiple BL55076 applications No external components required (even in multiple device applications) Manufactured in silicon gate CMOS process. Application Telephone、Power meter、Toy、Clock… 2 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 BL55076 Pin Assignment Pin Description Pin No. Pin name Function 10 11 12 SDA SCL SYNC 13 14 15 16-18 19 20 21 25-28 CLK Vdd OSC A0、A1、A2 SA0 Vss Vlcd BP0、BP2、BP1、BP3 29-32、34-37、49-64、2-7 S0——S39 1、8、9、22、23、24、33、 48 NC Serial data input Clock input Cascade synchronization clock External oscillator input Plus Power terminal Oscilator control Subaddress Select Slave address bit 0 Minus power terminal LCD power source Common terminal driving output Segment terminal driving output Unused FUNCTIONAL DESCRIPTION Functional Circuit The BL55076 is a versatile peripheral device designed to interface any microprocessor to a wide variety of LCD is. It can directly drive any static or multiplexed LCD containing up to 3 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 4 back planes and up to 40 segments. The display configurations possible with the BL55076 depend on the number of active back plane outputs required; a selection of display configurations is given in Table 2. All of the display configurations given in Table 2 can be implemented in the typical system shown in Fig.2. The host microprocessor/micro controller maintains the two-line bus communication channel with the BL55076. The internal oscillator is selected by tying OSC (pin 15) to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and to the LCD panel chosen for the application. Table 2 Fig 2 Display Ram The display RAM is a static 40×4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the ‘on’ state of the corresponding LCD segment; similarly, a logic 0 indicates the ‘off ’ state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the ,individual bits of a RAM word and the back plane outputs. The first RAM column corresponds to the 40 segments operated with respect to back plane BP0 (see Fig.3).In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. When display data are transmitted to the BL55076 the display bytes received are stored in the display RAM according to the selected LCD drive mode. To illustrate the filling order, an example of a 7 segment numeric display showing all drive modes is given in Fig.4; the RAM filling organization depicted applies equally to other LCD types. With reference to Fig.4, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in 4 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. Fig 3 Fig 4 IIC-BUS DESCRIPTION The IIC-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 5 Shanghai Belling Corp., Ltd BL55076 zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). System configuration A device generating a message is a ‘transmitter’, a device receiving a message is a ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 6 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 Fig 5 BL55076 IIC-bus controller The BL55076 acts as an IIC-bus slave receiver. It does not initiate IIC-bus transfers or transmit data to an IIC-bus master receiver. The only data output from the BL55076 are the acknowledge signals of the selected devices. Device selection depends on the IIC-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally left open-circuit or tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are left open-circuit or tied to VSS or VDD according to a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. In the power-saving mode it is possible that the BL55076 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the BL55076 forces the SCL line LOW until its internal operations are completed. This is known as the ‘clock synchronization feature’ of the IIC-bus and serves to slow down fast transmitters. Data loss does not occur. Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. IIC-bus protocol Two IIC-bus slave addresses (0111000 and 0111001) are reserved for BL55076. The least-significant bit of the slave address that a BL55076 will respond to is defined by the level tied at its input SA0 (pin 19). Therefore, two types of BL55076 can be distinguished on the same IIC-bus which allows: 1. Up to 16 BL55076s on the same IIC-bus for very large LCD applications 2. The use of two types of LCD multiplex on the same IIC-bus. The IIC-bus protocol is shown in Fig.15. The sequence is initiated with a START condition (S) from the IIC-bus master which is followed by one of the two BL55076 slave addresses available. All BL55076s with the corresponding SA0 level acknowledge in parallel the slave address but all BL55076s with the alternative SA0 level ignore the whole IIC-bus transfer. After acknowledgement, one or more command bytes (m) follow which define the status of the addressed BL55076s. The last command byte is tagged with a cleared most-significant bit, the continuation bit C. The command bytes are also acknowledged by all 7 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 addressed BL55076s on the bus. After the last command byte, a series of display data bytes (n) may follow. These display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data are directed to the intended BL55076 device. The acknowledgement after each byte is made only by the (A0, A1, A2) addressed BL55076. After the last display byte, the IIC-bus master issues a STOP condition (P). Command decoder The command decoder identifies command bytes that arrive on the IIC-bus. All available commands carry a continuation bit C in their most-significant bit position (see Fig.6). When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If the bit is reset, it indicates the last command byte of the transfer. Further bytes will be regarded as display data. The five commands available to the BL55076 are defined in Table 5. Fig 6 8 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 Table 5 Table 6 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the BL55076 and coordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. Cascaded operation In large display configurations, up to 16 BL55076s can be distinguished on the same IIC-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable IIC-bus slave address (SA0). It is also possible to cascade up to 16 BL55076s. When cascaded, several BL55076s are synchronized so that they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the outputs of only one device need to be through-plated to the backplane electrodes of the display. The other BL55076s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (Fig.7). The SYNC line is provided to maintain the correct synchronization between all cascaded BL55076s. This synchronization is guaranteed after the power-on reset. The only time that 9 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when BL55076s with differing SA0 levels are cascaded). SYNC is organized as an input/output pin; the output section being realized as an open-drain driver with an internal pull-up resistor. A BL55076 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first BL55076 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the BL55076 are shown in Fig.18. The waveforms are identical with the parent device BL55076. Cascade ability between BL55066s and BL55076s is possible, giving cost effective LCD applications. 10 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 Fig 8 11 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 BL55076 Absolute Maximum Rating Parameter Symbol MIN. MAX. Unit Supply Voltage VDD －0.5 +7.0 V LCD supply voltage VLCD VDD－ 7.0 VSS－ 0.5 VDD V VDD+0.5 V Input voltage（SCL、SDA、A0～ VI1 A2、OSC、CLK、 SYNC 、SA0） Output（S0～S23、BP0～BP3） VO VLCD－0.5 VDD+0.5 V DC input current ±II -20 +20 mA DC output current ±IO -25 +25 mA +50 mA - 400 mW VDD、VSS or VLCD current Power dissapation per package ±IDD、±ISS、 ±ILCD Ptot -50 Power dissapation per output PO - 100 mW Storage temperature Tatg －65 +150 ℃ Table 16 DC Characteristic Parameter Symbol Min Typ Max Unit Operating supply voltage VDD 2.5 - 6 V LCD supply voltage VLCD VDD－6 - V Operating supply current（Normal mode） ，fLCD=200kHz （1） IDD - 25 VDD－ 2.5 90 μΑ Power saving mode supplycurrent，VDD=3.5V，VLCD=0V，fCLK= 35kHz 1） Logic ILP - 12 40 μΑ VIL VSS - 0.3 VDD V VIH1 0.7VDD - VDD V Low level output voltage（IO=0mA） VOL - - 0.05 V High level output voltage（IO=0mA） VOH - - V - - mA Low level input voltage High level input voltage SYNC ,SA0,OSC,A0 to A2） （ SDA,SCL, CLK, Low level output current（CLK，SYNC） ，VOL=1V, VDD=5V IOL1 VDD－ 0.05 1 High level output current（CLK），VOH=4V, VDD=5V IOH - - -1 mA Low level output current（SDA，SCL） ，VOL=0.4V, VDD=5V IOL2 3 - - mA Leakage current（SA0，A0～A2，CLK，SCL，SDA）， VI=Vss or VDD ±IL1 -1 - +1 μΑ Leakage current（OSC），VI=VDD ±I12 -1 - +1 μΑ Pull down current（A0,A1,A2,OSC）VI=1V; VDD=5V Ipd 15 50 150 μΑ Pull up resistor（SYNC） RSYNC 15 25 60 kΩ Powron reset level （2） VREF - 1.3 2 V 12 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 BL55076 Tolerable spike width on bus tSW - - 100 ns Input capacitance（3） CI - - 7 pF DC voltage component（BP0～BP3），CBP=35nF ±VBP -20 - ＋20 mV DC voltage component（S0～S23），CS=5nF ±VS -20 - ＋20 mV Output impedance（BP0～BP3） ，VLCD=VDD-5V （4） RBP - 1 5 kΩ Output impedance（S0～S23），VLCD=VDD-5V （4） RS - 3 7 kΩ LCD output Table 17 Notes 1. Outputs open; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 2. Resets all logic when VDD < Vref. 3. Periodically sampled, not 100% tested. 4. Outputs measured one at a time. Ta=25oC AC Characteristic Parameter Symbol Min Typ Max Unit Oscilator frequency（Normal mode）VDD=5V fclk 125 200 315 kHz Oscilator frequency（Power saving mode）VDD=3.5V fclkP 21 31 48 kHz CLK high time tclkH 1 - - μs CLK low time tclkL 1 - - μs SYNC propagation delay tPSYNC - - 400 ns SYNC low time t 1 - - μs Driver delays with load, VLCD=VDD-5V tPLCD - - 30 μs Bus free time tBUF 4.7 - - μs START condition hold time tHD;STA 4.0 - - μs START condition setup time tSU;STA 4.7 - - μs SCL low time tLOW 4.7 - - μs SCL high time tHIGH 4.0 - - μs SCL/SDA rise timr tr - - 1 μs SCL/SDA fall time tf - - 0.3 μs Line capacitor CB - - 400 pF Data setup time tSU;DAT 250 - - ns Data hold time tHD;DAT 0 - - μs SYNCL IIC-bus 13 BL55076 Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 STOP condition setup time tSU;STO 4.0 Table 18 Notes 1. All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD. 2. At fCLK < 125 kHz, I2C-bus maximum transmission speed is derated. Fig 9 14 - - μs Shanghai Belling Corp., Ltd zip: 200233 Tel: 86-021-64850700 Fax: 86-021-64855865 BL55076 9 Package Outlines LQFP64(10x10) Unit mm(tolerance) D 10.0(0.1) E 12.0(0.15) e 0.5 b 0.22(0.05) 15 f 1.25(0.2) m 1.0 n 0.6(0.15)