BL9193

BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
FEATURES
Ultra-low Noise for RF Application
Ultra-Fast Response in Line/Load
Transient
Quick Start-Up (Typically 50µS)
<0.01µA
Standby
Current
When
Shutdown.
Low Dropout:[email protected]
Wide Operating Voltage Ranges:2V to
6V
TTL-logic-Controlled Shutdown Input
Low Temperature Coefficient
Current Limiting Protection
Thermal Shutdown Protection
Only 1µF Output Capacitor Required for
Stability
High Power Supply Rejection Ratio
Custom Voltage Available
Fast output discharge
Available in 5-Lead SOT-23 and SC-70
Package
APPLICATIONS
Cellular and Smart Phones
Battery-Powered Equipment
Laptop, Palmtops,Notebook Computers
ORDERING INFORMATION
Hand-Held Instruments
PCMCIA Cards
MP3/MP4/MP5 Players
Portable Information Appliances
DESCRIPTION
The BL9193 is designed for portable RF and
wireless applications with demanding performance and space requirements. The BL9193
performance is optimized for battery-powered
systems to deliver ultra low noise and low
quiescent current. A noise bypass pin is
available for further reduction of output noise.
Regulator ground current increases only
slightly in dropout, further prolonging the
battery life. The BL9193 also works with lowESR ceramic capacitors, reducing the
amount of board space necessary for power
applications, critical in hand-held wireless
devices. The BL9193 consumes less than
0.01µA in shutdown mode and has fast turnon time less than 50µs. The other features
include ultra low dropout voltage, high output
accuracy, current limiting protection, and high
ripple rejection ratio. Available in the 5-lead of
SC-70, SOT-23 packages.
TYPICAL APPLICATION
BL9193 XX X X X XXX
Package:
RN: SOT-23-5
URN: SC-70-5
Features
P: Standard (default, lead free)
C: Customized
Enable Option:
A: active high with internal 8 MΩ pull down
B: active high with external pull down
C: active low with internal 2 MΩ pull up
D: active low with external pull up
Output Voltage Accuracy
A: ±1%
B: ±2%
VIN
1
C1
1uF
2
Chip
Enable
VIN
VOUT
5
VOUT
C2
1uF
GND
BL9193
3
EN
BP
4
C3
22nF
Application hints:
≥
Output capacitor (C2 2.2uF) is recommended
in BL9193-1.2V BL9193-1.5V BL91931.8V application to assure the stability of circuit.
,
,
Output Voltage:
12:1.2V 15:1.5V 18:1.8V 25:2.5V
28:2.8V 30:3.0V 33:3.3V
CT: custom fixed output (50mV step)
AD: Adjustable
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Absolute Maximum Rating
Input Supply Voltage (VCC)
EN Input Voltage
Output Voltage
BP Voltage
Output Current
(Note 1)
-0.3V to +6V
-0.3V to +Vin
-0.3V to Vin+0.3V
-0.3V to +6V
300mA
Maximum Junction Temperature
125°C
(Note2)
Operating Temperature Range
-40°C to 85°C
Storage Temperature Range
-65°C to 125°C
Lead Temperature (Soldering, 10s)
300°C
Package Information
Thermal Resistance (Note 4):
Package
SOT23-5
SC70-5
SOT23
SOT2323-5/SC70
SC7070-5
TOP VIEW
VIN
1
5
Part Number
3
4 BP/FB
Top Mark
Temp Range
(Note3)
BL9193-12BA
CAYW
BL9193-15BA
CBYW
-40°C to +85°C
BL9193-18BA
CCYW
-40°C to +85°C
BL9193-25BA
CDYW
-40°C to +85°C
BL9193-28BB
CEYW
-40°C to +85°C
BL9193-30BA
CFYW
-40°C to +85°C
BL9193-33BA
CGYW
-40°C to +85°C
BL9193-12BB
CHYW
-40°C to +85°C
BL9193-28BA
CIYW
-40°C to +85°C
BL9193-ADBA
CJYW
-40°C to +85°C
Y
Year
9
2009
A
2010
B
2011
C
2012
D
2013
A
1
…
…
Y
25
Z
26
a
27
W
Week
ӨJC
130°C/W
170°C/W
MARKING
GND 2
EN
VOUT
ӨJA
250°C/W
333°C/W
-40°C to +85°C
…
…
y
51
z
52
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: The BL9193 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C
to 85°C operating temperature range are assured by design, characterization and correlation with statistical
process controls.
Note 3: Y: Year of manufacturing W: Week of manufacturing
Note 4: Thermal Resistance is specified with approximately 1 square of 1 oz copper.
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Pin Description
PIN
1
2
NAME
VIN
GND
3
EN
4
5
BP/FB
VOUT
FUNCTION
Power Input Voltage.
Ground.
Chip Enable Pin with four options.
A: active high with internal 8 MΩ pull down
B: active high with external pull down
C: active low with internal 2 MΩ pull up
D: active low with external pull up
Reference Noise Bypass. FB pin for adjustable version.
Output Voltage.
Block Diagram
BL9193 XX XA
BL9193 XX XC
BL9193 XX XB
PPMIC BU
BL9193 Rev 2.2
1/2011
BL9193 XX XD
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Electrical Characteristics (Note 5)
℃
(VIN=3.6V, EN=VIN, CIN=COUT=1µF, CBP=22nF, TA=25 , unless otherwise noted.)
Parameter
Symbol
Conditions
MIN
TYP
Input Voltage
VIN
2
Output Voltage Accuracy
-1
VIN=3.6V,
∆VOUT
(Note 6)
IOUT=1mA
-2
Current Limit
ILIM
400
430
RLOAD=1Ω
Quiescent Current
IQ
VEN>1.2V, IOUT=0mA
90
IOUT=200mA,
130
VOUT=2.8V
Dropout Voltage
VDROP
IOUT=300mA,
210
VOUT=2.8V
VIN=3.6V to 5.5V
(Note 7)
∆VLINE
0.05
Line Regulation
IOUT=1mA
(Note 8)
∆VLOAD
1mA<IOUT<300mA
Load Regulation
(Note 9)
Output Voltage
IOUT=1mA
±60
TCVOUT
Temperature Coefficient
Standby Current
ISTBY
VEN=GND,Shutdown
0.01
EN Input Bias Current
IIBSD
VEN=GND or VIN
0
VIN=3V to 5.5V,
EN
Logic Low
VIL
Shutdown
Input
VIN=3V to 5.5V,
Threshold
Logic High
VIH
1.2
Start up
10Hz to100KHz,
Output Noise
eNO
100
IOUT=200mA
Voltage
COUT=1uF
Power
f=217Hz
-80
Cout=1uF,
Supply
PSRR
f=1KHz
-78
Iout=100mA
Rejection
f=10KHz
-65
Ratio
Thermal Shutdown
Shutdown, Temp
TSD
165
Temperature
increasing
Thermal Shutdown
TSDHY
30
Hysteresis
MAX
6
+1
+2
unit
V
%
mA
µA
130
180
mV
300
0.17
%/V
2
%/A
℃
ppm/
1
100
µA
nA
0.4
V
V
µVRMS
dB
℃
℃
Note 5: 100% production test at +25°C. Specifications over the temperature range are guaranteed by design and
characterization.
Note 6: This IC includes two kinds of output voltage accuracy versions.A: ±1%, B: ±2%.
 VOUT 1 − VOUT 2
 ∆V × V
OUT ( normal )
 IN
Note 7:Line regulation is calculated by ∆V
LINE = 

 × 100

Where VOUT1 is the output voltage when VIN=5.5V, and VOUT2 is the output voltage when VIN=3.6V,
VIN=1.9V .VOUT(normal)=2.8V.
△
 VOUT 1 − VOUT 2 
Note 8: Load regulation is calculated by ∆V
 ×100
LOAD = 
 ∆I × V
 OUT OUT ( normal ) 
Where VOUT1 is the output voltage when IOUT=1mA, and VOUT2 is the output voltage when IOUT=300mA.
VOUT(normal)=2.8V.
∆VOUT
Note 9:The temperature coefficient is calculated by TC
VOUT =
∆T × VOUT
PPMIC BU
BL9193 Rev 2.2
1/2011
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△I
OUT=0.299A,
4
BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Typical Performance Characteristics
Output Voltage vs. Temperature
Quiescent Current vs. Temperature
140
3.0
130
VIN=3.6V
Output Voltage(V)
Quiescent Current(uA)
CIN=COUT=1uF
2.9
2.8
2.7
VIN=3.6V
CIN=COUT=1uF
120
110
100
90
80
2.6
70
2.5
-50
-25
0
25
50
75
100
60
-50
125
-25
0
25
Dropout Voltage vs. Load Current
100
125
PSRR
CIN=COUT=1uF
250
-10
-20
VIN=3.6V
CBP=22nF
CIN=1uF,COUT=1uF
-30
200
PSRR(dB)
Dropout Voltage(mV)
75
0
300
150
100
-40
-50
-60
TJ=85°C
TJ=25°C
TJ=-40°C
50
0
50
Temperature(°C)
Temperaute(°C)
0
50
100
150
200
250
-70
IOUT=100mA
IOUT=200mA
-80
300
-90
10
100
1000
10000
100000
1000000
Frequency(Hz)
Load Current(mA)
EN Pin Shutdown Threshold vs. Temperature
1.05
VIN=3.6V
EN Pin Shutdown Threshold(V)
1.00
CIN=COUT=1uF
0.95
0.90
0.85
0.80
0.75
-50
-25
PPMIC BU
BL9193 Rev 2.2
1/2011
0
25
50
Temperature(°C)
75
100
125
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Applications Information
Like any low-dropout regulator, the external capacitors used with the BL9193
must be carefully selected for regulator
stability and performance. Using a capacitor whose value is > 1µF on the BL9193
input and the amount of capacitance can
be increased without limit. The input capacitor must be located a distance of not
more than 0.5 inch from the input pin of the
IC and returned to a clean analog ground.
Any good quality ceramic or tantalum can
be used for this capacitor. The capacitor
with larger value and lower ESR (equivalent series resistance) provides better
PSRR and line-transient response. The
output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application.
The BL9193 is designed specifically to
work with low ESR ceramic output capacitor in space-saving and performance
consideration. Using a ceramic capacitor
whose value is at least 1µF with ESR is >
25mΩ on the BL9193 output ensures
stability. The BL9193 still works well with
output capacitor of other types due to the
wide stable ESR range. Output capacitor of
larger capacitance can reduce noise and
improve load transient response, stability,
and PSRR. The output capacitor should be
located not more than 0.5 inch from the
VOUT pin of the BL9193 and returned to a
clean analog ground.
Bypass Capacitor and Low Noise
Connecting a 22nF between the BP pin
and GND pin significantly reduces noise on
the regulator output, it is critical that the
capacitor connection between the BP pin
and GND pin be direct and PCB traces
should be as short as possible. There is a
PPMIC BU
BL9193 Rev 2.2
1/2011
relationship between the bypass capacitor
value and the LDO regulator turn on time.
DC leakage on this pin can affect the LDO
regulator output noise and voltage regulation performance.
Enable Function
The BL9193 features an LDO regulator enable/disable function. To assure the LDO
regulator will switch on; the EN turn on
control level must be greater than 1.2 volts.
The LDO regulator will go into the shutdown mode when the voltage on the EN
pin falls below 0.4 volts. For to protect the
system, the BL9193 have a quick discharge function. If the enable function is
not needed in a specific application, it may
be tied to VIN to keep the LDO regulator in
a continuously on state.
Programming the BL9193 Adjustable
LDO regulator
The output voltage of the BL9193
adjustable regulator is programmed using
an external resistor divider as show in
Figure as below. The output voltage is
calculated using equation as below:
R1 

VOUT = VREF × 1 +

 R2 
Where:
VREF=1.23V typ (the internal
reference voltage)
Resistors R1 and R2 should be chosen for
approximately 50uA divider current. Lower
value resistors can be used for improved
noise performance, but the solution
consumes more power. Higher resistor
values should be avoided as leakage
current into/out of FB across R1/R2
creates an offset voltage that artificially
increases/decreases the feedback voltage
and thus erroneously decrease/increases
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
VOUT. The recommended design procedure
is to choose R2=30.1kΩ to set the divider
current at 50uA, C1=22pF for stability, and
then calculate using Equation as below:
 VOUT 
R1 = 
− 1 × R 2
 VREF 
In order to improve the stability of the
adjustable version, it is suggested that a
small compensation capacitor be placed
between OUT and FB. The suggested
value of this capacitor for several resistor
ratios is shown in the table below.
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
R1
R2
C1
VOLTAGTE
1.8V
13.9 kΩ 30.1 kΩ
22pF
2.5V
31.6 kΩ 30.1 kΩ
22pF
3.3V
51 kΩ
30.1 kΩ
22pF
3.6V
59 kΩ
30.1 kΩ
22pF
BL9193 Adjustable LDO regulator
Programming
VIN
1
VIN
VOUT
5
VOUT
1uF
1uF
2
R1
GND
C1
BL9193 -ADJ
3
EN
FB
Thermal protection limits power dissipation
in BL9193. When the operation junction
temperature exceeds 165°C, the OTP
circuit starts the thermal shutdown function
turn the pass element off. The pass
element turns on again after the junction
temperature cools by 30°C.
For continue operation, do not exceed
absolute maximum operation junction
temperature 125°C. The power dissipation
definition in device is:
1/2011
PD(MAX) = ( TJ(MAX) − TA ) /θJA
Where TJ(MAX) is the maximum operation
junction temperature 125°C, TA is the
ambient temperature and the θJA is the
junction to ambient thermal resistance. For
recommended operating conditions specification of BL9193, where TJ(MAX) is the
maximum junction temperature of the die
(125°C) and TA is the maximum ambient
temperature. The junction to ambient thermal resistance (θJA is layout dependent)
for SOT-23-5 package is 250°C/W, SC-705 package is 333°C/W, on standard
JEDEC 51-3 thermal test board. The maximum power dissipation at TA= 25°C can
be calculated by following formula:
PD(MAX) = (125°C−25°C)/333 = 300mW
(SC-70-5)
Thermal Considerations
BL9193 Rev 2.2
The maximum power dissipation depends
on the thermal resistance of IC package,
PCB layout, the rate of surroundings
airflow and temperature difference between junction to ambient. The maximum
power dissipation can be calculated by
following formula:
4
R2
PPMIC BU
PD = (VIN−VOUT) ×IOUT + VIN×IQ
PD(MAX) = (125°C−25°C)/250 = 400mW
(SOT-23-5)
The maximum power dissipation depends
on operating ambient temperature for fixed
TJ(MAX) and thermal resistance θJA. It is
also useful to calculate the junction of
temperature of the BL9193 under a set of
specific conditions. In this example let the
Input voltage VIN=3.3V, the output current
Io=300mA and the case temperature
TA=40°C measured by a thermal couple
during operation. The power dissipation for
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
the Vo=2.8V version of the BL9193 can be
calculated as:
PD = (3.3V−2.8V) ×300mA+3.6V×100uA
=150mW
And the junction temperature, TJ, can be
calculated as follows:
TJ=TA+PD×θJA=40°C+0.15W×250°C/W
=40°C+37.5°C=77.5°C<TJ(MAX) =125°C
with separate ground planes for VIN and
VOUT, with each ground plane connected
only at the GND pin of the device. In
addition, the ground connection for the
bypass capacitor should connect directly to
the GND pin of the device.
BL9193-2.8V Layout Circuit
VIN
VIN
1
C4
1uF
For this operating condition, TJ is lower
than the absolute maximum operating
junction temperature,125°C, so it is safe to
use the BL9193 in this configuration.
C1
1uF
J1
1
2
3
VIN
VOUT
5
BL9193
2
3
1
VIN
C3
1uF
GND
EN
VOUT
BP
4
C2
22nF
2
3
R1
Layout considerations
To improve ac performance such as PSRR,
output noise, and transient response, it is
recommended that the PCB be designed
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Package Description
Symbol
A
A1
B
b
C
D
e
H
L
Dimensions In Millimeters
Min
0.800
0.000
1.150
0.150
1.800
1.800
Max
1.100
0.100
1.350
0.400
2.450
2.250
Dimensions In Inches
Min
0.031
0.000
0.045
0.006
0.071
0.071
0.650
Max
0.044
0.004
0.054
0.016
0.096
0.089
0.026
0.080
0.260
0.003
0.010
0.210
0.460
0.008
0.018
SC-70-5 Surface Mount Package
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Package type
SC70-5
Number of devices per reel
3000
Tape dimension
Taping reel dimension
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
A1
B
b
C
D
e
H
0.889
0.000
1.397
0.356
2.591
2.692
0.838
0.080
1.295
0.152
1.803
0.559
2.997
3.099
1.041
0.254
0.035
0.000
0.055
0.014
0.102
0.106
0.033
0.003
0.051
0.006
0.071
0.022
0.118
0.122
0.041
0.010
L
0.300
0.610
0.012
0.024
SOT-23-5 Surface Mount Package
PPMIC BU
BL9193 Rev 2.2
1/2011
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BL9193
300mA UltraUltra-low Noise, UltraUltra-Fast
CMOS LDO Regulator
Package type
SOT23-5
(
Number of devices per reel
3000
)
Tape dimension Default: Type I
Type I
Type II
Taping reel dimension
PPMIC BU
BL9193 Rev 2.2
1/2011
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