RD15LD74AP, RD15LD74ANP, RD15LD74AT 8-bit D-type Flip-Flop Driver (with Clear) REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Description RD15LD74AP, RD15LD74ANP, RD15LD74AT have eight D-type flip-flop drivers and high voltage NMOS output (open drain output) in a 20 pin package. Each bit, there are a common clear and clock input. The input signal is output with the rising edge of clock signals. The voltage of maximum 15 V can be impressed to the drain-source voltage. Features • • • • • • • • Application of amusement equipment. Output voltage : VDS (max) = 15 V Output current : IDS (max) = 200 mA (par pin) Supply voltage range : 3.0 to 5.5 V Operating temperature range : –20 to +85 °C Quiescent supply current : 5 µA max. Low input current : 1 µA max. Ordering Information Part Name Package Type RD15LD74APT0 SDIP-20 pin RD15LD74ANPT0 DILP-20 pin RD15LD74ATH0 Note: TSSOP-20 pin Package Code (Previous Code) PRDP0020BA-A (20P4B) PRDP0020AC-B (DP-20NEV) PTSP0020JB-A (TTP-20DAV) Package Abbreviation Packing Abbreviation (Quantity) P T (1,125 pcs/box) 0 (Sn-Cu) P T (1,000 pcs/box) 0 (Ni/Pd/Au) T H (2,000 pcs/reel) 0 (Ni/Pd/Au) Please consult the sales office for the above package availability. Pin Arrangement CLR 1 20 VCC D0 2 19 Y0 D1 3 18 Y1 D2 4 17 Y2 D3 5 16 Y3 D4 6 15 Y4 D5 7 14 Y5 D6 8 13 Y6 D7 9 12 Y7 CLK 10 11 GND (Top view) REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 1 of 9 Surface Treatment RD15LD74AP, RD15LD74ANP, RD15LD74AT Logic Diagram Y0 Y1 19 Y2 18 Y3 17 Y4 16 Y5 15 Y6 14 Y7 13 12 VCC 20 D 10 CLK D Q Q D Q D Q D Q D Q D Q D Q CK CK CK CK CK CK CK CK R R R R R R R R CLR GND 1 11 2 3 D0 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 Note: Schmitt trigger circuit is added to all input. VH = 1.5 V (TYP) Function Table Inputs CLK X ↑ ↑ L ↓ CLR L H H H H Output Y Z Z L Y0 Y0 D X L H X X H : High level L : Low level X : Immaterial Z : High Impedance ↑ : Low to High transition ↓ : High to Low transition Y0 : Level of Y before the indicated steady input conditions were established. Timing Figure VCC CLK GND VCC D GND VCC CLR GND VOH Y REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 2 of 9 VOL RD15LD74AP, RD15LD74ANP, RD15LD74AT Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Output current Symbol VCC VI VDS IDS Maximum power *1 dissipation Storage temperature Note: PT Ratings 6.5 –0.5 to VCC –0.5 to 15 200 1.47 1.38 Tstg 0.76 –55 to +125 Unit V V V mA Conditions Output : “Z” (off) Output : “on” , Current of one circuit SDIP Ta = 25°C DILP Base implementation TSSOP W °C The absolute maximum ratings are values which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The maximum package power dissipation was calculated using a junction temperature of 150°C Recommended Operating Conditions Item Supply voltage Symbol VCC 3.0 5.5 Unit V Input voltage Output voltage VI VDS 0 0 VCC 15 V V IDS 0 0 0 0 0 0 200 150 200 140 200 105 0 –20 500 85 Output current (Current of an one circuit, when eight circuit operation) Input rise / fall time Operating temperature Note: tr, tf Ta Ratings Conditions Output “Z” (off) Duty cycle ≤ 60% Duty cycle ≤ 100% Duty cycle ≤ 55% Duty cycle ≤ 100% Duty cycle ≤ 25% Duty cycle ≤ 100% mA SDIP mA DILP mA TSSOP ns °C VCC = 3.0 V, 4.5 V Unused or floating inputs must be held high or low. Electrical Characteristics (Ta = –20 to +85°C) Item Symbol VIH Input voltage VIL Output voltage VDS VCC (V) Ratings Unit Conditions 4.5 to 5.5 3.0 to 3.6 Min VCC×0.84 VCC×0.76 — Typ — — — 4.5 to 5.5 3.0 to 3.6 4.5 to 5.5 3.0 to 3.6 — — — — — 0.30 0.25 0.60 Max — — VCC×0.16 VCC×0.24 0.45 0.38 0.90 — — 0.51 0.005 0.77 1.0 µA VI = VCC VI = 0 V All output “Z” (off) VI = VCC or GND All output “on”, VI = VCC or GND 3.0 to 3.6 V V IDS = 100 mA V IDS = 200 mA “H” input current IIH 4.5 to 5.5 3.0 to 5.5 “L” input current IIL 3.0 to 5.5 — 0.005 –1.0 µA Quiescent supply current ICC 5.5 — 0.005 5.0 µA 5.5 — 0.005 5.0 IDS 5.0 — 0.002 5.0 µA VDS = 12 V RDS 4.5 — 2.5 3.8 Ω IDS = 100 mA Output off state leak current Output on resister REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 3 of 9 RD15LD74AP, RD15LD74ANP, RD15LD74AT Switching Characteristics (Ta = –20 to +85°C, CL = 30 pF, tr = tf =6 ns ) Item Symbol Ratings VCC (V) 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 Min — — 1.0 1.0 1.0 1.0 25 20 3 3 50 40 Max 15 20 65 50 60 45 — — — — — — Maximum clock frequency fmax Propagation delay time tPLH Propagation delay time tPHL Setup time tsu Hold time th Pulse width tW Output rise time tTLH 3.3 ± 0.3 5.0 ± 0.5 — — Output fall time tTHL 3.3 ± 0.3 5.0 ± 0.5 — — Unit Conditions MHz ns CLK, CLR to Y ns CLK to Y ns D to CLK ns CLK to D ns CLK, CLR 30 20 ns Y 10 5 ns Y Test Circuit VT = 12V VCC Input Input Palse generator Zout = 50 Ω VCC See Function Table Palse generator Zout = 50 Ω RL = 120Ω CLK Y D CLR Output CL = 30 pF GND Note: 1. Input waveform : PRR = 1MHz, Duty Cycle = 50%, tr = 6ns, tf = 6ns 2. CL includes probe and jig capacitance. REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 4 of 9 RD15LD74AP, RD15LD74ANP, RD15LD74AT Waveforms • Waveforms – 1 tr tf VCC 90 % 90 % Data Input (D0 to D7) 50 % 50 % 50 % 10 % 10 % t su th GND t su th tf tr VCC 90 % Clock Input (CLK) 50 % 50 % 10 % 10 % GND t PHL Output (Y0 to Y7) t PLH 90 % 90 % 50 % 10 % 50 % 10 % t THL VOH VOL t TLH • Waveforms – 2 tf VCC 90 % 50 % 10 % Clear Input (CLR) GND t PLH 90 % Output (Y0 to Y7) 50 % 10 % VOH VOL t TLH • Waveforms – 3 tr tf High Level Pulse VCC 90 % 50 % 90 % 50 % 10 % 10 % GND tw All Input tw 90 % 90 % Low Level Pulse 50 % 10 % tf 50 % 10 % VCC GND tr Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The input and output is measured one at a time with one transition per measurement. REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 5 of 9 RD15LD74AP, RD15LD74ANP, RD15LD74AT Application Data Duty Cycle − Output Current Characteristics Duty Cycle − Output Current Characteristics • RD15LD74AP • RD15LD74AP Ta=25°C 180 180 160 160 140 120 100 80 60 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 40 20 1~5 6 7 8 140 120 100 80 60 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 40 20 0 0 0 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Duty Cycle (%) Duty Cycle − Output Current Characteristics Duty Cycle − Output Current Characteristics • RD15LD74ANP • RD15LD74ANP Ta=25°C 200 180 180 160 160 140 120 100 80 60 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 40 20 0 Ta=85°C 200 1~8 Output Current IDS (mA) Output Current IDS (mA) Ta=85°C 200 1~8 Output Current IDS (mA) Output Current IDS (mA) 200 1~4 5 6 7 8 140 120 100 80 60 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 40 20 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 6 of 9 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) RD15LD74AP, RD15LD74ANP, RD15LD74AT Application Data Duty Cycle − Output Current Characteristics Duty Cycle − Output Current Characteristics • RD15LD74AT • RD15LD74AT Ta=25°C 200 200 6 180 3 160 4 140 5 6 7 8 7 160 8 140 120 100 80 60 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 40 20 Output Current IDS (mA) Output Current IDS (mA) 180 Ta=85°C 1~5 120 100 1~2 80 60 • Output current values represent the current per circuit. • Repeated frequency ≥ 10Hz • The value the circle represents the value of the simultaneously - operated circuit. 40 20 0 0 0 0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 Duty Cycle (%) Duty Cycle (%) Switching Time − Ambient Temperature Characteristics Switching Time − Output Current Characteristics VCC=5.0V, VT=12V, CL=30pF, RL=120Ω 50.0 VCC=5.0V, VT=12V, Ta=25°C 1000.0 40.0 30.0 tPLH(CLK to Y) tPHL(CLK to Y) 20.0 tTLH 10.0 100.0 Switching Time (ns) Switching Time (ns) tPLH(CLR to Y) tPLH(CLR to Y) tPLH(CLK to Y) tPHL(CLK to Y) 10.0 tTLH tTHL tTHL 0.0 1.0 -40 -20 0 20 40 60 80 Ambient Temperature Ta (°C) REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 7 of 9 100 10 100 Output Current IDS (mA) 1000 RD15LD74AP, RD15LD74ANP, RD15LD74AT Package Dimensions RENESAS Code PRDP0020BA-A Previous Code 20P4B MASS[Typ.] 1.0g 11 1 10 c *1 E 20 e1 JEITA Package Code P-SDIP20-6.3x19-1.78 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. D A A2 *2 Reference Dimension in Millimeters Symbol L A1 e1 D E A A1 A2 bp b3 c *3 b 3 e bp SEATING PLANE e L JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 0° 15° 1.528 1.778 2.028 3.0 MASS[Typ.] 1.26g D 11 E 20 1 10 b3 0.89 A1 A Z L Reference Symbol e bp θ c e1 ( Ni/Pd/Au plating ) REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 8 of 9 e1 D E A A1 bp b3 c θ e Z L Dimension in Millimeters Min Nom Max 7.62 24.50 25.40 6.30 7.00 5.08 0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0° 15° 2.29 2.54 2.79 1.27 2.54 RD15LD74AP, RD15LD74ANP, RD15LD74AT JEITA Package Code P-TSSOP20-4.4x6.5-0.65 RENESAS Code PTSP0020JB-A *1 Previous Code TTP-20DAV MASS[Typ.] 0.07g D F 20 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 11 c HE *2 E bp Terminal cross section ( Ni/Pd/Au plating ) Index mark Reference Dimension in Millimeters Symbol 1 10 e *3 bp L1 x M A Z A1 θ L y Detail F REJ03D0894-0300 Rev.3.00 Feb 29, 2008 Page 9 of 9 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 6.50 6.80 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.4 0.5 0.6 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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