YAMAR
Ele c tro nics L td
Preliminary Data Sheet
SIG61 - Smart Slave for
Multiplex Powerline Network
This information is preliminary and may be changed without notice
1 GENERAL
The SIG61 is an independent slave in a Powerline communication network controlled by a SIG60
master device. The SIG61 has 4 identification (ID) pins, used to set the device address, 8 input pins
and 8 output pins. The master can access any SIG61 device independently by using the proper device
address. Data received from a remote SIG60 Master device is reflected to its output pins. The Master
device can read the SIG61 input pins remotely. Its small footprint integrates most of the components
needed for proper operation allowing small-size control solutions.
The SIG61 is an economical slave device for applications such as controlling motors, reading sensors
etc., eliminating the need for dedicated control wires and a host controller for its operation. It helps
reducing the harness size and increase reliability. The SIG61 has a sleep mode that enables power
saving; special Wakeup messages on the AC or DC line are used to signal the sleeping devices to
return to normal operation mode.
The SIG61 is useful for a wide range of Automotive, Avionics and Industrial applications such as sensor
reading, actuator activation, doors, seats, mirrors, climate control, lights, Truck-Trailer, etc.
Host
Master
8
8
SIG61
ID
4
8
8
SIG61
ID
4
Battery Power Line
Figure 1.1 - SIG61 Application example
Applications
Features
Truck-Trailer sub-bus
Door module
Climate control network
Front and back Lights
Sensors Actuators network
Entertainment control
Renewal Energy / Battery
management Microgrid
Security Monitoring
© 2012 Yamar Electronics Ltd.
7 selectable Carrier frequencies 1.75MHz - 13MHz
Selectable bit rate between 9.6 Kbps to 115.2 Kbps.
8 output and 8 input pins
Eliminates data wires and transceiver.
Operates over wide range of noisy power supply / battery lines.
Byte oriented communication.
Sleep Mode for low power consumption.
Allows Master - Slave multiplex networks
Several independent networks can operate over the same wire
using different carrier frequencies.
Small footprint QFN 64 pin package
1
DS-SIG61 R0.98
2 OVERVIEW
The SIG61 is an independent slave in a Master-Slaves network operating on a selected narrow band
channel. A single SIG60 master controls all the slaves in a network; the slaves may be SIG61 devices
as well as SIG60 devices operating as slaves.
Proper Network operation is maintained by employing 5 types of command messages: Read, Readchange, Write, Sleep and Change-Frequency. The command format is similar to the standard Universal
Asynchronous Receiver Transmitter (UART).
The SIG61 has internal narrow band modem, capable of operating in noisy environments. The receiver
listens to the Powerline on its preset frequency. It filters out the signal from noise and interference and
tries to recover the original command. If the checksum is correct, the SIG61 extracts the ID, Command
and the Data.
If the received ID matches its own ID, the SIG61 proceeds to detect the received command. When a
Write command is received, the data part of the command is directed to the corresponding 8 output
pins. When a Read command is detected, the SIG61 responds by transmitting a dedicated message
towards the master containing an image of its 8 input pins.
Multiple networks can operate concurrently on the same wire using different carrier frequencies.
2.1
Channels and Network
The SIG60-SIG61 network supports 16 combinations of frequency pairs. When set to such a pair, it is
easy to switch from one frequency to the other when such need arises. Each channel accommodates a
single SIG60 master and up to 15 SIG61/SIG60 slave devices. Additional SIG60-SIG61 networks can
coexist on the same power line by employing different frequencies for each network, thus allowing
different applications.
Channel frequencies: 1.75MHz, 4.5MHz, 5.5MHz, 6.0MHz, 6.5MHz, 10.5MHz and 13.0MHz.
Data transfer rate:
9.6Kbps up to 115.2Kbps.
Cable length: Dependant on external AC loads connected to the AC/DC Powerline.
2.2
The SIG61 Device
Figure 2.1 outlines the building blocks of the SIG61 device.
Figure 2.1 - SIG61 Logical Blocks
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
3 SIG61 SIGNALS
INH
nSleep
AutoSleep
nReset
Out0
Out1
Wake
Out2
Out3
MF1nF0
Out4
Out5
TxOn
Out6
Out7
RxOn
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Device signals are described in table 3.1.
SIG61
F0F1-0
F0F1-1
Gnd
OscO
OscIn
AGnd
F0F1-2
F0F1-3
Vcc
F1B
F0B
AVdd
RxP
Mode3
Mode4
AutoFreqCh
Gnd
Vdd
HDO
In7
In6
F1nF0
In5
In4
In3_HDC
In2_HDI
Vdd
In1
DTxO
Gnd
In0
Mode2_LBD
Id0
Test
Id1
Id2
Id3
Vdd
RxIn
RxN
TxO
Gnd
Gnd
NC
Vdd
InterHope
BitRate1
BitRate0
EXP
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
EXP
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Figure 3.1 - SIG61 Pin-out
Pin name
Pin# Pin type
HDO
35
Output
8mA
Output
8mA
INH
32
nSleep
31
Input
Wake
26
Input
nReset
InterfHop
29
3
Description
Control Signals
Digital data output signal. Output the received data from the
powerline to the host.
Inhibit output for enabling the host or an external voltage regulator
powering the host. This signal is HIGH in the normal and standby
modes and LOW in sleep mode.
Sleep control input. Pulling this signal to LOW puts the SIG61 in
sleep mode. Should be pulled to Vdd.
Local wakeup input. Negative or positive edge triggered. This pin can
be connected to an external switch in the application. When the pin is
triggered the device will wake up and send a wake up message to all
the devices on the network. When not in use, this pin should be
pulled Up or Down.
Input, PU Reset Input
Input, PD Allows automatic frequency hoping whenever an interference signal
is detected on the power line. When HIGH, detection of interference
switches the operating frequency between F0 and F1. If at the new
frequency, no reception occurred for 2 sec, the operating frequency is
switched back. For designs with a single channel this pin should be
tied to ground.
Test
MF1nF0
15
23
OscO
52
Input, PD Should be connected to Gnd
Output Output indicating the operating frequency. F1 when HIGH and F0
12mA
when LOW.
Line Interface signals
Analog Crystal Output
Output
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
OscIn
53
Analog
Input
Analog
Output
Analog
Input
Tristate/
Output
2mA
Analog
Input
Analog
Output
Analog, Bi
directional
Analog, Bi
directional
Output
12mA
Output
12mA
RxN
9
RxP
61
DTxO
45
RxIn
10
TxO
8
F0B
59
F1B
58
TxOn
20
RxOn
17
In0
47
Input PD
In1
44
Input PD
In2_HDI
42
Input
In3_HDC
41
Input
In4
40
Input PD
In5
39
Input PD
In6
37
Input PD
In7
36
Input PD
Out0
28
Out1
27
Out2
25
Out3
24
Out4
22
Out5
21
Out6
19
Out7
18
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Output
8mA
Id0
Id1
Id2
Id3
16
14
13
12
Crystal Input
The internal comparator negative pin. Its value is internally pulled to
Vdd/2. Bypass RxN to Ground with a 1nF capacitor.
Positive pin input signal. Should be tied to RxN with a 1K Ohm
resistor.
Modulated digital transmit signal output to both ceramic filters.
Receive input from the power line to the RX operational amplifier. This
input is pulled internally to Vdd/2.
Transmit output.
F0 External filter I/O. Its value is internally pulled to Vdd/2.
F1 External filter I/O. Its value is internally pulled to Vdd/2.
HIGH when the device is transmitting a message.
HIGH when the device is in receive mode.
I/O Signals
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command. When in SIG60 mode, HDI input.
The pin is read by the Master with a Read or Read-Change
command. When in SIG60 mode, HDC input.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
The pin is read by the Master with a Read or Read-Change
command.
Output of data bit 0 when the Write command received from Master.
Output of data bit 1 when the Write command received from Master.
Output of data bit 2 when the Write command received from Master.
Output of data bit 3 when the Write command received from Master.
Output of data bit 4 when the Write command received from Master.
Output of data bit 5 when the Write command received from Master.
Output of data bit 6 when the Write command received from Master.
Output of data bit 7 when the Write command received from Master.
Configuration Signals
Input PD
Input PD
Input PD
Input PD
© 2012 Yamar Electronics Ltd.
SIG61 bit 0 ID address in the network.
SIG61 bit 1 ID address in the network.
SIG61 bit 2 ID address in the network.
SIG61 bit 3 ID address in the network.
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DS-SIG61 R0.98
F0F1-0
F0F1-1
F0F1-2
F0F1-3
BitRate0
BitRate1
NC
Mode2
Mode3
Mode4
AutoFreqCh
AutoSleep
F1nF0
Vdd
GND
AGnd
AVdd
Exp
49
50
55
56
1
2
5
48
62
63
64
Input PD
Input PD
Input PD
Input PD
Input PD
Input PD
--Input PD
Input PD
Input PD
Input PD
Frequency selection pins. See Table 4.2.
Frequency selection pins. See Table 4.2.
Frequency selection pins. See Table 4.2.
Frequency selection pins. See Table 4.2.
Bit rate selection pins. See Table 4.3.
Bit rate selection pins. See Table 4.3.
Not connected.
38
Input PD
Power
Selects between F0 / F1. HIGH – F1, LOW – F0
Power signals
3.3V power supply.
Power
Ground
Power
Power
Analog Ground
3.3V Analog Power. Separate from Vdd with a 6.8 to 10 Ohm resistor and
bypass to Ground with 1nF and 10nF capacitor.
May be connected to GND
Should be left unconnected.
Should be connected to Vdd.
Should be connected to Vdd
Automatic Frequency Change. When HIGH, the device automatically
switches frequency after about 4 seconds without bus activity.
30 Input PD When this pin is set to HIGH, the device will automatically enter sleep
mode after about 8 seconds without bus activity.
4,11,
34,43,
57
6,7,33,
46,51
54
60
Exp
PD – Pull down resistor 100K ohm ±%30
PU – Pull up resistor 100K ohm ±%30
Table 3.1 - Device signals
3.1 Power Signals
Vdd and Gnd layout traces should be as wide as possible. It is recommended to connect a 0.1uF
capacitor between each Vdd and ground pins, as close as possible to the pins.
Analog Vdd pin, AVdd, should be connected to Vdd. AGnd should be connected to ground. The Analog
supply has to be sufficiently powerful (capable of current driving), to avoid any fluctuations of supply
voltage level. It is recommended to keep the lines connecting the 3.3V power supply to Vdd pins as
short as possible with wide PCB traces.
AVdd
Vdd
R3
10
C5
1n
C6
10n
Figure 3.2 - Recommended AVdd circuitry
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
Input Port (8)
Output Port (8)
ID (4)
Vdd
Preliminary Data
Vdd
R5
R6
100K
100K
Optional 3MHz
Rx HiPass Filter for very noisy
channels, replaces C9
C21
0.1u
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
L3
100K
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C23
0.1u
R11
100K
Vdd
C20
Gnd
Vdd
HDO
In7
In6
F1nF0
In5
In4
In3_HDC
In2_HDI
Vdd
In1
DTxO
Gnd
In0
Mode2_LBD
C9a
Id0
Test
Id1
Id2
Id3
Vdd
RxIn
RxN
TxO
Gnd
Gnd
NC
Vdd
InterHope
BitRate1
BitRate0
U1_1
SIG61
0.1u
R1
49
50
51
52
53
54
F0F1_2 55
F0F1_3 56
57
58
59
60
61
MODE3 62
MODE4 63
64
* 1.2K
F0F1_0
F0F1_1
Vdd
INH
nSleep
AutoSleep
nReset
Out0
Out1
Wake
Out2
Out3
MF1nF0
Out4
Out5
TxOn
Out6
Out7
RxOn
100K
R7
F0F1-0
F0F1-1
Gnd
OscO
OscIn
AGnd
F0F1-2
F0F1-3
Vcc
F1B
F0B
AVdd
RxP
Mode3
Mode4
AutoFreqCh
R8
6.8uH
D8 BAS70-04
Vdd
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Power line
R4 C10
18
1n
2.2n/200V
R17
18
Vdd D2
C19
D1
0.1u
BAS70-04
EXP
Vdd
R2
3
2K
C3
F0 1
X1
1n
1n
C1
C2
R12
1K
4MHz
NC
C8 1n 3
Vdd
C4
C9 220p
BitRate (2)
C7
NC
220p
Vdd
BAS70-04
EXP
220pC11
R3 6.8
5.5MHz
Ceramic
Filter
F1 1
6.5MHz
C5
1n
C6
R13
1K
10n
Ceramic
Filter
Figure 3.3 – Typical SIG61 dual channel circuit
Notes:
All input the signals should be tied either to Gnd, or Vdd, according to the desired mode of
operation.
F0 and F1 are ceramic filters
Adjust R1 for maximal output level without distortion on powerline.
C1 and C2 values depend on crystal used. Usually values are between 0pF (NC) to 1.5pF.
Optional 3MHz HPF for very noisy channels, replace C9 with C9a, C11, D8 and L3
F1 is an optional communication channel
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
3.2 Ceramic Filter
3.2.1
Ceramic Filter Considerations
The SIG61 is designed to operate with one ceramic filter for transmission and reception. However, if
switching between two channels is desired, two ceramic filters are required. The minimum allowable
bandwidth of the ceramic filters is +/-60 kHz @ 3dB. Narrow bandwidth limits the maximal bit rate.
The SIG61 selectable frequencies meet market available ceramic filters. It is important to select the
widest bandwidth available. 1.75MHz, 10.5MHz and 13MHz may use discrete filters.
Through hole ceramic filters are available from Oscilent.
Nominal
freq.
3 db BW
20db BW Insertion Stop band In/Out
loss attenuation imped.
MHz
KHz min.
KHz max.
dB max.
dB min.
Oscilent
part #
Ohm
*1.75
+/-70
750
6.0
330-1000 discrete filters
4.50
+/-70
750
6.0
30
1000
773-0045
5.50
+/-80
750
6.0
30
600
773-0055
6.00
+/-80
750
6.0
30
470
773-0060
6.50
+/-80
800
6.0
30
470
773-0065
**10.50
+/-150
1500
4.5
330
discrete filters
**13.00 280 +/-50
1500
4.5
330
discrete filters
* 1.75MZ can operate only at 9.6Kbps
** 10.5MHz and 13.00MHz operates at 115.2Kbps instead of 9.6Kbps.
SMD ceramic filters are available from Murata.
Nominal 3 db BW 20db BW Insertion Stop band In/Out
freq.
loss attenuation imped.
MHz
4.50
5.50
6.00
6.50
3.3
KHz min.
KHz max.
+/-60
+/-60
+/-60
+/-60
600
600
600
600
dB max.
dB min.
Ohm
20
25
25
25
1000
600
470
470
6.0
6.0
6.0
6.0
Murata
part #
SFSKA4M50CF00-R3
SFSKA5M50CF00-R3
SFSKA6M00CF00-R3
SFSKA6M50CF00-R3
Oscillator
The SIG61 is designed to operate with a low cost 4MHz crystal connected between OscIn and
OscOut pins. Each of these pins should be connected to the ground via a capacitor. All the
corresponding PCB traces should be as short as possible.
Recommended crystals are:
1. NDK AT-51 GW.
2. Epson MA-506.
The values of C1, and C2 in Figure 3.3, pertaining to the oscillator circuitry, should be determined
according to the crystal manufacturer recommendations. Values between 0pF and 1.5pF may serve as
good starting point.
The overall frequency tolerance should not exceed 200ppm.
3.4
Communication performance
The maximum cable length between two devices depends mainly on the AC impedance of loads
connected to that line and number of nodes. The Powerline cable length has less effect on
communication. The SIG61 requires a minimum received signal of 20mVpp for proper reception.
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
4
4.1
DEVICE OPERATION
Protocol
The device operation is controlled via 5 types of commands:
Write command - Upon receiving a Write command with the SIG61 specific ID, the device shall output
the data byte content as indicated by the command to its Output pins.
Read command - Upon receiving a Read massage with the SIG61 specific ID, the device shall
respond by sending a message containing the status of its Input pins (followed by an appropriate
checksum).
Read-Change command - When receiving a Read-Change massage with the SIG61 specific ID, the
device shall respond to the command by indicating if a pulse upon detecting the first change on its input
pins. The response message shall contain the new status of the input pins followed by an appropriate
checksum.
Sleep command - Upon receiving a Sleep command, the device shall enter a low power-consumption
(sleep) mode. A wakeup message generated by the master, or by any of the slaves, wakes up all the
devices on the network. This is a global message targeting all the slaves in the network.
Change-Frequency command - Upon receiving Change-Frequency command, the device shall switch
from its current operational frequency to the other. This command is a global command targeting all the
slaves in the network.
4.1.1
Command structure
The structure of the five types of commands is detailed below.
Command type 1: Write command.
The Write command consists of 5 bytes: sync break, sync field, Identifier, data and checksum.
Upon receiving a write command, if checksum and protection bits calculations are successful, the data
byte content is transferred to the corresponding output pins.
Sync break: Sync break length is at least 13 bit times with compliance to Lin protocol.
Identifier byte: Consist of 2 protection bits (MSB),"01" bits and 4 ID bits - {P1, P0, '0','1', ID [3:0]}
Protection bits calculation:
P0 = (Identifier [0]) XOR (Identifier [1]) XOR (Identifier [2]) XOR (Identifier [4])
P1 = ~ ((Identifier [1]) XOR (Identifier [3]) XOR (Identifier [4]) XOR (Identifier [5]))
Checksum calculation:
The checksum is an inverted 8 bit sum of the Identifier and Data byte including (own) carry:
Checksum = ~ (Identifier Byte + Data Byte + Carry)
Transmitted command
Sync break
Sync Field
P1, P0, 0, 1, Address
Out [7:0]
Checksum
3 bit delay
SIG61 Outputs at receiving device
Figure 4.1 - Write command
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
Write Command Example
Sending Write command of Data byte 0xFF to a device with ID '4' will be calculated the following way:
P0 = ('0' XOR '0' XOR '1' XOR '1') = '0'
P1 = ~ ('0' XOR '0' XOR '1' XOR '0') = '0'
Identifier Byte = '00'-'01'-'0100' = 0x14
Checksum = ~ (0x14 + 0xFF + (Carry ='1')) = 0xEB
Transmitted Command = [Sync Break - 0x55 - 0x14 - 0xFF - 0xEB]
Command type 2: Read command.
The Read command, initiated by the Master, requests the status of the SIG61 input pins.
The Read command from the master consists of 3 bytes: sync break, sync field and identifier.
Identifier byte: consist of 2 protection bits (MSB),"00" bits and 4 ID bits - {P1, P0, '0','0', ID [3:0]}
The two protection bits are calculated as described above.
If header detection is correct (including protection bits), the SIG61 device (whose ID matches the one in
the command) shall respond by sending two bytes. A data byte containing the status of its eight input
Signal pins followed by a checksum byte. The checksum calculation is carried out as in the description
above while part of it, the identifier byte, was transmitted by the Master. Figure 4.2 shows a generic
Read command.
Sync break
Sync Field
P1, P0, 0, 0, Address
Master
Data (8 input bits)
Checksum
Slave
Figure 4.2 - Read command
Command type 3: Read-change
The Read-change command is similar to the Read command. However, it enables to detect any change
in the input pins (pulse-like behavior) that may have occurred between two consecutive Read or Readchange commands. The command from the master instructs the SIG61 to send back information on
changes of its input pins since the last Read or Read-change command. The first change on the pin
after the Read command sets its bit value.
Figure 4.3 shows the process of determining the sent bit value of an input pin.
“1”
“1”
“0”
“0”
Sent value
Change
Input pin level
Read -change
command
1 bit
Figure 4.3 - Determining the recent changed value of an input pin
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
The Read-change command from the master has 3 bytes: sync break, sync field and identifier.
Identifier byte: consist of 2 protection bits (MSB),"10" bits and 4 ID bits - {P1, P0, '1','0', ID [3:0]}
The response for this command is a data byte containing the SIG61`s input pins recent changed value,
followed by the checksum byte. See checksum and protection bits calculation description above. Figure
4.4 shows a Read-changes command.
Sync break
Sync Field
Data (8 input bits)
P1, P0, 1, 0, Address
Master
Checksum
Slave
Figure 4.4 - Read-change command
Command type 4: Sleep command.
This type of command consist of 5 bytes: sync break, sync field, “3C” Hex, “00” Hex and checksum.
The sleep command identifier is “3C”Hex as in LIN2.0 specifications and the following data byte
“00”Hex.
Upon reception of sync break, sync field, “3C”Hex and “00”Hex bytes, a device enters sleep mode
immediately and as a result it’s the following command bytes are ignored.
Sync break
Sync Field
0x3C
Zero byte/bytes
Checksum
Figure 4.5 - Sleep command
Command type 5: Change Frequency command.
This type of command consists of 5 bytes - sync break, sync field, “FE” Hex, “00” Hex and checksum.
The change frequency command identifier is “FE” Hex and the following data byte is “00”Hex.
Upon reception of sync break, sync field, “FE” Hex and “00” Hex bytes the frequency changes from F1
to F0, or vise versa. Checksum calculation follows the description above.
Sync Field
Sync break
0xFE
Zero byte/bytes
Checksum
Figure 4.6 - Frequency Change command
4.2
Power Management
The SIG61 device features Sleep mode for power saving. Entering the Sleep mode, as well as waking
up, can be initiated locally, by means of dedicated input pins, or remotely through activity (proper
messages) over the bus.
4.2.1
Entering Sleep mode
The SIG61 can enter sleep mode by any of the following ways:
1. The device nSleep pin is lowered.
2. Sleep command from a remote master is received.
3. The AutoSleep pin is set HIGH and no reception occurred for about 8 seconds.
4.2.2
Device Outputs during Sleep
During Sleep mode, the SIG61 8 output pins remain unchanged if the device has entered this mode
due to a Sleep command from the Master or by lowering the Pin nSleep.
However if the device entered the Sleep mode due to the AutoSleep function, SIG61 will lower all the
outputs to "0".
© 2012 Yamar Electronics Ltd.
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DS-SIG61 R0.98
4.2.3
Remote wake up process
The SIG61 can be awakened by a remote SIG60 master, or SIG61 slave, device transmitting a wakeup
message over the bus. During Sleep Mode, the SIG61 wakes up periodically, every 32mSec, to sense
for bus activity. If a wakeup message is detected, the SIG61 device raises pin INH and lowers pin HDO.
If nSleep pin is low upon remote waking up, the local host (a device controlling the SIG61) which initially
pulled nSleep pin down, must raise the nSleep back high. Figure 4.7 provides the signal description.
T11
Wakeup Message
Powerline
msg. detected
T9 T10
SIG61 Rx
INH
nSleep
HDO
Standby
Normal mode
Figure 4.7 - Wakeup from bus message
4.2.4
Wakeup from Wake pin
A transition seen on the Wake pin (caused by an external source) is used to wake up the device. The
device then enters Standby mode, it rises pin INH, and transmits a wakeup message to the bus. While
transmitting the wakeup message, the device lowers pin HDO. After the transmission is completed the
device raises pin HDO. This is depicted in Figure 4.8. After the transmission is completed the device
enters Normal mode. If nSleep pin is low upon waking up, the local host which initially pulled nSleep pin
down, must raise the nSleep back to high.
Wake
INH
T1
DC-BUS
Wakeup Message
Standby
HDO
Normal
T2
T1 = 30uS-62uS
T2 = 92uS-124uS
mode
Figure 4.8 - Wakeup from Wake pin
4.3
Timing Characteristic
Symbol
T1
T2
T3
Figure
4.3,4.4
4.3
4.3
T4
T5
T6
4.5
4.4
Characteristics
Drop of HDC to drop of HDI
Raise of HDC to drop of HDI
Command stop bit to raise of HDC
Min
200nS
200nS
Drop of nSleep to drop of INH
Raise of nSleep to raise of INH
Transact on Wake to raise of INH
30uS
30uS
30uS
© 2012 Yamar Electronics Ltd.
11
Max
Half bit
rate
62uS
62uS
62uS
DS-SIG61 R0.98
4.4
T7
T8
4.3
4.4
T9
T10
T11
4.5
4.5
4.5
Raise of nSleep to drop of HDO
Transact on Wake to drop of HDO
Power Up or Reset to Normal mode
Receive duration during sleep mode
Receive period during sleep mode
Wakeup message
92uS
92uS
1.5mS
32mS
124uS
124uS
6mS
+/-20%
150mS
SIG61 Configuration
The Pins labeled “Mode 4” and “Mode 3” should be tied up to Vdd.
The SIG61 operates at default with the following parameters:
Bit rate: 19.2Kbps, F0=5.5MHz, F1=6.5MHz
The following configuration bits set the operating frequencies according to table 4.2.
Table 4.2 – F0, F1 select
F0F1 (3:0) pins
F0
F1
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
1.75Mhz
1.75Mhz
1.75Mhz
1.75Mhz
4.5Mhz
4.5Mhz
4.5Mhz
4.5Mhz
10.5Mhz
5.5Mhz
5.5Mhz
6.0Mhz
6.0Mhz
6.5Mhz
6.5Mhz
5.5Mhz
4.5Mhz
5.5Mhz
6Mhz
6.5Mhz
5.5Mhz
6.0Mhz
6.5Mhz
10.5Mhz
13.0Mhz
10.5Mhz
13.0Mhz
10.5Mhz
13.0Mhz
10.5Mhz
13.0Mhz
6.5Mhz
Table 4.3 – bit rates selection
BitRate (1,0)
11
10
01
Pins
Frequency
1.75 MHz
9.6K
4.50 MHz
38.4K 57.6K
9.6K
5.50 MHz
38.4K 57.6K
9.6K
6.00 MHz
38.4K 57.6K
9.6K
6.50 MHz
38.4K 57.6K
9.6K
10.50 MHz
38.4K 57.6K 115.2
13.00 MHz
38.4K 57.6K 115.2
Signal
AutoSleep
ID[3:0]
F1nF0
InterHop
© 2012 Yamar Electronics Ltd.
High (“1”)
Auto Sleep On
Defines device ID
Select F1
InterHop On
12
00
19.2K
19.2K
19.2K
19.2K
19.2K
19.2K
19.2K
Low (“0”)
Auto Sleep Off
Select F0
InterHop Off
DS-SIG61 R0.98
5
ELECTRICAL PARAMETERS
5.1
Absolute Maximum Rating
Ambient Temperature under bias
Storage Temperature
Input Voltage
Vdd Supply voltage
5.2
-40C to 125C
-55C to 150C
-0.6V to Vdd+0.3V
-0.3V to 4V
Electrical Operating Conditions
Symbol
Vdd
Idd
Idd
Ipd
Characteristics
Supply Voltage
Supply Current
Supply Current during Tx
Supply Current in Sleep
mode
5.3
Min
3.0
Typ
3.3
40
50
80
Max
3.6
Vdd
3.0
3.0
3.0
3.0
Typ
2.1
0.9
2.4
0.4
Units
V
mA
mA
uA
Conditions
Units
V
V
V
V
Conditions
5.5MHz
5.5MHz
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
VOL
Iout
IIN
Characteristics
Minimum high level input voltage
Maximum low level input voltage
Minimum high level output voltage
Maximum low level output voltage
Maximum output current, other
pins
Maximum input current
5.4
3.3
± 10
uA
Operating Temperature
Commercial:
Industrial:
See pins table
0C to 70C
-40C to 85C
© 2012 Yamar Electronics Ltd.
13
DS-SIG61 R0.98
5.5
Mechanical Information
Package type - QFN 64 pin
Figure 5.1 – QFN64 mechanical dimensions
© 2012 Yamar Electronics Ltd.
14
DS-SIG61 R0.98
Revision changes:
Revision
0.2
0.4
0.5
0.61
Date
2.3.2008
22.5.2009
25.5.2009
22.7.2009
0.7
13.9.2009
0.8
20.11.2009
0.9
20.12.2009
0.92
0.93
0.932
0.94
0.95
0.96
0.961
0.97
28.12.2009
7.1.2010
6.5.2010
29.8.2010
24.10.2010
27.2.2011
4.8.2011
1.11.2011
0.98
30.4.2012
Comments
Detailed description
Updated schematic
Updated pin information
Updated mechanical drawing
Added “Outputs during Sleep”
Added checksum and parity calculations
Renumbering figures
Update the Write and Read commands.
Update tables 4.2- 4.3
Added 3.4.8 and 3.4.9
Updated schematics, protection network, Electrical parameters, pin
description table
Updated drawings, notations, descriptions.
Updated Read-change command explanation
Updated drawings, descriptions.
Updated ceramic filters, schematics,
Updated figures 4.1-4.6
Updated figure 3.3 schematic for high noise channels operation
Updated figure 3.3 C9 and C11 to 220p
Update schema - Connect pins Mode3 and Mode4 to Vdd.
Update Table 3.1 - Replace between the GND pins and the Vdd pins, Fix a
typo at mode4 pin number.
Update figures 4.1 ,descriptions, examples
© 2012 Yamar Electronics Ltd.
15
DS-SIG61 R0.98