RENESAS M16C/64

REJ09B0392-0064
M16C/64 Group
16
Hardware Manual
RENESAS MCU
M16C FAMILY / M16C/60 SERIES
PRELIMINARY
M16C/64 Group Hardware
Manual
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the
latest information published by Renesas Technology Corp. through various means,
including the Renesas Technology Corp. website (http://www.renesas.com).
Rev.0.64
Revision Date: Oct 12, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
HOW TO USE THIS MANUAL
1.
Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A
basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions,
peripheral functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the M16C/64 Group. Make sure to refer to the latest versions of these
documents. The newest versions of the documents listed may be obtained from the Renesas Technology
Web site.
Document Type
Datasheet
Description
Document Title
Document No.
Hardware overview and electrical characteristics M16C/64 Group
REJ03B0216
Datasheet
This hardware
Hardware manual Hardware specifications (pin assignments, mem- M16C/64 Group
Hardware Manual manual
ory maps, peripheral function specifications,
electrical characteristics, timing charts) and
operation description
Note: Refer to the application notes for details on
using peripheral functions.
Available from Renesas TechnolApplication note Information on using peripheral functions and
ogy Web site.
application examples
Sample programs
Information on writing programs in assembly language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are
described below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the
word “register,” “bit,” or “pin” to distinguish the three categories.
Examples
the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b” is appended to numeric values given in binary format. However, nothing is
appended to the values of single bits. The indication “h” is appended to numeric values given in
hexadecimal format. Nothing is appended to numeric values given in decimal format.
Examples
Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7
b6
b5
b4
b3
*1
b2
b1
b0
Symbol
XXX
0
Bit Symbol
XXX0
Address
XXX
Bit Name
XXX bits
XXX1
After Reset
00h
Function
RW
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
RW
RW
(b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(b3)
Reserved bits
Set to 0.
RW
XXX bits
Function varies according to the operating
mode.
RW
XXX4
*3
XXX5
WO
XXX6
RW
XXX7
XXX bit
*2
b1 b0
0: XXX
1: XXX
*4
RO
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation
ACIA
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
UART
VCO
Full Form
Asynchronous Communication Interface Adapter
bits per second
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment bus
Input/Output
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connection
Phase Locked Loop
Pulse Width Modulation
Special Function Registers
Subscriber Identity Module
Universal Asynchronous Receiver/Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
IEBus is a registered trademark of NEC Electronics Corporation.
SFR Page Reference
Address
0042h
Register
INT7 Interrupt Control Register
Symbol
INT7IC
0001h
0043h
INT6 Interrupt Control Register
INT6IC
0002h
0044h
INT3 Interrupt Control Register
INT3IC
106
0003h
0045h
Timer B5 Interrupt Control Register
TB5IC
105
0046h
TB4IC,
U1BCNIC
105
TB3IC,
U0BCNIC
S4IC, INT5IC
105
S3IC, INT4IC
106
BCNIC
106
004Bh
Timer B4 Interrupt Control Register, UART1
BUS Collision Detection Interrupt Control
Register
Timer B3 Interrupt Control Register, UART0 BUS
Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register, INT5 Interrupt Control Register
SI/O3 Interrupt Control Register, INT4 Interrupt Control Register
UART2 BUS Collision Detection Interrupt
Control Register
DMA0 Interrupt Control Register
DM0IC
105
000Dh
004Ch
DMA1 Interrupt Control Register
DM1IC
105
000Eh
004Dh
Key Input Interrupt Control Register
KUPIC
105
000Fh
004Eh
A/D Conversion Interrupt Control Register
ADIC
105
004Fh
UART2 Transmit Interrupt Control Register
S2TIC
105
0050h
UART2 Receive Interrupt Control Register
S2RIC
105
0051h
UART0 Transmit Interrupt Control Register
S0TIC
105
0013h
0052h
UART0 Receive Interrupt Control Register
S0RIC
105
0014h
0053h
UART1 Transmit Interrupt Control Register
S1TIC
105
Address
0000h
Register
Symbol
Page
0004h
Processor Mode Register 0
PM0
48
0005h
Processor Mode Register 1
PM1
49
0006h
System Clock Control Register 0
CM0
76
0007h
System Clock Control Register 1
CM1
77
0008h
Chip Select Control Register
CSR
55
000Ah
Protect Register
PRCR
98
000Bh
Data Bank Register
DBR
67
000Ch
Oscillation Stop Detection Register
CM2
78
0009h
0010h
0015h
0048h
0049h
Program 2 Area Control Register
PRG2C
50
0011h
0012h
0047h
Peripheral Clock Select Register
Clock Prescaler Reset Flag
PCLKR
CPSRF
79
141
004Ah
Page
106
106
106
0054h
UART1 Receive Interrupt Control Register
S1RIC
105
0016h
0055h
Timer A0 Interrupt Control Register
TA0IC
105
0017h
0056h
Timer A1 Interrupt Control Register
TA1IC
105
0018h
Reset Source Determine Flag
RSTFR
46
0057h
Timer A2 Interrupt Control Register
TA2IC
105
0019h
Voltage Detection 2 Circuit Flag Register
VCR1
38
0058h
Timer A3 Interrupt Control Register
TA3IC
105
001Ah
VCR2
38
0059h
Timer A4 Interrupt Control Register
TA4IC
105
001Bh
Voltage Detection Circuit Operation Enable
Register
Chip Select Expansion Control Register
CSE
62
005Ah
Timer B0 Interrupt Control Register
TB0IC
105
001Ch
PLL Control Register 0
PLC0
80
005Bh
Timer B1 Interrupt Control Register
TB1IC
105
005Ch
Timer B2 Interrupt Control Register
TB2IC
105
001Eh
Processor Mode Register 2
PM2
79
005Dh
INT0 Interrupt Control Register
INT0IC
106
001Fh
Low Voltage Detection Interrupt Register
D4INT
39
005Eh
INT1 Interrupt Control Register
INT1IC
106
005Fh
INT2 Interrupt Control Register
INT2IC
106
0068h
0069h
DMA2 Interrupt Control Register
DM2IC
105
006Ah
DMA3 Interrupt Control Register
DM3IC
105
006Bh
U5BCNIC
105
S5TIC
105
001Dh
0020h
0060h
0021h
0061h
0022h
0062h
0023h
0063h
0024h
0064h
0025h
0065h
0026h
0066h
0027h
0067h
0028h
0029h
002Ah
Voltage Monitor 0 Circuit Control Register
VW0C
002Bh
40
002Dh
006Ch
UART5 BUS Collision Detection Interrupt Control
Register
UART5 Transmit Interrupt Control Register
002Eh
006Dh
UART5 Receive Interrupt Control Register
S5RIC
105
002Fh
006Eh
U6BCNIC
105
006Fh
UART6 BUS Collision Detection Interrupt
Control Register
UART6 Transmit Interrupt Control Register
S6TIC
105
0070h
UART6 Receive Interrupt Control Register
S6RIC
105
0071h
U7BCNIC
105
S7TIC
105
S7RIC
105
002Ch
0030h
0031h
0032h
0034h
0072h
UART7 BUS Collision Detection Interrupt
Control Register
UART7 Transmit Interrupt Control Register
0035h
0073h
UART7 Receive Interrupt Control Register
0036h
0074h
0037h
0075h
0038h
0076h
0039h
0077h
003Ah
0078h
003Bh
0079h
003Ch
007Ah
003Dh
007Bh
003Eh
007Ch
003Fh
007Dh
0040h
007Eh
0041h
007Fh
0033h
NOTE: 1. Blank columns are all reserved space. No access is allowed.
D080h to
D17Fh
B-1
Address
0180h
Register
DMA0 Source Pointer
Symbol
SAR0
Page
128
Address
01C3h
0181h
01C4h
0182h
01C5h
0183h
0184h
Register
Symbol
Page
01C6h
DMA0 Destination Pointer
DAR0
128
01C7h
0185h
01C8h
Timer B Count Source Select Register 0
TBCS0
157
0186h
01C9h
Timer B Count Source Select Register 1
TBCS1
157
0187h
01CAh
0188h
DMA0 Transfer Counter
TCR0
128
01CBh
0189h
01CCh
018Ah
01CDh
018Bh
018Ch
01CEh
DMA0 Control Register
DM0CON
128
01CFh
018Dh
01D0h
Timer A Count Source Select Register 0
TACS0
141
018Eh
01D1h
Timer A Count Source Select Register 1
TACS1
141
018Fh
01D2h
Timer A Count Source Select Register 2
TACS2
142
Timer A Waveform Output Function Select
Register
TAPOFS
0190h
DMA1 Source Pointer
SAR1
128
01D3h
0191h
01D4h
0192h
01D5h
0193h
0194h
DMA1 Destination Pointer
DAR1
128
01D6h
0195h
01D7h
0196h
01D8h
01D9h
0197h
0198h
DMA1 Transfer Counter
TCR1
128
01DAh
0199h
01DBh
019Ah
01DEh
01DCh
019Bh
019Ch
DMA1 Control Register
DM1CON
127
01DDh
019Dh
01DFh
019Eh
01E0h
01E1h
019Fh
01A0h
DMA2 Source Pointer
SAR2
128
01E2h
01A1h
01E3h
01A2h
01E4h
01E5h
01A3h
01A4h
142
DMA2 Destination Pointer
DAR2
128
01E6h
01A5h
01E7h
01A6h
01E8h
Timer B Count Source Select Register 2
TBCS2
157
01A7h
01E9h
Timer B Count Source Select Register 3
TBCS3
157
01A8h
DMA2 Transfer Counter
TCR2
128
01EAh
01A9h
01EBh
01AAh
01ECh
01EDh
01ABh
01ACh
DMA2 Control Register
DM2CON
127
01EEh
01ADh
01EFh
01AEh
01F0h
01F1h
01AFh
01B0h
DMA3 Source Pointer
SAR3
128
01F2h
01B1h
01F3h
01B2h
01F4h
01F5h
01B3h
01B4h
DMA3 Destination Pointer
DAR3
128
01F6h
01B5h
01F7h
01B6h
01F8h
01F9h
01B7h
01B8h
DMA3 Transfer Counter
TCR3
128
01FAh
01B9h
01FBh
01BAh
01FCh
01FDh
01BBh
01BCh
DMA3 Control Register
DM3CON
128
01FEh
01BDh
01FFh
01BEh
0200h
01BFh
0201h
01C0h
0202h
01C1h
0203h
01C2h
0204h
NOTE: 1. Blank columns are all reserved space. No access is allowed.
B-2
Address
0205h
Register
Interrupt Source Select Register 3
Symbol
IFSR3A
0206h
Interrupt Source Select Register 2
0207h
Interrupt Source Select Register
Page
114
Address
0249h
Register
UART0 Bit Rate Register
Symbol
U0BRG
Page
IFSR2A
114
024Ah
UART0 Transmit Buffer Register
U0TB
179
IFSR
113
024Bh
180
0208h
024Ch
UART0 Transmit/Receive Control Register 0
U0C0
181
0209h
024Dh
UART0 Transmit/Receive Control Register 1
U0C1
182
020Ah
024Eh
UART0 Receive Buffer Register
U0RB
UART Transmit/Receive Control Register 2
UCON
183
0254h
UART1 Special Mode Register 4
U1SMR4
185
0255h
UART1 Special Mode Register 3
U1SMR3
184
0256h
UART1 Special Mode Register 2
U1SMR2
184
0257h
UART1 Special Mode Register
U1SMR
183
0258h
UART1 Transmit/Receive Mode Register
U1MR
180
0259h
UART1 Bit Rate Register
U1BRG
180
025Ah
UART1 Transmit Buffer Register
U1TB
025Ch
UART1 Transmit/Receive Control Register 0
U1C0
180
025Dh
UART1 Transmit/Receive Control Register 1
U1C1
182
025Eh
UART1 Receive Buffer Register
U1RB
0264h
UART2 Special Mode Register 4
U2SMR4
185
0265h
UART2 Special Mode Register 3
U2SMR3
184
0266h
UART2 Special Mode Register 2
U2SMR2
184
0267h
UART2 Special Mode Register
U2SMR
183
0268h
UART2 Transmit/Receive Mode Register
U2MR
180
0269h
UART2 Bit Rate Register
U2BRG
180
026Ah
UART2 Transmit Buffer Register
U2TB
026Ch
UART2 Transmit/Receive Control Register 0
U2C0
181
026Dh
UART2 Transmit/Receive Control Register 1
U2C1
182
026Eh
UART2 Receive Buffer Register
U2RB
SI/O3 Transmit/Receive Register
S3TRR
224
0272h
SI/O3 Control Register
S3C
224
0273h
SI/O3 Bit Rate Register
S3BRG
224
0274h
SI/O4 Transmit/Receive Register
S4TRR
224
0276h
SI/O4 Control Register
S4C
224
0277h
SI/O4 Bit Rate Register
S4BRG
224
0278h
SI/O34 Control Register 2
S34C2
225
0284h
UART5 Special Mode Register 4
U5SMR4
185
0285h
UART5 Special Mode Register 3
U5SMR3
184
0286h
UART5 Special Mode Register 2
U5SMR2
184
0287h
UART5 Special Mode Register
U5SMR
183
0288h
UART5 Transmit/Receive Mode Register
U5MR
180
0289h
UART5 Bit Rate Register
U5BRG
180
020Bh
024Fh
020Ch
0250h
020Dh
020Eh
Address Match Interrupt Enable Register
AIER
117
020Fh
Address Match Interrupt Enable Register 2
AIER2
117
0210h
Address Match Interrupt Register 0
RMAD0
117
0211h
0212h
0213h
0214h
Address Match Interrupt Register 1
RMAD1
117
0215h
0216h
0217h
0218h
Address Match Interrupt Register 2
RMAD2
117
0219h
021Ah
021Bh
021Ch
Address Match Interrupt Register 3
RMAD3
117
021Dh
0251h
0252h
0253h
025Bh
025Fh
170
170
0260h
0261h
021Eh
0262h
021Fh
0220h
Flash Memory Control Register 0
FMR0
272
0221h
Flash Memory Control Register 1
FMR1
273
0222h
Flash Memory Control Register 2
FMR2
274
0223h
0224h
0225h
0226h
0227h
0263h
026Bh
0228h
0229h
022Ah
022Bh
026Fh
022Ch
0270h
022Dh
170
179
0271h
022Eh
022Fh
0230h
179
Flash Memory Control Register 6
FMR6
275
0231h
0275h
0232h
0233h
0234h
0235h
0279h
0236h
027Ah
0237h
027Bh
0238h
027Ch
0239h
027Dh
023Ah
027Eh
023Bh
027Fh
023Ch
0280h
023Dh
0281h
023Eh
0282h
023Fh
0283h
0240h
0241h
0242h
0243h
0244h
UART0 Special Mode Register 4
U0SMR4
185
0245h
UART0 Special Mode Register 3
U0SMR3
184
0246h
UART0 Special Mode Register 2
U0SMR2
184
0247h
UART0 Special Mode Register
U0SMR
183
0248h
UART0 Transmit/Receive Mode Register
U0MR
180
NOTE: 1. Blank columns are all reserved space. No access is allowed.
B-3
Address
028Ah
Register
UART5 Transmit Buffer Register
Symbol
U5TB
Page
031Bh
Timer B3 Mode Register
TB3MR
155
028Ch
UART5 Transmit/Receive Control Register 0
U5C0
181
031Ch
Timer B4 Mode Register
TB4MR
155
028Dh
UART5 Transmit/Receive Control Register 1
U5C1
182
031Dh
Timer B5 Mode Register
TB5MR
155
028Eh
UART5 Receive Buffer Register
U5RB
Count Start Flag
TABSR
156
179
028Bh
028Fh
170
Address
031Ah
Register
Symbol
Page
031Eh
031Fh
0290h
0320h
0291h
0321h
0292h
0322h
One-Shot Start Flag
ONSF
140
0293h
0323h
Trigger Select Register
TRGSR
140
Up/Down Flag
UDF
139
Timer A0 Register
TA0
152
Timer A1 Register
TA1
152
Timer A2 Register
TA2
152
Timer A3 Register
TA3
152
Timer A4 Register
TA4
152
Timer B0 Register
TB0
155
Timer B1 Register
TB1
155
Timer B2 Register
TB2
155
0294h
UART6 Special Mode Register 4
U6SMR4
185
0324h
0295h
UART6 Special Mode Register 3
U6SMR3
184
0325h
0296h
UART6 Special Mode Register 2
U6SMR2
184
0326h
0297h
UART6 Special Mode Register
U6SMR
183
0327h
0298h
UART6 Transmit/Receive Mode Register
U6MR
180
0328h
0299h
UART6 Bit Rate Register
U6BRG
180
0329h
029Ah
UART6 Transmit Buffer Register
U6TB
179
032Ah
032Bh
029Bh
029Ch
UART6 Transmit/Receive Control Register 0
U6C0
181
032Ch
029Dh
UART6 Transmit/Receive Control Register 1
U6C1
182
032Dh
029Eh
UART6 Receive Buffer Register
U6RB
179
032Eh
029Fh
032Fh
02A0h
0330h
02A1h
0331h
02A2h
0332h
02A3h
0333h
02A4h
UART7 Special Mode Register 4
U7SMR4
185
0334h
02A5h
UART7 Special Mode Register 3
U7SMR3
184
0335h
02A6h
UART7 Special Mode Register 2
U7SMR2
184
0336h
Timer A0 Mode Register
TA0MR
138
02A7h
UART7 Special Mode Register
U7SMR
183
0337h
Timer A1 Mode Register
TA1MR
138
02A8h
UART7 Transmit/Receive Mode Register
U7MR
180
0338h
Timer A2 Mode Register
TA2MR
138
02A9h
UART7 Bit Rate Register
U7BRG
180
0339h
Timer A3 Mode Register
TA3MR
138
02AAh
UART7 Transmit Buffer Register
U7TB
179
033Ah
Timer A4 Mode Register
TA4MR
138
033Bh
Timer B0 Mode Register
TB0MR
155
02ABh
02ACh
UART7 Transmit/Receive Control Register 0
U7C0
181
033Ch
Timer B1 Mode Register
TB1MR
155
02ADh
UART7 Transmit/Receive Control Register 1
U7C1
182
033Dh
Timer B2 Mode Register
TB2MR
155
02AEh
UART7 Receive Buffer Register
U7RB
179
033Eh
Timer B2 Special Mode Register
TB2SC
170
02AFh
033Fh
02B0h
0340h
to
0341h
02FFh
0300h
0342h
Timer B3,4,5 Count Start Flag
TBSR
156
Timer A1-1 Register
TA11
170
Timer A2-1 Register
TA21
170
Timer A4-1 Register
TA41
170
0308h
Three-Phase PWM Control Register 0
INVC0
167
034Bh
0309h
Three-Phase PWM Control Register 1
INVC1
168
034Ch
030Ah
Three-Phase Output Buffer Register 0
IDB0
169
034Dh
030Bh
Three-Phase Output Buffer Register 1
IDB1
169
034Eh
030Ch
Dead Time Timer
DTT
169
034Fh
030Dh
Timer B2 Interrupt Generation Frequency Set
Counter
ICTB2
0301h
0302h
0344h
0303h
0304h
169
Timer B3 Register
TB3
155
Timer B4 Register
TB4
155
Timer B5 Register
TB5
155
0311h
0313h
0315h
0316h
0317h
0318h
0319h
0350h
0351h
0352h
030Fh
0314h
0349h
034Ah
030Eh
0312h
0347h
0348h
0307h
0310h
0345h
0346h
0305h
0306h
0343h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
NOTE: 1. Blank columns are all reserved space. No access is allowed.
B-4
Address
035Ch
Register
Symbol
Page
Address
03A0h
035Dh
03A1h
035Eh
03A2h
035Fh
Pull-Up Control Register 0
PUR0
258
03A4h
0361h
Pull-Up Control Register 1
PUR1
258
03A5h
0362h
Pull-Up Control Register 2
PUR2
259
03A6h
0363h
03A7h
0364h
03A8h
0365h
Page
03A9h
Port Control Register
PCR
259
03AAh
0367h
03ABh
0368h
03ACh
0369h
03ADh
036Ah
03AEh
036Bh
03AFh
036Ch
03B0h
036Dh
03B1h
036Eh
03B2h
036Fh
03B3h
0370h
03B4h
0371h
03B5h
0372h
03B6h
0373h
03B7h
0374h
03B8h
0375h
03B9h
0376h
03BAh
0377h
03BBh
0378h
03BCh
0379h
03BDh
037Ah
03BEh
037Bh
03BFh
037Ch
Count Source Protection Mode Register
CSPR
120
03C0h
037Dh
Watchdog Timer Reset Register
WDTR
119
03C1h
037Eh
Watchdog Timer Start Register
WDTS
119
03C2h
037Fh
Watchdog Timer Control Register
WDC
119
03C3h
0380h
03C4h
0381h
03C5h
0382h
03C6h
0383h
03C7h
0384h
03C8h
0385h
03C9h
0386h
03CAh
0387h
03CBh
0388h
03CCh
0389h
03CDh
038Ah
03CEh
038Bh
03CFh
038Ch
03D0h
038Dh
03D1h
038Eh
03D2h
CRC Data Register
CRCD
248
CRC Input Register
CRCIN
248
A/D Register 0
AD0
233
A/D Register 1
AD1
233
A/D Register 2
AD2
233
A/D Register 3
AD3
233
A/D Register 4
AD4
233
A/D Register 5
AD5
233
A/D Register 6
AD6
233
A/D Register 7
AD7
233
A/D Control Register 2
ADCON2
233
03D3h
038Fh
0390h
Symbol
03A3h
0360h
0366h
Register
DMA2 Source Select Register
DM2SL
125
03D4h
03D5h
0391h
03D6h
A/D Control Register 0
ADCON0
232
0393h
03D7h
A/D Control Register 1
ADCON1
232
0394h
03D8h
D/A0 Register
DA0
247
0395h
03D9h
0396h
03DAh
D/A1 Register
DA1
247
0397h
03DBh
D/A Control Register
DACON
247
0392h
0398h
DMA3 Source Select Register
DMA0 Source Select Register
DM3SL
DM0SL
125
125
039Ah
03DCh
03DDh
0399h
DMA1 Source Select Register
DM1SL
125
03DEh
039Bh
03DFh
039Ch
03E0h
Port P0 Register
P0
257
039Dh
03E1h
Port P1 Register
P1
257
039Eh
03E2h
Port P0 Direction Register
PD0
256
039Fh
03E3h
Port P1 Direction Register
PD1
256
NOTE: 1. Blank columns are all reserved space. No access is allowed.
B-5
Address
03E4h
Port P2 Register
Register
P2
Symbol
Page
257
03E5h
Port P3 Register
P3
257
03E6h
Port P2 Direction Register
PD2
256
03E7h
Port P3 Direction Register
PD3
256
03E8h
Port P4 Register
P4
257
03E9h
Port P5 Register
P5
257
03EAh
Port P4 Direction Register
PD4
256
03EBh
Port P5 Direction Register
PD5
256
03ECh
Port P6 Register
P6
257
03EDh
Port P7 Register
P7
257
03EEh
Port P6 Direction Register
PD6
256
03EFh
Port P7 Direction Register
PD7
256
03F0h
Port P8 Register
P8
257
03F1h
Port P9 Register
P9
257
03F2h
Port P8 Direction Register
PD8
256
03F3h
Port P9 Direction Register
PD9
256
03F4h
Port P10 Register
P10
257
Port P10 Direction Register
PD10
256
Optional Feature Select Address
OFS1
269
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
D000h
to
D7FFh
OFS1
NOTE: 1. Blank columns are all reserved space. No access is allowed.
B-6
TABLE OF CONTENTS
SFR Page Reference .......................................................................................................B-1
1.
Overview .................................................................................................. 1
1.1
Features .............................................................................................................. 1
1.1.1
2.
Applications .................................................................................................. 1
1.2
Specifications ...................................................................................................... 2
1.3
Product List ........................................................................................................ 4
1.4
Block Diagram ..................................................................................................... 6
1.5
Pin Assignments.................................................................................................. 7
1.6
Pin Functions..................................................................................................... 11
Central Processing Unit (CPU)............................................................... 14
2.1
Data Registers (R0, R1, R2 and R3)................................................................. 14
2.2
Address Registers (A0 and A1)......................................................................... 15
2.3
Frame Base Registers (FB)............................................................................... 15
2.4
Interrupt Table Register (INTB) ......................................................................... 15
2.5
Program Counter (PC) ...................................................................................... 15
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ............................. 15
2.7
Static Base Register (SB).................................................................................. 15
2.8
Flag Register (FLG)........................................................................................... 15
2.8.1
Carry Flag (C Flag)..................................................................................... 15
2.8.2
Debug Flag (D Flag) ................................................................................... 15
2.8.3
Zero Flag (Z Flag)....................................................................................... 15
2.8.4
Sign Flag (S Flag)....................................................................................... 15
2.8.5
Register Bank Select Flag (B Flag) ............................................................ 15
2.8.6
Overflow Flag (O Flag) ............................................................................... 15
2.8.7
Interrupt Enable Flag (I Flag)...................................................................... 15
2.8.8
Stack Pointer Select Flag (U Flag) ............................................................. 16
2.8.9
Processor Interrupt Priority Level (IPL) ...................................................... 16
2.8.10
Reserved Space ......................................................................................... 16
1- 1
3.
Memory .................................................................................................. 17
4.
Special Function Registers (SFRs) ........................................................ 18
5.
Reset ...................................................................................................... 32
5.1
6.
7.
8.
Hardware Reset 1 ............................................................................................. 32
5.1.1
Reset on a Stable Supply Voltage .............................................................. 32
5.1.2
Power-on Reset.......................................................................................... 32
5.2
Brown-out Reset................................................................................................ 35
5.3
Software Reset.................................................................................................. 35
5.4
Watchdog Timer Reset...................................................................................... 35
5.5
Oscillation Stop Detection Reset ....................................................................... 35
5.6
Internal Space ................................................................................................... 36
Voltage Detection Circuit ........................................................................ 37
6.1
Brown-out Reset................................................................................................ 41
6.2
Low Voltage Detection Interrupt ........................................................................ 42
6.3
Limitations on Exiting Stop Mode ...................................................................... 44
6.4
Limitations on Exiting Wait Mode ...................................................................... 44
6.5
Cold Start-up / Warm Start-up Discrimination.................................................... 45
Processor Mode ..................................................................................... 47
7.1
Types of Processor Mode.................................................................................. 47
7.2
Setting Processor Modes .................................................................................. 47
7.3
Internal Memory ................................................................................................ 51
Bus ......................................................................................................... 53
8.1
Bus Mode .......................................................................................................... 53
8.1.1
Separate Bus.............................................................................................. 53
8.1.2
Multiplexed Bus .......................................................................................... 53
8.2
Bus Control........................................................................................................ 54
8.2.1
Address Bus ............................................................................................... 54
8.2.2
Data Bus..................................................................................................... 54
8.2.3
Chip Select Signal ...................................................................................... 54
8.2.4
Read and Write Signals.............................................................................. 57
8.2.5
ALE Signal.................................................................................................. 57
8.2.6
RDY Signal ................................................................................................. 58
1- 2
9.
8.2.7
HOLD Signal............................................................................................... 59
8.2.8
BCLK Output .............................................................................................. 59
8.2.9
External Bus Status When Internal Area IS Accessed ............................... 61
8.2.10
Software Wait ............................................................................................. 61
Memory Space Expansion Function ....................................................... 66
9.2
4-Mbyte Mode ................................................................................................... 66
9.2.1
Addresses 04000h to 3FFFFh, C0000h to FFFFFh ................................... 66
9.2.2
Addresses 40000h to BFFFFh ................................................................... 66
10. Clock Generation Circuit ........................................................................ 74
10.1
Type of the Clock Generation Circuit................................................................. 74
10.1.1
Main Clock.................................................................................................. 81
10.1.2
Sub Clock ................................................................................................... 82
10.1.3
125 kHz On-Chip Oscillator Clock (fOCO-S).............................................. 83
10.1.4
PLL Clock ................................................................................................... 83
10.2
CPU Clock and Peripheral Function Clock........................................................ 86
10.2.1
CPU Clock and BCLK................................................................................. 86
10.2.2
Peripheral Function Clock (f1, fC32) .......................................................... 87
10.3
Clock Output Function....................................................................................... 87
10.4
Power Control.................................................................................................... 88
10.4.1
Normal Operating Mode ............................................................................. 88
10.4.2
Wait Mode .................................................................................................. 90
10.4.3
Stop Mode .................................................................................................. 92
10.5
System Clock Protection Function .................................................................... 95
10.6
Oscillation Stop and Re-Oscillation Detect Function ......................................... 96
10.6.1
Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) ............. 96
10.6.2
Operation When CM27 bit = 1 (Oscillation Stop and
Re-oscillation Detect Interrupt) ................................................................... 96
10.6.3
How to Use Oscillation Stop and Re-Oscillation Detect Function............... 97
11. Protection ............................................................................................... 98
12. Interrupt .................................................................................................. 99
12.1
Type of Interrupts .............................................................................................. 99
12.2
Software Interrupts .......................................................................................... 100
12.2.1
Undefined Instruction Interrupt ................................................................. 100
1- 3
12.2.2
Overflow Interrupt ..................................................................................... 100
12.2.4
INT Instruction Interrupt............................................................................ 100
12.3
Hardware Interrupts......................................................................................... 101
12.3.1
Special Interrupts...................................................................................... 101
12.3.2
Peripheral Function Interrupts .................................................................. 101
12.4
Interrupts and Interrupt Vector......................................................................... 102
12.4.1
Fixed Vector Tables .................................................................................. 102
12.4.2
Relocatable Vector Tables ........................................................................ 103
12.5
Interrupt Control .............................................................................................. 105
12.5.1
I Flag......................................................................................................... 107
12.5.2
IR Bit......................................................................................................... 107
12.5.3
Bits ILVL2 to ILVL0 and IPL ...................................................................... 107
12.5.4
Interrupt Sequence ................................................................................... 108
12.5.5
Interrupt Response Time .......................................................................... 109
12.5.6
Variation of IPL when Interrupt Request IS Accepted .............................. 109
12.5.7
Saving Registers ...................................................................................... 110
12.5.8
Returning from an Interrupt Routine ..........................................................111
12.5.9
Interrupt Priority .........................................................................................111
12.5.10 Interrupt Priority Level Select Circuit .........................................................111
12.6
INT Interrupt .................................................................................................... 113
12.7
NMI Interrupt ................................................................................................... 115
12.8
Key Input Interrupt........................................................................................... 115
12.9
Address Match Interrupt .................................................................................. 116
13. Watchdog Timer ................................................................................... 118
13.1
Count Source Protection Mode Disabled ........................................................ 121
13.2
Count Source Protection Mode Enabled ......................................................... 122
14. DMAC................................................................................................... 123
14.1
Transfer Cycles ............................................................................................... 129
14.1.1
Effect of Source and Destination Addresses ............................................ 129
14.1.2
Effect of BYTE Pin Level .......................................................................... 129
14.1.3
Effect of Software Wait ............................................................................. 129
14.1.4
Effect of RDY Signal................................................................................. 129
14.2
DMA Transfer Cycles ...................................................................................... 131
14.3
DMA Enabled .................................................................................................. 132
1- 4
14.4
DMA Request .................................................................................................. 132
14.5
Channel Priority and DMA Transfer Timing..................................................... 133
15. Timers.................................................................................................. 134
15.1
Timer A ............................................................................................................ 137
15.1.1
Timer Mode .............................................................................................. 143
15.1.2
Event Counter Mode................................................................................. 144
15.1.3
One-Shot Timer Mode .............................................................................. 149
15.1.4
Pulse Width Modulation (PWM) Mode...................................................... 151
15.2
Timer B ............................................................................................................ 154
15.2.1
Timer Mode .............................................................................................. 158
15.2.2
Event Counter Mode................................................................................. 160
15.2.3
Pulse Period and Pulse Width Measurement Modes ............................... 162
16. Three-Phase Motor Control Timer Function ......................................... 165
17. Serial Interface ..................................................................................... 175
17.1
UARTi (i = 0 to 2, 5 to 7).................................................................................. 175
17.1.1
Clock Synchronous Serial I/O Mode......................................................... 186
17.1.2
Clock Asynchronous Serial I/O (UART) Mode.......................................... 194
17.1.3
Special Mode 1 (I2C mode) ...................................................................... 202
17.1.4
Special Mode 2 ......................................................................................... 212
17.1.5
Special Mode 3 (IE mode) ........................................................................ 216
17.1.6
Special Mode 4 (SIM Mode) (UART2) ...................................................... 218
17.2
SI/O3 and SI/O4 .............................................................................................. 223
17.2.1
SI/Oi Operation Timing ............................................................................. 227
17.2.2
CLK Polarity Selection.............................................................................. 227
17.2.3
Functions for Setting an SOUTi Initial Value............................................. 228
17.2.4
Functions for Selecting SOUTi State after Transmission.......................... 229
18. A/D Converter....................................................................................... 230
18.1
Mode Description ............................................................................................ 234
18.1.1
One-Shot Mode ........................................................................................ 234
18.1.2
Repeat Mode ............................................................................................ 236
18.1.3
Single Sweep Mode.................................................................................. 238
18.1.4
Repeat Sweep Mode 0 ............................................................................. 240
18.1.5
Repeat Sweep Mode 1 ............................................................................. 242
1- 5
18.2
Conversion Rate.............................................................................................. 244
18.3
Extended Analog Input Pins ............................................................................ 244
18.4
Current Consumption Reducing Function ....................................................... 244
18.5
Output Impedance of Sensor under A/D Conversion ...................................... 245
19. D/A Converter....................................................................................... 246
19.1
Summary ......................................................................................................... 246
20. CRC Operation..................................................................................... 248
21. Programmable I/O Ports....................................................................... 250
21.1
Port Pi Direction Register (PDi Register, i = 0 to 10)....................................... 250
21.2
Port Pi Register (Pi Register, i = 0 to 10) ........................................................ 250
21.3
Pull-up Control Register 0 to Pull-up Control Register 2 (Registers
PUR0 to PUR2) ............................................................................................... 250
21.4
Port Control Register (PCR Register) ............................................................. 250
22. Flash Memory Version.......................................................................... 263
22.1
Memory Map ................................................................................................... 264
22.1.1
Boot Mode ................................................................................................ 265
22.1.2
User Boot Function................................................................................... 265
22.2
Functions to Prevent Flash Memory from Rewriting ....................................... 267
22.2.1
ROM Code Protect Function .................................................................... 267
22.2.2
ID Code Check Function .......................................................................... 267
22.2.3
Forced Erase Function ............................................................................. 268
22.2.4
Standard Serial I/O Mode Disable Function ............................................. 268
22.3
CPU Rewrite Mode.......................................................................................... 270
22.3.1
EW0 Mode................................................................................................ 271
22.3.2
EW1 Mode................................................................................................ 271
22.3.3
Flash Memory Control Register (Registers FMR0, FMR1, FMR2 and
FMR6)....................................................................................................... 271
22.3.4
Precautions on CPU Rewrite Mode.......................................................... 282
22.3.5
Software Commands ................................................................................ 284
22.3.6
Data Protect Function............................................................................... 290
22.3.7
Status Register ......................................................................................... 290
22.3.8
Full Status Check...................................................................................... 292
22.4
Standard Serial I/O Mode ................................................................................ 294
1- 6
22.4.1
ID Code Check Function .......................................................................... 294
22.4.2
Example of Circuit Application in the Standard Serial I/O Mode............... 298
22.5
Parallel I/O Mode............................................................................................. 300
22.5.1
ROM Code Protect Function .................................................................... 300
23. Electrical Characteristics ...................................................................... 301
23.1
Electrical Characteristics ................................................................................. 301
24. Precautions .......................................................................................... 341
24.1
SFR ................................................................................................................. 341
24.1.1
24.2
Register Settings ...................................................................................... 341
Reset ............................................................................................................... 342
24.2.1
VCC1 ........................................................................................................ 342
24.2.2
CNVSS ..................................................................................................... 342
24.3
Bus .................................................................................................................. 343
24.4
PLL Frequency Synthesizer ............................................................................ 344
24.5
Power Control.................................................................................................. 345
24.6
Protect ............................................................................................................. 347
24.7
Interrupt ........................................................................................................... 348
24.7.1
Reading address 00000h ......................................................................... 348
24.7.2
SP Setting................................................................................................. 348
24.7.3
NMI Interrupt............................................................................................. 348
24.7.4
Changing an Interrupt Generate Factor.................................................... 349
24.7.5
INT Interrupt ............................................................................................. 349
24.7.6
Rewriting the Interrupt Control Register ................................................... 350
24.7.7
Watchdog Timer Interrupt ......................................................................... 351
24.8
DMAC.............................................................................................................. 352
24.8.1
24.9
Write to the DMAE Bit in the DMiCON Register (i = 0 to 3)...................... 352
Timers ............................................................................................................. 353
24.9.1
Timer A ..................................................................................................... 353
24.9.2
Timer B ..................................................................................................... 357
24.10 Serial Interface ................................................................................................ 360
24.10.1 Clock Synchronous Serial I/O................................................................... 360
24.10.2 UART (Clock Asynchronous Serial I/O) Mode.......................................... 362
24.10.3 Special Mode 1 (I2C Mode) ...................................................................... 362
24.10.4 Special Mode 4 (SIM Mode) ..................................................................... 362
1- 7
24.10.5 SI/O3, SI/O4 ............................................................................................. 363
24.11 A/D Converter.................................................................................................. 364
24.12 Programmable I/O Ports.................................................................................. 366
24.13 Flash Memory Version..................................................................................... 367
24.13.1 Functions to Inhibit Rewriting Flash Memory............................................ 367
24.13.2 Stop Mode ................................................................................................ 367
24.13.3 Wait Mode ................................................................................................ 367
24.13.4 Low Power Consumption Mode,
On-Chip Oscillator Low Power Consumption Mode ................................. 367
24.13.5 Writing Command and Data ..................................................................... 367
24.13.6 Program Command .................................................................................. 367
24.13.7 Lock Bit Program Command .................................................................... 367
24.13.8 Operation Speed....................................................................................... 368
24.13.9 Instructions Inhibited against Use............................................................. 368
24.13.10 Interrupts .................................................................................................. 368
24.13.11 How to Access.......................................................................................... 368
24.13.12 Writing in the User ROM Area .................................................................. 368
24.13.13 DMA transfer ............................................................................................ 368
24.13.14 Programming / Erasing Endurance and Execution Time.......................... 369
24.14 Noise ............................................................................................................... 370
Appendix 1.Package Dimensions ................................................................ 371
Register Index
Appendix 1-372
1- 8
PRELIMINARY
M16C/64 Group
RENESAS MCU
1.
Overview
1.1
Features
The M16C/64 Group MCUs incorporate the M16C/60 Series CPU core and flash memory, employing
sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space (expandable to 4
Mbyte), this MCU is capable of executing instructions at high speed. In addiditon, the CPU core boasts a
multiplier for high-speed operation processing.
Power consumption is low, and the M16C/64 Group supports operating modes that allow additional power
control. The MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and
is designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and
serial interface, reduces the number of system components.
1.1.1
Applications
Audio, cameras, television, home appliance, office equipment, communication equipment, portable
equipment, industrial equipment, etc.
REJ09B0392-0064 Rev.0.64
Page 1 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1.2
1. Overview
Specifications
Tables 1.1 and 1.2 list Specifications Outline.
Table 1.1
Specifications (1)
Item
Function
Specification
CPU
Central processing unit
M16C/60 core (multiplier: 16-bit × 16-bit ! 32 bits,
multiply and accumulate instruction: 16 × 16 + 32 !32 bits)
• Number of basic instructions: 91
• Minimum instruction execution time:
40.0 ns ( f(BCLK) = 25 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)
• Operating modes: Single-chip, memory expansion, and microprocessor
Memory
ROM, RAM,
data flash
See Table 1.3 Product List.
Voltage
Detection
Voltage detection circuit
Low-voltage detection unit
Clock
Clock generation circuit
• 4 circuits: Main clock, sub clock, on-chip oscillator (125 kHz), PLL
• Oscillation stop detection: Main clock oscillation stop detection and reoscillation detection function
• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8 and 16
• Low-power consumption modes: Wait mode, stop mode
External Bus Bus and memory expansion
Expansion
• Address space: 1 Mbyte
• External bus interface: 0 to 3 waits states, chip select 4 outputs, memory area expansion function (up to 4 Mbytes), 3 V, 5 V interface
• Bus format: Separate bus or multiplexed bus selectable, data bus
width selectable (8 or 16 bits), number of address buses selectable
(12, 16, or 20 buses)
I/O Ports
• CMOS I/O ports: 85, selectable pull-up resistor
• Nch open drain ports: 3
Programmable I/O ports
Interrupts
• Interrupt vectors: 70
• External interrupt input: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
Watchdog Timer
15 bits × 1 (with prescaler)
Automatic reset start function selectable
DMA
DMAC
Timer
Timer A
16-bit timer × 5
Timer mode, event counter mode, one shot timer mode, pulse width
modulation (PWM) mode
Event counter two-phase pulse signal processing (two-phase encoder
input) × 3 channels
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement mode,
pulse width measurement mode
Timer functions for threephase motor control
Three-phase inverter control (timer A1, timer A2, timer A4, timer B2),
On-chip dead time timer
UART0 to UART2, UART5 to
UART7
Clock synchronous/asynchronous × 6 channels
I2C-bus, IEBus (1), special mode 2, SIM (UART2)
SI/O3, SI/O4
Clock synchronization only × 2 channels
Serial Interface
• 4 channels, cycle steal mode
• Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)
NOTE:
1. IEBus is a registered trademark of NEC Electronics Corporation.
REJ09B0392-0064 Rev.0.64
Page 2 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 1.2
1. Overview
Specifications (2)
Item
Function
Specification
A/D Converter
10-bit resolution × 26 channels, including sample and hold function,
Conversion time: 1.72 µs
D/A Converter
8-bit resolution × 2
CRC Calculation Circuit
CRC-CCITT (X16 + X12 + X5 + 1) compliant
Flash Memory
Programming and erasure power supply voltage: 2.7 V to 5.5 V
Programming and erasure endurance: 100 times
Program security: ROM code protect, ID code check
Debug Function
Functions on-chip debug, on-board flash rewrite function, address match × 4
Operation Frequency/Supply Voltage
25 MHz/VCC1 = VCC2 = 2.7 to 5.5 V
Power Consumption
20 mA (25 MHz/VCC1 = VCC2 = 3 V)
3.0 µA(VCC1 = VCC2 = 3 V, in stop mode)
Operating Temperature
-20°C to 85°C, -40°C to 85°C
Package
100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A)
100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)
REJ09B0392-0064 Rev.0.64
Page 3 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1.3
1. Overview
Product List
Table 1.3 lists product information. Figure 1.1 shows part numbers, memory sizes, and packages.
Table 1.3
Product List
ROM Capacity
Part No.
R5F36406NFA
R5F36406NFB
R5F3640DNFA
R5F3640DNFB
R5F3640MNFA
R5F3640MNFB
R5F36406DFA
R5F36406DFB
R5F3640DDFA
R5F3640DDFB
R5F3640MDFA
R5F3640MDFB
Program
ROM 1
RAM
Program
Data Flash Capacity
ROM 2
Package Code
Remarks
(D) 128 Kbytes 16 Kbytes 4 Kbytes
12 Kbytes PRQP0100JD-B Operating
×
2
blocks
(D)
PLQP0100KB-A temperature
-20°C to 85°C
(D) 256 Kbytes 16 Kbytes 4 Kbytes
16 Kbytes PRQP0100JD-B
× 2 blocks
(D)
PLQP0100KB-A
(D) 512 Kbytes 16 Kbytes 4 Kbytes
31 Kbytes PRQP0100JD-B
×
2
blocks
(D)
PLQP0100KB-A
(D) 128 Kbytes 16 Kbytes 4 Kbytes
12 Kbytes PRQP0100JD-B Operating
×
2
blocks
(D)
PLQP0100KB-A temperature
-40°C to 85°C
(D) 256 Kbytes 16 Kbytes 4 Kbytes
16 Kbytes PRQP0100JD-B
× 2 blocks
(D)
PLQP0100KB-A
(D) 512 Kbytes 16 Kbytes 4 Kbytes
31 Kbytes PRQP0100JD-B
×
2
blocks
(D)
PLQP0100KB-A
(D) : Under development
NOTE:
1. Previous package codes are as follows.
PRQP0100JD-B: 100P6F-A, PLQP0100KB-A: 100P6Q-A
Part No. R 5 F 3
640
6
D
FA
Package type:
FA: Package PRQP0100JD-B (100P6F-A)
FB: Package PLQP0100KB-A (100P6Q-A)
Property Code
N: Operating temperature -20°C to 85°C
D: Operating temperature -40°C to 85°C
Memory capacity
Program ROM 1 / RAM
6: 128 Kbytes / 12 Kbytes
D: 256 Kbytes / 16 Kbytes
M: 512 Kbytes / 31 Kbytes
M16C / 64 Group
16-bit microcomputer
Memory type:
F: Flash memory
Renesas microcomputer
Renesas semiconductor
Figure 1.1
Correspondence of Part No., with Memory Size and Package
REJ09B0392-0064 Rev.0.64
Page 4 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1. Overview
M1 6 C
R 5 F 3 6 4 0 6 DF A
XXXXXXX
Figure 1.2
Part No. (See Figure 1.1 Correspondence of Part No.,
with Memory Size and Package )
Date code seven digits
Marking Diagram of Flash Memory Version (Top View)
REJ09B0392-0064 Rev.0.64
Page 5 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1.4
1. Overview
Block Diagram
Figure 1.3 is a M16C/64 Group Block Diagram.
8
8
Port P0
Port P1
8
8
Port P3
Port P2
8
8
Port P4
Port P5
VCC2 ports
Internal peripheral functions
Timer (16-bit)
Outputs (Timer A): 5
Inputs (Timer B): 6
Clock generation circuits
UART or
clock synchronous serial I/O
(6 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
Clock synchronous serial I/O
(8 bits × 2 channels)
DMAC
(4 channels)
Three-phase motor control circuit
CRC calculation circuit (CCITT)
(Polynomial X16 + X12 + X5 + 1)
Watchdog timer
(15 bits)
A/D converter
(10 bits × 26 channels)
Memory
M16C/60 Series CPU core
R0H
R1H
D/A converter
(8 bits × 2 channels)
R0L
R1L
R2
R3
A0
A1
FB
SB
USP
ISP
Port P9
8
Port P8
8
NOTES :
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3
Block Diagram
REJ09B0392-0064 Rev.0.64
Page 6 of 373
Oct 12, 2007
Port P7
8
RAM (2)
INTB
PC
FLG
VCC1 ports
Port P10
8
ROM (1)
Port P6
8
Multiplier
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1.5
1. Overview
Pin Assignments
Figures 1.4 and 1.5 show pin assignments (top view).
53
52
51
55
54
58
57
56
61
60
59
64
63
62
66
65
69
68
67
71
70
72
76
75
74
73
81
50
VCC2 ports
82
83
84
85
86
49
48
47
46
45
M16C/64 Group
87
88
89
90
44
43
42
41
40
PRQP0100JD-B
(100P6F-A)
(top view)
91
92
93
94
95
96
97
98
39
38
37
36
35
34
33
VCC1 ports
99
32
31
30
29
27
28
26
25
24
21
22
23
20
19
18
17
16
14
15
12
13
11
9
10
8
7
6
4
5
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD(1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN(1)
P7_0/TXD2/SDA2/TA0OUT(1)
2
3
100
1
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
79
78
77
80
P1_0/CTS6/RTS6/D8
P1_1/CLK6/D9
P1_2/RXD6/SCL6/D10
P1_3/TXD6/SDA6/D11
P1_4/D12
P1_5/INT3/D13
P1_6/INT4/D14
P1_7/INT5/D15
P2_0/AN2_0/A0, [A0/D0], A0
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]
P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]
P2_7/AN2_7/A7, [A7/D7], [A7/D6]
VSS
P3_0/A8 [A8/D7]
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
(3)
NOTES:
1. N-channel open-drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Symbols in brackets [ ] represent a functional signal as a whole.
Figure 1.4
Pin Assignment (Top View)
REJ09B0392-0064 Rev.0.64
Page 7 of 373
Oct 12, 2007
P4_4/CTS7/RTS7/CS0
P4_5/CLK7/CS1
P4_6/RXD7/SCL7/CS2
P4_7/TXD7/SDA7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1. Overview
76
77
61
60
59
58
57
56
55
54
53
52
51
50
49
VCC2 ports
78
79
80
81
82
83
48
47
46
M16C/64 Group
84
85
86
87
88
34
33
32
31
30
99
29
28
27
100
26
20
21
22
23
24
25
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4
5
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI/SD(1)
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
2
3
VCC1 ports
NOTES:
1. N-channel open-drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Symbols in brackets [ ] represent a functional signal as a whole.
Figure 1.5
42
41
37
36
35
93
94
95
96
97
98
45
44
43
40
39
38
PLQP0100KB-A
(100P6Q-A)
(top view)
89
90
91
92
1
P1_2/RXD6/SCL6/D10
P1_1/CLK6/D9
P1_0/CTS6/RTS6/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
64
63
62
75
74
73
72
71
70
69
68
67
66
65
P1_3/TXD6/SDA6/D11
P1_4/D12
P1_5/INT3/D13
P1_6/INT4/D14
P1_7/INT5/D15
P2_0/AN2_0/A0, [A0/D0], A0
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]
P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]
P2_7/AN2_7/A7, [A7/D7], [A7/D6]
VSS
P3_0/A8 [A8/D7]
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
(3)
Pin Assignment (Top View)
REJ09B0392-0064 Rev.0.64
Page 8 of 373
Oct 12, 2007
P4_2/A18
P4_3/A19
P4_4/CTS7/RTS7/CS0
P4_5/CLK7/CS1
P4_6/RXD7/SCL7/CS2
P4_7/TXD7/SDA7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT(1)
P7_1/RXD2/SCL2/TA0IN/TB5IN(1)
P7_2/CLK2/TA1OUT/V
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 1.4
Pin No.
FA FB
1
99
2
100
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10 8
11 9
12 10
13
14
15
16
17
11
12
13
14
15
18
1. Overview
Pin Names, for 100-Pin Package(1)
Control Pin
Port
Interrupt
Pin
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
BYTE
CNVSS
XCIN
XCOUT
Timer Pin
UART Pin
SOUT4
CLK4
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
Analog Pin
Bus Control Pin
ANEX1
ANEX0
DA1
DA0
SOUT3
SIN3
CLK3
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
P8_5
NMI
16
P8_4
INT2
19
17
P8_3
INT1
20
18
P8_2
INT0
21
19
P8_1
22
23
24
25
20
21
22
23
P8_0
P7_7
P7_6
P7_5
26
27
24
25
P7_4
P7_3
28
29
30
31
32
33
34
26
27
28
29
30
31
32
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
P6_4
35
36
37
38
33
34
35
36
P6_3
P6_2
P6_1
P6_0
39
37
P5_7
40
41
38
39
P5_6
P5_5
42
43
44
40
41
42
P5_4
P5_3
P5_2
45
43
P5_1
46
44
P5_0
47
45
P4_7
TXD7/SDA7
CS3
48
46
P4_6
RXD7/SCL7
CS2
49
47
P4_5
CLK7
CS1
50
48
P4_4
CTS7/RTS7
CS0
REJ09B0392-0064 Rev.0.64
Page 9 of 373
SD
ZP
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
CTS5/RTS5
RXD5/SCL5
CLK5
TXD5/SDA5
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
CTS1/RTS1/CTS0/
CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
CTS0/RTS0
RDY/CLKOUT
ALE
HOLD
HLDA
BCLK
RD
WRH/BHE
WRL/WR
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 1.5
1. Overview
Pin Names for 100-Pin Package(2)
Pin No.
Control
FA FB
Pin
51
49
52
50
53
51
54
52
55
53
56
54
57
55
58
56
59
57
60
58
61
59
62
60
VCC2
63
61
64
62
VSS
65
63
66
64
67
65
Port
Interrupt
Pin
Timer Pin
UART Pin
Analog Pin
P2_7
P2_6
P2_5
68
66
P2_4
69
70
71
72
73
67
68
69
70
71
P2_3
P2_2
P2_1
P2_0
P1_7
74
72
P1_6
75
73
P1_5
76
77
78
79
80
74
75
76
77
78
P1_4
P1_3
P1_2
P1_1
P1_0
81
82
83
84
85
86
87
88
89
79
80
81
82
83
84
85
86
87
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN7
90
88
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7 KI3
P10_6 KI2
91
89
AN5
92
90
P10_5 KI1
P10_4 KI0
93
94
95
96
97
98
99
100
91
92
93
94
95
96
97
98
P10_3
P10_2
P10_1
AN3
AN2
AN1
P10_0
AN0
Bus Control Pin
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
P3_0
A8, [A8/D7]
INT7
AN2_7
AN2_6
AN2_5
A7, [A7/D7], [A7/D6]
A6, [A6/D6], [A6/D5]
A5, [A5/D5], [A5/D4]
INT6
AN2_4
A4, [A4/D4], [A4/D3]
AN2_3
AN2_2
AN2_1
AN2_0
INT5
A3, [A3/D3], [A3/D2]
A2, [A2/D2], [A2/D1]
A1, [A1/D1], [A1/D0]
A0, [A0/D0], A0
D15
INT4
D14
INT3
D13
D12
D11
D10
D9
D8
TXD6/SDA6
RXD6/SCL6
CLK6
CTS6/RTS6
AN6
AN4
AVSS
VREF
AVCC
P9_7
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SIN4
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ADTRG
D7
D6
D5
D4
D3
D2
D1
D0
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
1.6
1. Overview
Pin Functions
Table 1.6
Pin Functions (1)
Signal Name
Pin Name
I/O
Power Supply
Description
Power supply
input
VCC1
VCC2
VSS
I
-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 =VCC2)
and 0 V to the VSS pin (1)
Analog power
supply input
AVCC
AVSS
I
VCC1
Apply the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
Reset input
RESET
I
VCC1
Low active input pin. Driving this pin Low resets the MCU.
CNVSS
CNVSS
I
VCC1
Input pin to switch processor mode. To start up in single-chip
mode after a reset, connect the CNVSS pin to VSS via
resister. To start up in microprocessor mode, connect the
CNVSS pin to VSS1.
External data
bus width
select input
BYTE
I
VCC1
Input pin to select the data bus of the external memory area.
The data bus is 16-bit when it is Low and 8-bit when it is
High. This pin must be fixed either High or Low. Connect the
BYTE pin to VSS in single-chip mode
Bus control
pins
D0 to D7
I/O
VCC2
Inputs or outputs data (D0 to D7) while accessing an external memory area with separate bus
D8 to D15
I/O
VCC2
Inputs or outputs data (D8 to D15) while accessing an external memory area with 16-bit separate bus
A0 to A19
O
VCC2
Outputs address bits A0 to A19
A0/D0 to
A7/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external memory area with 8-bit multiplexed bus
A1/D0 to
A8/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A1 to A8) by timesharing, while accessing an external memory area with 16-bit multiplexed bus
CS0 to CS3
O
VCC2
Outputs chip-select signals CS0 to CS3 to specify an external memory area
WRL/WR
WRH/BHE
RD
O
VCC2
Low active output pins. Outputs WRL, WRH, (WR, BHE), RD
signals. WRL and WRH can be switched with or BHE and
WR can be selected by a program.
WRL, WRH and RD selected
If the external data bus is 16-bit, data is written to an even
address in external memory area when WRL is driven low.
Data is written to an odd address when WRH is driven low.
Data is read when RD is driven low.
WR, BHE and RD are selected
Data is written to external memory area when WR is driven
low. Data in external memory area is read when RD is driven
low. An odd address is accessed when BHE is driven low.
Select WR, BHE, and RD for external 8-bit data bus
ALE
O
VCC2
Output ALE signal to latch address.
HOLD
I
VCC2
Low active input pin. The MCU is placed in hold state while
the HOLD pin is driven low.
HLDA
O
VCC2
Low active output pin. In a hold state, HLDA outputs a lowlevel signal.
RDY
I
VCC2
Low active input pin. The MCU is placed in wait state while
the RDY pin is driven low.
Power supply: VCC2 is used to supply power to external bus related pins.
NOTE:
1. VCC1 is hereinafter referred to as VCC unless otherwise noted.
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 1.7
1. Overview
Pin Functions (2)
Signal Name
Pin Name
I/O
Power
Supply
Description
Main clock input
XIN
I
VCC1
Main clock output
XOUT
O
VCC1
Sub clock input
XCIN
I
VCC1
Sub clock output
XCOUT
O
VCC1
BCLK output
BCLK
O
VCC2
Output pin for BCLK signal
Clock output
CLKOUT
O
VCC2
This pin outputs the clock having the same frequency
as fC, f8, or f32
INT interrupt input
INT0 to INT2
I
VCC1
Low active input pins for INT interrupt
INT3 to INT7
I
VCC2
NMI interrupt input
NMI
I
VCC1
Low active input pin for NMI interrupt
Key input
interrupt input
KI0 to KI3
I
VCC1
Low active input pins for key input interrupt
Timer A
TA0OUT to
TA4OUT
I/O
VCC1
Timer A0 to A4 I/O pins (TA0OUT as an output pin is
N-channel open drain output)
TA0IN to TA4IN
I
VCC1
Timer A0 to A4 input pins
ZP
I
VCC1
Input pin for Z-phase
Timer B
TB0IN to TB5IN
I
VCC1
Timer B0 to B5 input pins
Three-phase motor
control timer
U, U, V, V, W, W
O
VCC1
Output pins for three-phase motor control timer output
SD
I
VCC1
Input pin for three-phase motor control timer input
CTS0 to CTS2,
CTS5
I
VCC1
Input pins to control data transmission
CTS6, CTS7
I
VCC2
RTS0 to RTS2,
RTS5
O
VCC1
RTS6, RTS7
O
VCC2
CLK0 to CLK2, CLK5
I/O
VCC1
CLK6, CLK7
I/O
VCC2
Serial interface
UART0 to UART2,
UART5 to UART7
RXD0 to RXD2, RXD5
I
VCC1
RXD6, RXD7
I
VCC2
TXD0 to TXD2, TXD5
O
VCC1
TXD6, TXD7
O
VCC2
CLKS1
O
VCC1
I/O pins for the main clock oscillation circuit. Connect
a ceramic resonator or crystal oscillator between XIN
and XOUT(1). To apply an external clock, connect it to
XIN and leave XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a
crystal oscillator between XCIN and XCOUT (1).
To apply an external clock, connect it to XCIN and
leave XCOUT open
Output pins to control data reception
Transfer clock I/O pins
Serial data input pins
Serial data output pins(2)
Output pin for transfer clock multiple-pin output function
NOTES:
1. Consult the oscillator manufacturer regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open-drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open-drain output pins by a program.
REJ09B0392-0064 Rev.0.64
Page 12 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 1.8
Signal Name
1. Overview
Pin Functions (3)
I/O
Power Supply
SDA0 to SDA2,
SDA5
I/O
VCC1
SDA6, SDA7
I/O
VCC2
SCL0 to SCL2,
SCL5
I/O
VCC1
SCL6, SCL7
I/O
VCC2
CLKS3, CLKS4
I/O
VCC1
Transfer clock I/O pins
SIN3, SIN4
I
VCC1
Serial data input pins
SOUT3, SOUT4
O
VCC1
Serial data output pins
Reference
VREF
voltage input
I
VCC1
Reference voltage input pins for the A/D converter and D/A
converter. Connect to VCC1.
A/D
converter
AN0 to AN7
I
VCC1
Analog input pins for the A/D converter
AN0_0 to AN0_7
AN2_0 to AN2_7
I
VCC2
ADTRG
I
VCC1
Input pin for an external A/D trigger
UART0 to
UART2,
UART5 to
UART7
I2C mode
Serial
interface
SI/03, SI/04
Pin Name
Description
Serial data I/O pins (1)
Transfer clock I/O pins (1)
ANEX0, ANEX1
I
VCC1
Extended analog input pin for the A/D converter
D/A
converter
DA0, DA1
O
VCC1
Output pin for the D/A converter
I/O port
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0 to P5_7
I/O
VCC2
8-bit CMOS I/O ports. A direction register determines whether
each pin is used as an input port or an output port. A pull-up
resistor may be enabled or disabled for input ports in 4-bit
units.
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_7
P9_0 to P9_7
P10_0 to P10_7
I/O
VCC1
8-bit I/O ports having equivalent functions to P0.
However, P7_0, P7_1, and P8_5 are N-channel open-drain
output ports. No pull-up resistor is provided. P8_5 is an input
port for verifying the NMI pin level and shares a pin with NMI.
NOTE:
1. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, SCLi can be
selected as CMOS output pin or N-channel open drain output pin by program.
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen registers configure a register bank. There are two sets of register banks.
b31
b15
b8 b7
b0
R2
R0H(high order bits of R0) R0L (loworder bits of R0)
R3
R1H(high order bits of R1) R1L (loworder bits of R1)
R2
Data registers (1)
R3
A0
Address registers (1)
A1
FB
b19
b15
Frame base registers (1)
b0
INTBH
Interrupt table register
INTBL
INTBH is 4 high-order bits of INTB register and
INTBL is 16 low-order bits of INTB register
b19
b0
Program counter
PC
b15
b0
User stack pointer
USP
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
U I
Flag register
b0
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
NOTE:
1. These registers comprise a register bank. There are two sets of register banks.
Figure 2.1
2.1
Central Processing Unit Register
Data Registers (R0, R1, R2 and R3)
The R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic and logic operations. R0 and R1
can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data
registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to
R3R1.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
2.2
2. Central Processing Unit (CPU)
Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer,
arithmetic and logic operations. A0 can be combined with A1 and used as a 32-bit address register
(A1A0).
2.3
Frame Base Registers (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register indicating the start address of an relocatable interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), as USP and ISP, are each 16 bits wide. The U flag is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB-relative addressing.
2.8
Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit that has been generated by the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is for debugging purpose only. Set it to 0.
2.8.3
Zero Flag (Z Flag)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S Flag)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set
to 1.
2.8.6
Overflow Flag (O Flag)
The O flag is set to 1 when an arithmetic operation results in an overflow; otherwise to 0.
2.8.7
Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is set to 0, and enabled when it is set to 1. The I flag is
set to 0 when an interrupt request is acknowledged.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
2.8.8
2. Central Processing Unit (CPU)
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt number 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Space
Only write 0 to bits assigned as reserved bits. The read value is undefined.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
3.
3. Memory
Memory
Figure 3.1 is a memory map of the M16C/64 Group. The M16C/64 Group has 1 Mbyte address space from
address 00000h to FFFFFh.
The internal ROM is flash memory. Program ROM 1 is allocated from address FFFFFh to lower.
For example, a 64-Kbyte program ROM 1 is addressed from F0000h to FFFFFh. An 8-Kbyte data flash is
addressed from 0E000h to 0FFFFh. This data flash space is used not only for data storage but also for program storage. Program ROM 2 is allocated addresses 10000h to 13FFFh. The user boot code area is
assigned addresses 13FF0h to 13FFFh in the program ROM 2.
The fixed interrupt vectors are addressed from FFFDCh to FFFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated from address 00400h to higher. For example, a 10-Kbyte internal RAM is
addressed from 00400h to 02BFFh. The internal RAM is used not only for data storage but also for stack
area when subroutines are called or when interrupt request are acknowledged.
SFRs are allocated from address 00000h to 003FFh and from 0D000h to 0D7FFh. Peripheral function control registers are located here. All blank spaces within SFRs are reserved and cannot be accessed by users.
The special page vectors are addressed from FFE00h to FFFD7h. They are used for the JMPS instruction
and JSRS instruction. Refer to the M16C/60, M16C/20 Series Software Manual for details.
In memory expansion mode or microprocessor mode, some spaces are reserved and cannot be accessed
by users.
00000h
SFR
00400h
Internal RAM
XXXXXh
0D000h
Reserved area
13FF0h
SFR
0D800h
13FFFh
User boot code area
External area
0E000h
10000h
14000h
27000h
Internal ROM
(data flash)
FFE00h
Internal ROM
(program ROM 2)
FFFD8h
External area
FFFDCh
Reserved area
28000h
Internal RAM
Size
Address XXXXXh
Internal ROM
Size
Address YYYYYh
12 Kbytes
033FFh
128 Kbytes
E0000h
16 Kbytes
043FFh
256 Kbytes
C0000h
31 Kbytes
07FFFh
512 Kbytes
80000h
NOTES:
External area
80000h
Reserved area (2)
YYYYYh
Internal ROM
(program ROM 1)
FFFFFh
FFFFFh
Special page
vector table
Reserved area
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
1. This memory map is based on the case that the PM10 bit in the PM1 register is 1, the PM13 bit in the PM1 register is 1,
and the PRG2C0 bit in the PRG2C register is 0.
2. Available as external area in microprocessor mode.
Figure 3.1
Memory Map
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (Special Function Register) is a control register for a peripheral function. Tables 4.1 to 4.14 list SFR
information.
Table 4.1
SFR Information (1) (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
Register
Symbol
After Reset
Processor Mode Register 0
PM0
00000000b (CNVSS pin is “L”)
00000011b(CNVSS pin is “H”) (2)
00001000b
01001000b
00100000b
00000001b
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
PM1
CM0
CM1
CSR
Protect Register
Data Bank Register
Oscillation Stop Detection Register
PRCR
DBR
CM2
00h
00h
Program 2 Area Control Register
PRG2C
XXXXXXX0b
Peripheral Clock Select Register
PCLKR
00000011b
Clock Prescaler Reset Flag
CPSRF
0XXXXXXXb
0X000010b (3)
Reset Source Determine Flag
RSTFR
0XXXXXXXb (4)
0019h
Voltage Detection 2 Circuit Flag Register
VCR1
001Ah
Voltage Detection Circuit Operation Enable Register
VCR2
001Bh
001Ch
001Dh
001Eh
Chip Select Expansion Control Register
PLL Control Register 0
CSE
PLC0
00001000b (2)
000X0000b (Hardware reset 1)
001X0000b (Brown-out reset) (2)
00h
0X01X010b
Processor Mode Register 2
PM2
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
Low Voltage Detection Interrupt Register
D4INT
Voltage Monitor 0 Circuit Control Register
VW0C
XXX00X01b (2)
00h
10001X10b (Hardware Reset 1)
11001X11b (Brown-out reset) (2)
002Bh
002Ch
002Dh
002Eh
002Fh
NOTES:
X: Undefined
1.
The blank areas are reserved and cannot be accessed by users.
2.
Software reset, watchdog timer reset, and oscillation stop detection reset do not affect bits PM01 and PM00 in the PM0 register, and registers
VCR1, VCR2, and VW0C.
3.
Oscillation stop detection reset do not affect bits CM20, CM21, and CM27.
4.
The CWR bit in the RSTFR register is set to 0 after brown-out reset. This bit does not change by any other reset.
REJ09B0392-0064 Rev.0.64
Page 18 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Address
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
NOTE:
1.
Register
INT7 Interrupt Control Register
INT6 Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt
Control Register
Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt
Control Register
SI/O4 Interrupt Control Register, INT5 Interrupt Control Register
SI/O3 Interrupt Control Register, INT4 Interrupt Control Register
UART2 BUS Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
Symbol
After Reset
INT7IC
INT6IC
INT3IC
TB5IC
TB4IC, U1BCNIC
XX00X000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
TB3IC, U0BCNIC
XXXXX000b
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Information (3) (1)
Address
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh to 015Fh
NOTE:
1.
Register
DMA2 Interrupt Control Register
DMA3 Interrupt Control Register
UART5 BUS Collision Detection Interrupt Control Register
UART5 Transmit Interrupt Control Register
UART5 Receive Interrupt Control Register
UART6 BUS Collision Detection Interrupt Control Register
UART6 Transmit Interrupt Control Register
UART6 Receive Interrupt Control Register
UART7 BUS Collision Detection Interrupt Control Register
UART7 Transmit Interrupt Control Register
UART7 Receive Interrupt Control Register
Symbol
DM2IC
DM3IC
U5BCNIC
S5TIC
S5RIC
U6BCNIC
S6TIC
S6RIC
U7BCNIC
S7TIC
S7RIC
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
X: Undefined
The blank areas are reserved and cannot be accessed by users.
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Page 20 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Address
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
NOTE:
1.
Register
Symbol
After Reset
DMA0 Source Pointer
SAR0
XXh
XXh
0Xh
DMA0 Destination Pointer
DAR0
XXh
XXh
0Xh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh
XXh
0Xh
DMA1 Destination Pointer
DAR1
XXh
XXh
0Xh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
00000X00b
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 21 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.5
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Address
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
NOTE:
1.
Register
Symbol
After Reset
DMA2 Source Pointer
SAR2
XXh
XXh
0Xh
DMA2 Destination Pointer
DAR2
XXh
XXh
0Xh
DMA2 Transfer Counter
TCR2
XXh
XXh
DMA2 Control Register
DM2CON
00000X00b
DMA3 Source Pointer
SAR3
XXh
XXh
0Xh
DMA3 Destination Pointer
DAR3
XXh
XXh
0Xh
DMA3 Transfer Counter
TCR3
XXh
XXh
DMA3 Control Register
DM3CON
00000X00b
Timer B Count Source Select Register 0
Timer B Count Source Select Register 1
TBCS0
TBCS1
00h
X0h
Timer A Count Source Select Register 0
Timer A Count Source Select Register 1
Timer A Count Source Select Register 2
TACS0
TACS1
TACS2
00h
00h
X0h
Timer A Waveform Output Function Select Register
TAPOFS
XXX00000b
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 22 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
NOTE:
1.
Register
Symbol
After Reset
Timer B Count Source Select Register 2
Timer B Count Source Select Register 3
TBCS2
TBCS3
00h
X0h
Interrupt Source Select Register 3
Interrupt Source Select Register 2
Interrupt Source Select Register
IFSR3A
IFSR2A
IFSR
00h
00h
00h
Address Match Interrupt Enable Register
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 0
AIER
AIER2
RMAD0
XXXXXX00b
XXXXXX00b
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Address Match Interrupt Register 2
RMAD2
00h
00h
X0h
Address Match Interrupt Register 3
RMAD3
00h
00h
X0h
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 23 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
NOTE:
1.
Register
Symbol
After Reset
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00000001b
00X0XX0Xb
XXXX0000b
Flash Memory Control Register 6
FMR6
XX0XXX00b
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART Transmit/Receive Control Register 2
UCON
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
X0000000b
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 24 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
NOTE:
1.
Register
Symbol
After Reset
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
SI/O3 Transmit/Receive Register
S3TRR
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
XXh
SI/O3 Control Register
SI/O3 Bit Rate Register
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
01000000b
XXh
XXh
SI/O4 Control Register
SI/O4 Bit Rate Register
SI/O34 Control Register 2
S4C
S4BRG
S34C2
01000000b
XXh
00XXX0X0b
UART5 Special Mode Register 4
UART5 Special Mode Register 3
UART5 Special Mode Register 2
UART5 Special Mode Register
UART5 Transmit/Receive Mode Register
UART5 Bit Rate Register
UART5 Transmit Buffer Register
U5SMR4
U5SMR3
U5SMR2
U5SMR
U5MR
U5BRG
U5TB
UART5 Transmit/Receive Control Register 0
UART5 Transmit/Receive Control Register 1
UART5 Receive Buffer Register
U5C0
U5C1
U5RB
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
UART6 Special Mode Register 4
UART6 Special Mode Register 3
UART6 Special Mode Register 2
UART6 Special Mode Register
UART6 Transmit/Receive Mode Register
UART6 Bit Rate Register
UART6 Transmit Buffer Register
U6SMR4
U6SMR3
U6SMR2
U6SMR
U6MR
U6BRG
U6TB
UART6 Transmit/Receive Control Register 0
UART6 Transmit/Receive Control Register 1
UART6 Receive Buffer Register
U6C0
U6C1
U6RB
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 25 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
NOTE:
1.
Register
Symbol
UART7 Special Mode Register 4
UART7 Special Mode Register 3
UART7 Special Mode Register 2
UART7 Special Mode Register
UART7 Transmit/Receive Mode Register
UART7 Bit Rate Register
UART7 Transmit Buffer Register
U7SMR4
U7SMR3
U7SMR2
U7SMR
U7MR
U7BRG
U7TB
UART7 Transmit/Receive Control Register 0
UART7 Transmit/Receive Control Register 1
UART7 Receive Buffer Register
U7C0
U7C1
U7RB
After Reset
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 26 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
Address
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
0308h
0309h
030Ah
030Bh
030Ch
030Dh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
031Ch
031Dh
031Eh
031Fh
NOTE:
1.
Register
Symbol
After Reset
Timer B3,4,5 Count Start Flag
TBSR
000XXXXXb
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Generation Frequency Set Counter
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
XX111111b
XX111111b
XXh
XXh
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
TB3MR
TB4MR
TB5MR
XXh
XXh
XXh
XXh
XXh
XXh
00XX0000b
00XX0000b
00XX0000b
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 27 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
0320h
0321h
0322h
0323h
0324h
0325h
0326h
0327h
0328h
0329h
032Ah
032Bh
032Ch
032Dh
032Eh
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
NOTE:
1.
Register
Symbol
After Reset
Count Start Flag
TABSR
00h
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
ONSF
TRGSR
UDF
00h
00h
00h
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 28 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.12
4. Special Function Registers (SFRs)
SFR Information (12) (1)
Address
Register
Symbol
After Reset
0360h
0361h
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
00h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
Pull-Up Control Register 2
PUR2
00000000b (2)
00000010b
00h
Port Control Register
PCR
00000XX0bh
Count Source Protection Mode Register
CSPR
037Dh
037Eh
037Fh
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
WDTR
WDTS
WDC
00h (3)
XXh
XXh
00XXXXXXb
NOTES:
X: Undefined
1.
The blank areas are reserved and cannot be accessed by users.
2.
Values after hardware reset 1 or brown-out reset are as follows:
• 00000000b when "L" is input to the CNVSS pin
• 00000010b when "H" is input to the CNVSS pin
Values after software reset, watchdog timer reset, and oscillation stop detection reset are as follows:
• 00000000b when bits PM01 and PM00 in the PM0 register are set to 00b (single-chip mode).
• 00000010b when bits PM01 and PM00 in the PM0 register are set to 01b (memory expansion mode) or 11b (microprocessor mode).
3.
When the CSPROINT bit in the OFS1 address is set to 0, value after reset is 10000000b
REJ09B0392-0064 Rev.0.64
Page 29 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.13
4. Special Function Registers (SFRs)
SFR Information (13) (1)
Address
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
NOTE:
1.
Register
Symbol
After Reset
DMA2 Source Select Register
DM2SL
00h
DMA3 Source Select Register
DM3SL
00h
DMA0 Source Select Register
DM0SL
00h
DMA1 Source Select Register
DM1SL
00h
CRC Data Register
CRCD
CRC Input Register
CRCIN
XXh
XXh
XXh
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
XXXXXXXXb
000000XXb
A/D Register 3
AD3
XXXXXXXXb
000000XXb
A/D Register 4
AD4
XXXXXXXXb
000000XXb
XXXXXXXXb
000000XXb
XXXXXXXXb
000000XXb
X: Undefined
The blank areas are reserved and cannot be accessed by users.
REJ09B0392-0064 Rev.0.64
Page 30 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 4.14
4. Special Function Registers (SFRs)
SFR Information (14) (1)
Address
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
D000h to
D7FFh
NOTE:
1.
Register
Symbol
After Reset
A/D Register 5
AD5
XXXXXXXXb
000000XXb
A/D Register 6
AD6
XXXXXXXXb
000000XXb
A/D Register 7
AD7
XXXXXXXXb
000000XXb
A/D Control Register 2
ADCON2
0000X00Xb
A/D Control Register 0
A/D Control Register 1
D/A0 Register
ADCON0
ADCON1
DA0
00000XXXb
0000X000b
00h
D/A1 Register
DA1
00h
D/A Control Register
DACON
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P10 Direction Register
PD10
00h
X: Undefined
The blank areas are reserved and cannot be accessed by users.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
5.
5. Reset
Reset
Hardware reset 1, brown-out reset, software reset, watchdog timer reset and oscillation stop detection reset
are available to reset the microcomputer.
5.1
Hardware Reset 1
The microcomputer resets pins, the CPU, and SFR by setting the RESET pin. If the supply voltage meets
the recommended operating conditions, the microcomputer resets all pins, the CPU, and SFR when an
“L” signal is applied to the RESET pin (see Table 5.1 “Pin Status When RESET Pin Level is “L””).
When the signal applied to the RESET pin changes low (“L”) to high (“H”), the microcomputer executes
the program in an address indicated by the reset vector. The 125 kHz on-chip oscillator clock divided by 8
is automatically selected as a CPU clock after reset.
Refer to 4. “Special Function Registers (SFRs)” for SFR states after reset.
The internal RAM is not reset. When an “L” signal is applied to the RESET pin while writing data to the
internal RAM, the internal RAM is in an indeterminate state.
Figure 5.1 shows an Example Reset Circuit. Figure 5.2 shows a Reset Sequence. Table 5.1 lists Pin Status When RESET Pin Level is “L”.
5.1.1
Reset on a Stable Supply Voltage
(1) Apply “L” to the RESET pin
(2) Wait for 1/fOCO-S × 20
(3) Apply an “H” signal to the RESET pin
5.1.2
Power-on Reset
(1)
(2)
(3)
(4)
(5)
Apply “L” to the RESET pin
Raise the supply voltage to the recommended operating level
Insert td(P-R) ms as wait time for the internal voltage to stabilize
Wait for 1/fOCO-S × 20
Apply “H” to the RESET pin
Recommended
operation
VCC1 voltage
0V
RESET
VCC1
RESET
0.2 VCC1 or below
0.2 VCC1 or below
0V
td (P-R)+
Figure 5.1
Example Reset Circuit
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1
x 20 or above
fOCO - S
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
5. Reset
VCC1, VCC2
XIN
Microprocessor mode
BYTE = “H”
td(P-R)
More than
20 cycles of
fOCO-S are
necessary.
BCLK
48 cycles
(fOCO-S divided by 8 x 48)
RESET
BCLK
FFFFCh
Address
FFFFDh
FFFFEh
RD
WR
CS0
Microprocessor mode
BYTE = “L”
FFFFCh
Address
FFFFEh
RD
WR
CS0
Single-chip
mode
FFFFEh
Address
Figure 5.2
Content of reset vector
FFFFCh
Reset Sequence
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Content of reset vector
Content of reset vector
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 5.1
5. Reset
Pin Status When RESET Pin Level is “L”
Status
Pin Name
CNVSS = VSS
CNVSS = VCC1 (1)
BYTE = VSS
BYTE = VCC1
P0
Input port
Data input
Data input
P1
Input port
Data input
Input port
P2, P3, P4_0 to P4_3 Input port
Address output (undefined)
Address output (undefined)
P4_4
Input port
CS0 output (“H” is output)
CS0 output (“H” is output)
P4_5 to P4_7
Input port
Input port (pulled high)
Input port (pulled high)
P5_0
Input port
WR output (“H” is output)
WR output (“H” is output)
P5_1
Input port
BHE output (undefined)
BHE output (undefined)
P5_2
Input port
RD output (“H” is output)
RD output (“H” is output)
P5_3
Input port
BCLK output
BCLK output
P5_4
Input port
HLDA output (The output
value
depends on the input to the
HOLD pin)
HLDA output (The output
value
depends on the input to the
HOLD pin)
P5_5
Input port
HOLD input (2)
HOLD input (2)
P5_6
Input port
ALE output (“L” is output)
ALE output (“L” is output)
P5_7
Input port
RDY input
RDY input
P6, P7, P8, P9, P10
Input port
Input port
Input port
NOTE:
1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power
on. When CNVSS = VCC1, the pin state is indeterminate until the internal power supply voltage stabilizes.
2. Apply a “H” signal.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
5.2
5. Reset
Brown-out Reset
The microcomputer resets pins, the CPU, or SFRs by setting the built-in voltage detection 0 circuit. The
voltage detection 0 circuit monitors the voltage applied to the VCC1 pin (Vdet0).
The microcomputer resets pins, the CPU, and SFR as soon as the voltage that is applied to the VCC1 pin
drops to Vdet0 or below.
Then, 125 kHz on-chip oscillator clock starts counting when the voltage that is applied to the VCC1 pin
goes up to Vdet0 or above. The internal reset signal becomes “H” after the 125 kHz on-chip oscillator
clock is counted 32 times, and then reset sequence starts (see Figure 5.2). The 125 kHz on-chip oscillator
clock divided by 8 is automatically selected as a CPU clock after reset.
Refer to 4. “Special Function Registers (SFRs)” for the SFR status after brown-out reset.
The internal RAM is not reset. When the voltage that is applied to the VCC1 pin drops to Vdet0 or below
while writing data to the internal RAM, the internal RAM is in an indeterminate state.
Refer to 6. “Voltage Detection Circuit” for details of the voltage detection 0 circuit.
5.3
Software Reset
The microcomputer resets pins, the CPU, and SFRs when the PM03 bit in the PM0 register is set to 1
(microcomputer reset). Then the microcomputer executes the program in an address determined by the
reset vector. The 125 kHz on-chip oscillator clock divided by 8 is automatically selected as a CPU clock
after reset.
In the software reset, the microcomputer does not reset a part of the SFRs. Refer to 4. “Special Function Registers (SFRs)” for details.
The internal RAM is not reset.
5.4
Watchdog Timer Reset
The microcomputer resets pins, the CPU, and SFRs when the PM12 bit in the PM1 register is set to 1
(reset when watchdog timer underflows) and the watchdog timer underflows. Then the microcomputer
executes the program in an address determined by the reset vector. The 125 kHz on-chip oscillator clock
divided by 8 is automatically selected as a CPU clock after reset.
In the watchdog timer reset, the microcomputer does not reset a part of the SFRs. Refer to 4. “Special
Function Registers (SFRs)” for details.
The internal RAM is not reset. When the watchdog timer underflows while writing data to the internal
RAM, the internal RAM is in an indeterminate state.
Refer to 13. “Watchdog Timer” for details.
5.5
Oscillation Stop Detection Reset
The microcomputer resets and stops pins, the CPU, and SFRs when the CM27 bit in the CM2 register is
0 (reset when oscillation stop detected), if it detects main clock oscillation circuit stop. Refer to 10.6
“Oscillation Stop and Re-Oscillation Detect Function” for details.
In the oscillation stop detection reset, the microcomputer does not reset a part of the SFRs. Refer to 4.
“Special Function Registers (SFRs)” for details. Processor mode remains unchanged since bits PM01
to PM00 in the PM0 register are not reset.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
5.6
5. Reset
Internal Space
Figure 5.3 shows CPU Register Status After Reset. Refer to 4. “Special Function Registers (SFRs)” for
SFR states after reset.
b15
b0
0000h
Data register (R0)
0000h
Data register (R1)
0000h
Data register (R2)
0000h
Data register (R3)
0000h
Address register (A0)
0000h
Address register (A1)
0000h
Frame base register (FB)
b19
b0
00000h
Interrupt table register (INTB)
Content of addresses FFFFEh to FFFFCh
b15
Program counter (PC)
b0
0000h
User stack pointer (USP)
0000h
Interrupt stack pointer (ISP)
0000h
Static base register (SB)
b15
b0
Flag register (FLG)
0000h
b15
b8
IPL
Figure 5.3
b7
U I
b0
O B S Z D C
CPU Register Status After Reset
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6.
6. Voltage Detection Circuit
Voltage Detection Circuit
The voltage detection circuit consists of the voltage detection 0 circuit and the low voltage detection circuit.
The voltage detection 0 circuit monitors the voltage applied to the VCC1 pin. The microcomputer is reset if
the voltage detection 0 circuit detects VCC1 is Vdet0 or below.
The low voltage detection circuit also monitors the voltage applied to the VCC1 pin. The low voltage detection signal is generated when the low voltage detection circuit detects that VCC1 passes through Vdet2.
This signal generates the low voltage detection interrupt. The VC13 bit in the VCR1 register determines
whether VCC1 is Vdet2 and above or below Vdet2.
The voltage detection circuit is available when VCC1 = 5 V.
Figure 6.1 shows a Voltage Detection Circuit Block Diagram.
Low voltage
detection circuit
VCC1
VC27
Noise
filter
+
Internal
reference
voltage
-
Low voltage detection
interrupt signal
≥ Vdet2
VCR1 register
b3
VC25
VC13 bit
Voltage
detection 0
circuit
Voltage detection 0 signal
+
-
Figure 6.1
≥ Vdet0
Voltage Detection Circuit Block Diagram
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6. Voltage Detection Circuit
Voltage Detection 2 Circuit Flag Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
Symbol
Address
After Reset (2)
VCR1
0019h
00001000b
Bit Symbol
—
(b2-b0)
VC13
—
(b7-b4)
Bit Name
Function
RW
Reserved bits
Set to 0
RW
Low voltage monitor flag (1)
0 : VCC1 < Vdet2
1 : VCC1 ≥ Vdet2
RO
Reserved bits
Set to 0
RW
NOTES :
1. The VC13 bit is enabled when the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled).
The VC13 bit is always 1 (VCC1 ≥ Vdet2) when the VC27 bit is set to 0 (low voltage detection circuit disabled).
2. This register dose not change at software reset, watchdog timer reset, and oscillation stop detection reset.
Voltage Detection Circuit Operation Enable Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 0 0
Symbol
Address
VCR2
001Ah
Bit Symbol
—
(b3-b0)
—
(b4)
VC25
—
(b6)
VC27
After Reset (4)
000X0000b (Hardware reset 1)
001X0000b (Brown-out reset)
Bit Name
Reserved bits
Function
Set to 0
No register bit. If necessary, set to 0. Read as undefined value
RW
RW
—
Voltage detection 0 enable bit 0 : Disable voltage detection 0 circuit
(2, 5)
1 : Enable voltage detection 0 circuit
RW
Reserved bit
Set to 0
RW
Low voltage monitor bit (3, 5)
0 : Disable low voltage detection circuit
1 : Enable low voltage detection circuit
RW
NOTES :
1. Write to this register after setting the PRC3 bit in the PRCR register to 1 (write enabled).
2. To use brown-out reset, set the VC25 bit to 1 (voltage detection 0 circuit enabled).
3. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to 1 (low
voltage detection interrupt enabled), set the VC27 bit to 1 (low voltage detection circuit enabled).
4. This register does not change at software reset, watchdog timer reset, and oscillation stop detection reset.
5. The detection circuit does not start operation until td(E-A) elapses after the VC25 bit or VC27 bit is set to 1.
Figure 6.2
Registers VCR1 and VCR2
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6. Voltage Detection Circuit
Low Voltage Detection Interrupt Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
D4INT
001Fh
00h
Bit Symbol
Bit Name
Function
RW
Low voltage detection
interrupt enable bit (5)
0 : Disabled
1 : Enabled
RW
D41
STOP mode deactivation
control bit (4, 6)
0 : Disabled (the low voltage
detection interrupt is not used for
recovery from stop mode)
1 : Enabled (the low voltage detection
interrupt is used for recovery from stop
mode)
RW
D42
Voltage change detection
flag (2)
0 : Not detected
1 : Vdet2 passing detection
RW (3)
D43
WDT overflow detect flag
0 : Not detected
1 : Detected
RW (3)
D40
b5
DF0
b4
DF1
0
0
1
1
—
(b7-b6)
No register bits. If necessary, set to 0. Read as undefined value.
Sampling clock select bit
0 : D4INT clock divided by 8
1 : D4INT clock divided by 16
0 : D4INT clock divided by 32
1 : D4INT clock divided by 64
RW
RW
—
NOTES :
1. Write to this register after setting the PRC3 bit in the PRCR register to 1 (write enabled).
2. This flag is enabled when the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled).
If the VC27 bit is set to 0 (low voltage detection circuit disabled), the D42 bit is set to 0 (not detected).
3. This bit is set to 0 by writing a 0 in a program. (writing a 1 has no effect.)
4. If the low voltage detection interrupt needs to be used to get out of stop mode again after once used for that
purpose, reset the D41 bit by writing a 0 and then a 1.
5. The D40 bit is effective when the VC27 bit in the VCR2 register = 1.
To set the D40 bit to 1, set bits in the following order.
(a) Set the VC27 bit to 1.
(b) Wait for td(E-A) until the detection circuit is actuated.
(c) Wait for the sampling time. (See Table 6.3 Sampling Period.)
(d) Set the D40 bit to 1.
6. This bit is used for wait mode exiting control when the CM02 bit in the CM0 register is 1 (stop peripheral function
clock f1 in wait mode).
Figure 6.3
D4INT Register
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6. Voltage Detection Circuit
Voltage Monitor 0 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
0
Symbol
Address
VW0C
002Ah
After Reset (2)
10001X10b (Hardware reset 1)
11001X11b (Brown-out reset)
Bit Symbol
Bit Name
Function
VW0C0
Brown-out reset enable bit (3)
VW0C1
Voltage monitor 0 digital filter 0 : Enable digital filter
disable mode select bit
1 : Disable digital filter
0 : Disabled
1 : Enabled
RW
RW
RW
—
(b2)
Reserved bit
Set to 0.
Read as undefined value
RW
—
(b3)
Reserved bit
Read as undefined value
RO
b5 b4
VW0F0
Sampling clock select bit
VW0F1
—
(b7-b6)
Reserved bits
0
0
1
1
0 : fOCO-S divided by 1
1 : fOCO-S divided by 2
0 : fOCO-S divided by 4
1 : fOCO-S divided by 8
Set to 1
RW
RW
NOTES :
1. Set the PRC3 bit in the PRCR register to 1 (write enabled) to rewrite the VW0C register.
2. The value of this register remain unchanged after software reset, watchdog timer reset, or oscillation stop detection
reset.
3. Set the VC25 bit in the VCR2 register to 1 (voltage detection 0 circuit enabled) to enable the VW0C0 bit. Set the
VW0C0 bit to 0 (disabled) when the VC25 bit is set to 0 (voltage detection 0 circuit disabled).
Figure 6.4
VW0C Register
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6.1
6. Voltage Detection Circuit
Brown-out Reset
Figure 6.5 is a block diagram illustrating brown-out reset generation circuit. Table 6.1 shows a setting procedure of the bits for brown-out reset. Figure 6.6 provides an example of brown-out reset operation.
When using brown-out resetbrown-out reset to exit stop mode, set the VW0C1 bit in the VW0C register to
1 (digital filter disabled).
Table 6.1
Setting Procedures of the Bits for Brown-out Reset
Procedure
1
2
3
4
5
6
7
When using the digital filter
When not using the digital filter
Set the VC25 bit in the VCR2 register to 1 (voltage detection 0 circuit enabled)
Wait for td (E-A)
Use bits VW0F0 to VW0F1 in the VW0C regis- Set the VW0C1 bit in the VW0C register to 1
ter to select the digital filter sampling clock. Set (digital filter disabled), and bits 6 and 7 to 1
the VW0C1 bit to 0 (digital filter enabled), bits 6
and 7 to 1
Set bit 2 in the VW0C register to 0 (setting bit 2 to 0 once again after procedure 3 is necessary)
Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator oscillates)
Wait for digital filter sampling clock x 4 cycles
- (no wait time)
Set the VW0C0 bit in the VW0C register to 1 (brown-out reset enabled)
Brown-out reset generation circuit
VW0F1 to VW0F0
= 00b
= 01b
Voltage detection 0 circuit
= 10b
fOCO-S
1/2
1/2
1/2 = 11b
VC25
VW0C1
VCC1
Internal
reference
voltage
+
-
Digital
filter
Voltage
detection
0 signal
When the VC25 bit is set to
0 (disabled), the voltage
detection 0 signal becomes
“H.”
Brown-out
reset signal
VW0C1
VW0C0
1
VW0C0 to VW0C1, VW0F0 to VW0F1 = the bits in the VW0C register
VC25 = the bit in the VC2 register
Figure 6.5
Brown-out Reset Generation Circuit
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1
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6. Voltage Detection Circuit
VCC
Vdet0
Digital filter sampling clock
×4 cycles
When the VW0C1 bit is 0
(digital filter enabled)
When the VW0C1 bit is 1
(digital filter disabled)
1
fOCO-S
×32
1
fOCO-S
×32
Internal reset signal
Internal reset signal
VW0C1 = the bit in the VW0C register
The above diagram shows an instance in which the following conditions are all met.
•The VC25 bit in the VCR2 register = 1 (voltage detection 0 circuit enabled)
•The VW0C0 bit in the VW0C register = 1 (brown-out reset enabled)
Pins, the CPU, and SFRs are initialized when the internal reset signal becomes low.
The microcomputer executes the program in an address indicated by the reset vector when the internal reset signal changes low
to high.
Refer to 4. SFRs for the SFR status after reset.
Figure 6.6
6.2
Brown-out Reset Operation Example
Low Voltage Detection Interrupt
If the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled), the low voltage
detection interrupt request is generated when the voltage applied to the VCC1 pin is above or below
Vdet2. The low voltage detection interrupt shares the same interrupt vector with the watchdog timer interrupt, oscillation stop, and re-oscillation detection interrupt.
Set the D41 bit in the D4INT register to 1 (enabled) to use the low voltage detection interrupt to exit stop
mode.
The D42 bit in the D4INT register is set to 1 as soon as the voltage applied to the VCC1 pin reaches
Vdet2 due to the voltage rise and voltage drop. When the D42 bit changes 0 to 1, the low voltage detection interrupt request is generated. Set the D42 bit to 0 by program. However, when the D41 bit is set to 1
and the microcomputer is in stop mode, the low voltage detection interrupt request is generated regardless of the D42 bit state if the voltage applied to the VCC1 pin is detected to be above Vdet2. The microcomputer then exits stop mode.
Table 6.2 shows Low Voltage Detection Interrupt Request Generation Conditions.
Bits DF1 to DF0 in the D4INT register determine the sampling period that detects the voltage applied to
the VCC1 pin reaches Vdet2. Table 6.3 shows the Sampling Periods.
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
Table 6.2
6. Voltage Detection Circuit
Low Voltage Detection Interrupt Request Generation Conditions
Operating Mode
Normal Operating Mode
VC27 Bit
D40 Bit
D41 Bit
D42 Bit
CM02 Bit
-
0 to 1
-
0 to 1
0
-
1
0
(1)
Wait Mode (2)
1
1
-
Stop Mode (2)
1
VC13 Bit
0 to 1 (3)
1 to 0 (3)
0 to 1 (3)
1 to 0 (3)
0 to 1
0 to 1
- indicates either 0 or 1 is settable.
NOTE:
1. The status except wait mode and stop mode is handled as normal mode. (Refer to 10. “Clock Generation Circuit”)
2. Refer to 6.3 “Limitations on Exiting Stop Mode” and 6.4 “Limitations on Exiting Wait Mode”.
3. An interrupt request for voltage reduction is generated after the value of the VC13 bit changes and a
sampling time elapses. See Figure 6.8 “Low Voltage Detection Interrupt Generation Circuit
Operation Example” for details.
Table 6.3
Sampling Periods
Sampling Clock (μs)
DF1 to DF0 = 00
DF1 to DF0 = 01
DF1 to DF0 = 10
DF1 to DF0 = 11
(CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64)
3.0
6.0
12.0
24.0
CPU Clock
(D4INT clock)
(MHz)
16
Low voltage detection interrupt generation circuit
DF1, DF0
00b
01b
Low voltage detection circuit
The D42 bit is set to 0 (not
detected) by program. When the
VC27 bit is set to 0 (low voltage
detection circuit disabled), the
D42 bit is set to 0.
10b
D4INT clock
(the clock with
which it operates
also in wait mode)
VC27
1/8
1/2
1/2
1/2
11b
VC13
VCC1
+
VREF
-
Noise
rejection
(Rejection range : 200 ns)
Watchdog timer
interrupt signal
D42
Noise
rejection
circuit
Low voltage
detection
signal
The low voltage detection
signal becomes “H” when the
VC27 bit is set to 0
(disabled).
CM10
Digital
filter
Low voltage
detection
interrupt signal
D41
Oscillation stop,
re-oscillation
detection interrupt
signal
CM02
WAIT instruction (wait mode)
Watchdog timer block
D43
D40
Watchdog timer
underflow signal
Figure 6.7
This bit is set to 0 (not detected) by program.
Low Voltage detection Interrupt Generation Block Diagram
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Non-maskable
interrupt sognal
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
6. Voltage Detection Circuit
VCC1
VC13 bit
Sampling
Sampling
Sampling
Sampling
No low voltage detection
interrupt signals are generated
when the D42 bit is “H.”
Output of the digital filter
(2)
D42 bit
Set the D42 bit to 0 (not
detected) by program.
Low voltage detection interrupt signal
NOTES :
1. The D40 bit is set to 1 (low voltage detection interrupt enabled).
2. Output of the digital filter is shown in Figure 6.7.
Figure 6.8
6.3
Low Voltage Detection Interrupt Generation Circuit Operation Example
Limitations on Exiting Stop Mode
The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if
the CM10 bit in the CM1 register is set to 1 (stop mode) under the conditions below.
• the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled)
• the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled)
• the D41 bit in the D4INT register is set to 1 (low voltage detection interrupt is used to exit stop mode)
• the voltage applied to the VCC1 pin is higher than Vdet2 (the VC13 bit in the VCR1 register is 1)
If the microcomputer is set to enter stop mode when the voltage applied to the VCC1 pin drops below
Vdet2 and to exit stop mode when the voltage applied rises to Vdet2 or above, set the CM10 bit to 1 when
VC13 bit is 0 (VCC1 < Vdet2).
6.4
Limitations on Exiting Wait Mode
The low voltage detection interrupt is immediately generated and the microcomputer exits wait mode If
WAIT instruction is executed under the conditions below.
• the CM02 bit in the CM0 register is set to 1 (stop peripheral function clock)
• the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled)
• the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled)
• the D41 bit in the D4INT register is set to 1 (low voltage detection interrupt is used to exit wait mode)
• the voltage applied to the VCC1 pin is higher than Vdet2 (the VC13 bit in the VCR1 register is 1)
If the microcomputer is set to enter wait mode when the voltage applied to the VCC1 pin drops below
Vdet2 and to exit wait mode when the voltage applied rises to Vdet2 or above, perform WAIT instruction when the VC13 bit is 0 (VCC1 < Vdet2).
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M16C/64 Group
6.5
6. Voltage Detection Circuit
Cold Start-up / Warm Start-up Discrimination
As for the cold start-up / warm start-up discrimination, the CWR bit in the RSTFR register determines
either cold start-up (reset process) when power-on or warm start-up (reset process) when reset signal is
applied during the microcomputer running.
The value of the CWR bit is 0 when power is applied. The CWR bit is also set to 0 after brown-out reset.
The CWR bit is set to 1 by writing a 1 in a program and does not change at hardware reset 1, software
reset, watchdog timer reset, and oscillation stop detection reset.
Use brown-out reset for cold start-up / warm start-up discrimination.
Follow Table 6.1 Setting Procedures of the Bits for Brown-out Reset to set the bits for brown-out reset.
Figure 6.9 shows Cold Start-up / Warm Start-up Discrimination Example. Figure 6.10 shows RSTFR Register.
5V
VCC1
Vdet0
0V
Set to 1 by
program
Set to 1 by
program
CWR bit
Brown-out reset
The above diagram shows an instance in which the digital filter is not used.
Figure 6.9
Cold Start-up / Warm Start-up Discrimination Example
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M16C/64 Group
6. Voltage Detection Circuit
Reset Source Determine Flag
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
After Reset
RSTFR
0018h
0XXXXXXXb (1)
Bit Symbol
Bit Name
Function
RW
Cold start-up / warm start
determine flag (2, 3)
0 : Cold start-up
1 : Warm start-up
RW
—
(b5-b1)
Reserved bits
Read as undefined value
RO
—
(b7-b6)
Reserved bits
Set to 0
RW
CWR
NOTES :
1. The CWR bit is set to 0 (cold start-up) after power activation or brown-out reset. The CWR bit remains unchanged
after hardware reset 1, software reset, watchdog timer reset, or oscillation stop detection reset.
2. The CWR bit is set to 1 by writing a 1 in a program (writing a 0 has no effect).
3. The CWR bit is undefined when the VW0C0 bit in the VW0C register is set to 0 (brown-out reset disabled).
Figure 6.10
RSTFR Register
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M16C/64 Group
7.
7. Processor Mode
Processor Mode
7.1
Types of Processor Mode
Three processor modes are available to choose from: single-chip mode, memory expansion mode, and
microprocessor mode. Table 7.1 shows the Features of Processor Modes.
Table 7.1
Features of Processor Modes
Processor Modes
Access Space
Single-chip mode
SFR, internal RAM, internal ROM
Memory expansion
mode
Microprocessor mode
Pins Which Are Assigned I/O Ports
All pins are I/O ports or peripheral function I/
O pins
Some pins serve as bus control pins (1)
SFR, internal RAM, internal ROM,
external area (1)
SFR, internal RAM, external area (1) Some pins serve as bus control pins (1)
NOTE:
1. Refer to 8. “Bus” for details.
7.2
Setting Processor Modes
Processor mode is set by using the CNVSS pin and bits PM01 to PM00 in the PM0 register.
Table 7.2 shows the Processor Mode After Hardware Reset. Table 7.3 shows Bits PM01 to PM00 Set
Values and Processor Modes
Table 7.2
Processor Mode After Hardware Reset
CNVSS Pin Input Level
VSS
Processor Modes
Single-chip mode
Microprocessor mode
VCC1 (1, 2)
NOTES:
1. If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or
brown-out reset), the internal ROM cannot be accessed regardless of the status of bits PM10 to
PM00.
2. The multiplexed bus cannot be assigned to the entire CS space.
Table 7.3
Bits PM01 to PM00 Set Values and Processor Modes
Bits PM01 to PM00
00b
01b
10b
11b
Processor Modes
Single-chip mode
Memory expansion mode
Do not set
Microprocessor mode
Rewriting bits PM01 to PM00 places the microcomputer in the corresponding processor mode regardless
of whether the input level on the CNVSS pin is “H” or “L”. Note, however, that bits PM01 to PM00 cannot
be rewritten to 01b (memory expansion mode) or 11b (microprocessor mode) at the same time bits PM07
to PM02 are rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the
internal ROM, nor can they be rewritten to exit microprocessor mode in areas overlapping the internal
ROM.
If the microcomputer is reset in hardware by applying VCC1 to the CNVSS pin (hardware reset 1 or
brown-out reset), the internal ROM cannot be accessed regardless of bits PM01 to PM00.
Figures 7.1 to 7.3 show the PM0 Register and PM1 Register. Figure 7.4 show the Memory Map in SingleChip Mode.
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M16C/64 Group
7. Processor Mode
Processor Mode Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
PM0
0004h
Bit Symbol
After Reset (4)
00000000b (CNVSS pin = “L”)
00000011b (CNVSS pin = “H”)
Bit Name
Function
b1
PM00
Processor mode bit
(4)
PM01
0
0
1
1
b0
0 : Single-chip mode
1 : Memory expansion mode
0 : Do not set
1 : Microprocessor mode
RW
RW
RW
PM02
R/W mode select bit (2)
0 : RD, BHE, WR
1 : RD, WRH, WRL
RW
PM03
Software reset bit
Setting this bit to 1 resets the
microcomputer. Read as 0
RW
b5
PM04
0
Multiplexed bus space select
bit (2)
PM05
0
1
1
b4
0 : Multiplexed bus is unused
(separate bus in the entire CS space)
1 : Allocated to CS2 space
0 : Allocated to CS1 space
1 : Allocated to the entire CS space (3)
RW
RW
PM06
Port P4_0 to P4_3 function
select bit (2)
0 : Address output
1 : Port function (address is not output)
RW
PM07
BCLK output disable bit (2)
0 : BCLK is output
1 : BCLK is not output
(pin is left high-impedance)
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. Bits PM02, and PM04 to PM07 are effective when bits PM01 and PM00 are set to 01b (memory expansion mode) or 11b
(microprocessor mode).
3. To set bits PM01 and PM00 to 01b and bits PM05 and PM04 to 11b (multiplexed bus assigned to the entire CS space),
apply an “H” signal to the BYTE pin (external data bus is 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not
rewrite the PM05 and PM04 bits to 11b after reset. If bits PM05 and PM04 are set to 11b during memory expansion
mode, P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case the accessible area for each CS is 256 bytes.
4. Bits PM01 and PM00 do not change at software reset, watchdog timer reset, and oscillation stop detection reset.
Figure 7.1
PM0 Register
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M16C/64 Group
7. Processor Mode
Processor Mode Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
PM1
0005h
00001000b
Bit Symbol
Bit Name
Function
RW
PM10
CS2 area switch bit
(data flash enable bit) (2)
0 : CS2 (0E000h to 0FFFFh )
1 : Data flash (0E000h to 0FFFFh)
RW
PM11
Port P3_7 to P3_4 function
select bit (3)
0 : Address output
1 : Port function
RW
PM12
Watchdog timer function select 0 : Watchdog timer interrupt
bit (4)
1 : Watchdog timer reset
RW
PM13
Internal reserved area
expansion bit (2, 6)
RW
(NOTE 6)
b5
PM14
Memory area expansion bit
PM15
—
(b6)
PM17
(3)
0
0
1
1
b4
0 : 1-Mbyte mode (no expansion)
1 : Do not set
0 : Do not set
1 : 4-Mbyte mode
RW
RW
Reserved bit
Set to 0
RW
Wait bit (5)
0 : No wait state
1 : Wait state (1 wait)
RW
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. Bits PM10 and PM13 are automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite
mode).
3. Bits PM11, PM14, and PM 15 are effective when bits PM01 and PM00 are set to 01b (memory expansion mode) or 11b
(microprocessor mode).
4. The PM12 bit is set to 1 by writing a 1 in a program (writing a 0 has no effect).
The PM12 bit is automatically set to 1 when the CSPRO bit in the CSPR register is 1 (count source protection mode
enabled).
5. When the PM17 bit is set to 1 (wait state), one wait state is inserted when accessing the internal RAM or internal ROM.
When the PM17 bit is set to 1 and accesses an external area, set the CSiW bit in the CSR register (i = 0 to 3) to 0
(wait state).
6. The access area is changed by the PM13 bit as listed in the table below.
Access Area
Internal
PM13 = 1
RAM
Up to Addresses 00400h to 03FFFh (15 Kbytes) The entire area is usable
Program ROM 1
Up to Addresses D0000h to FFFFFh (192 Kbytes)
External
Figure 7.2
PM13 = 0
The entire area is usable
Address 04000h to 0CFFFh are usable
Address 04000h to 0CFFFh are reserved
Address 80000h to CFFFFh are usable
Address 80000h to CFFFFh are reserved
Note that 08000h to 0CFFFh are reserved when (in memory expansion mode)
PM10 is set to 1 during microprocessor mode.
PM1 Register
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M16C/64 Group
7. Processor Mode
Program 2 Area Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
PRG2C(1)
0010h
XXXXXXX0h
Bit Symbol
PRG2C
—
(b1)
—
(b7-b2)
Bit Name
Function
Program ROM 2 disable bit
0 : Enable program ROM 2
1 : Disable program ROM 2
RW
Reserved bit
Set to 0
RW
No register bits. If necessary, set to 0. Read as undefined value
NOTE :
1. Write to this register after setting the PRC6 bit in the PRCR register to 1 (write enabled).
Figure 7.3
PRG2C Register
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RW
Oct 12, 2007
—
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Preliminary Specification
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M16C/64 Group
7.3
7. Processor Mode
Internal Memory
The internal RAM can be used in all processor modes. The range of the internal RAM depends on the setting of the PM 13 bit in the PM1 register.
The internal ROM is used in single-chip mode and memory expansion mode. Three internal ROMs are
available: data flash, program ROM 2, and program ROM 1.
Data flash includes block A (addresses 0E000h to 0EFFFh) and block B (addresses 0F000h to 0FFFFh).
When data flash is selected by the setting of the PM10 bit in the PM1 register, both block A and block B
can be used. Table 7.4 shows Data Flash (addresses 0E000h to 0FFFFh).
Table 7.4
Data Flash (addresses 0E000h to 0FFFFh)
PM10 Bit in PM1 Register
Processor Modes
Single-chip mode
Memory expansion mode
Microprocessor mode
0
Unusable
External area
External area
1
Data flash
Data flash
Reserved area
Set the PRG2C0 bit in the PRG2C register to select program ROM 2. Table 7.5 shows Program ROM 2
(addresses 10000h to 13FFFh).
Do not use the last 16 bytes (addresses 13FF0h to 13FFFh) when using program ROM 2 in single-chip
mode or memory expansion mode. These bytes are assigned as the user boot code area (refer to 22.1.2
“User Boot Function”).
Table 7.5
Program ROM 2 (addresses 10000h to 13FFFh)
PRG2C0 bit in PRG2C Register
Processor Modes
Single-chip mode
Memory expansion mode
Microprocessor mode
0
Program ROM 2
Program ROM 2
Reserved area
1
Unusable
External area
External area
The range of program ROM 1 depends on the setting of the PM13 bit in the PM1 register. Figure 7.4 indicates the Memory Map in Single-Chip Mode.
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M16C/64 Group
7. Processor Mode
Single-chip Mode
00000h
SFR
00400h
Internal RAM
XXXXXh
Unusable
0D000h
SFR
0D800h
PM13 = 0
Internal RAM
Address XXXXXh
Size
12 Kbytes
033FFh
16 Kbytes
03FFFh (1)
31 Kbytes
03FFFh (1)
Internal ROM
Address YYYYYh
Size
128 Kbytes E0000h
256 Kbytes D0000h (1)
512 Kbytes D0000h (1)
PM13 = 1
Internal RAM
Address XXXXXh
Size
12 Kbytes
033FFh
16 Kbytes
043FFh
31 Kbytes
07FFFh
Internal ROM
Address YYYYYh
Size
128 Kbytes
E0000h
256 Kbytes
C0000h
512 Kbytes
80000h
Unusable
0E000h
10000h
14000h
Internal ROM (2)
(data flash)
Internal ROM (3)
(program ROM 2)
Unusable
YYYYYh
Internal ROM
(program ROM 1)
FFFFFh
NOTES :
1. If the PM13 bit is set to 0, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
2. Data flash can be used when the PM10 bit in the PM1 register is 1 (0E000h to 0FFFFh = data flash).
3. Program ROM 2 can be used when the PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled).
Figure 7.4
Memory Map in Single-Chip Mode
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M16C/64 Group
8.
8. Bus
Bus
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform
data input /output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0
to CS3, RD, WRL /WR, WRH / BHE, ALE, RDY, HOLD, HLDA, and BCLK.
8.1
Bus Mode
Bus mode, either multiplexed or separate, can be selected using bits PM05 and PM04 in the PM0 register. Table 8.1 shows the Difference between Separate Bus and Multiplexed Bus.
8.1.1
Separate Bus
In this bus mode, data and address are separate.
8.1.2
Multiplexed Bus
In this bus mode, data and address are multiplexed.
8.1.2.1
When the Input Level on BYTE Pin is High (8-Bit Data Bus)
D0 to D7 and A0 to A7 are multiplexed.
8.1.2.2
When the Input Level on BYTE Pin is Low (16-Bit Data Bus)
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External devices connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd addresses cannot be accessed.
Table 8.1
Difference between Separate Bus and Multiplexed Bus
Multiplexed Bus
BYTE = “H”
BYTE = “L”
Pin Name (1)
Separate Bus
P0_0 to P0_7 / D0 to D7
D0 to D7
(NOTE 2)
(NOTE 2)
P1_0 to P1_7 / D8 to D15
D8 to D15
I/O port
P1_0 to P1_7
(NOTE 2)
P2_0 / A0 (/ D0 / -)
A0
P2_1 to P2_7 / A1 to A7
(/ D1 to D7 / D0 to D6)
A1 to A7
A1 to A7 D1 to D7
P3_0 / A8 (/ - / D7)
A8
A8
A0
D0
A0
A1 to A7 D0 to D6
A8
D7
NOTES:
1. See Table 8.6 “Pin Functions for Each Processor Mode” for bus control signals other than the
above.
2. It changes with a setting of PM05 and PM04, and area to access.
See Table 8.6 “Pin Functions for Each Processor Mode” for details.
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M16C/64 Group
8.2
8. Bus
Bus Control
The following describes the signals needed for accessing external devices and the functionality of software wait.
8.2.1
Address Bus
The address bus consists of 20 lines: A0 to A19. The address bus width can be chosen to be 12, 16, or
20 bits by using the PM06 bit in the PM0 register and the PM11 bit in the PM1 register. Table 8.2 shows
the Set Value of Bits PM06 and PM11, and Address Bus Width.
Table 8.2
Set Value of Bits PM06 and PM11, and Address Bus Width
Bits Set Value (1)
PM11 = 1
PM06 = 1
PM11 = 0
PM06 = 1
PM11 = 0
PM06 = 0
Pin Function
P3_4 to P3_7
P4_0 to P4_3
A12 to A15
P4_0 to P4_3
A12 to A15
A16 to A19
Address Bus Width
12 bits
16 bits
20 bits
NOTE:
1. No values other than those shown above can be set.
When processor mode is changed from single-chip mode to memory expansion mode, the address bus
is indeterminate until any external area is accessed.
8.2.2
Data Bus
When input on the BYTE pin is high (data bus is 8 bits wide), 8 lines D0 to D7 comprise the data bus;
when input on the BYTE pin is low (data bus is 16 bits wide), 16 lines D0 to D15 comprise the data bus.
Do not change the input level on the BYTE pin while in operation.
8.2.3
Chip Select Signal
The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These
pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register. Figure 8.1
shows the CSR Register.
During 1-Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output
from the CSi pin. During 4-Mbyte mode, CSi signal or bank number is output from the CSi pin. Refer to
9. “Memory Space Expansion Function”. Figure 8.2 shows Examples of Address Bus and CSi Signal Output in 1-Mbyte mode.
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M16C/64 Group
8. Bus
Chip Select Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
CSR
0008h
01h
Bit Symbol
Bit Name
Function
0 : Disable chip select output
(functions as I/O port)
1 : Enable chip select output
RW
CS0
CS0 output enable bit
CS1
CS1 output enable bit
RW
CS2
CS2 output enable bit
RW
CS3
CS3 output enable bit
RW
0 : Wait state
1 : No wait state (1, 2, 3)
RW
CS0W
CS0 wait bit
CS1W
CS1 wait bit
RW
CS2W
CS2 wait bit
RW
CS3W
CS3 wait bit
RW
RW
NOTES :
1. When the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the CSiW bit to 0
(wait state).
2. When the PM17 bit in the PM1 register is set to 1 (wait state), set the CSiW bit to 0 (wait state).
3. When the CSiW bit = 0 (wait state), the number of wait states can be selected using bits CSEi1W to CSEi0W in the CSE
register.
Figure 8.1
CSR Register
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M16C/64 Group
8. Bus
Example 1
Example 2
To access the external area indicated by CSj in the next cycle after
accessing the external area indicated by CSi
To access the internal ROM or internal RAM in the next cycle after
accessing the external area indicated by CSi
The address bus and chip select signal both change state between these
two cycles.
The chip select signal changes state but the address bus does not change
state
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSj
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
Data
Data
Address Address
Data bus
Data
Address bus
Address
CSi
Access to the internal
ROM or internal RAM
CSi
CSj
Example 3
Example 4
To access the external area indicated by CSi in the next cycle after
accessing the external area indicated by the same CSi
Not to access any area (nor instruction prefetch generated) in the next cycle after
accessing the external area indicated by CSi
The address bus changes state but the chip select signal does not change
state
Access to the external
area indicated by CSi
Access to the same
external area
Neither the address bus nor the chip select signal changes state between these
two cycles
Access to the external
area indicated by CSi
BCLK
BCLK
Read signal
Read signal
Data bus
Address bus
Data
Data
Address Address
CSi
Data bus
Address bus
No access
Data
Address
CSi
NOTE :
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip
select bus cycle may be extended more than two cycles depending on a combination of these examples.
Shown above is the case where separate bus is selected and the area is accessed for read without wait states.
i = 0 to 3, j = 0 to 3 (not including i, however)
Figure 8.2
Examples of Address Bus and CSi Signal Output in 1-Mbyte Mode
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M16C/64 Group
8.2.4
8. Bus
Read and Write Signals
When the data bus is 16 bits wide, the read and write signals can be chosen to be a combination of RD,
BHE, and, WR or a combination of RD, WRL, and WRH by using the PM02 bit in the PM0 register.
When the data bus is 8 bits wide, use a combination of RD, WR, and BHE.
Table 8.3 shows the Operation of RD, WRL, and WRH Signals. Table 8.4 shows the Operation of RD,
WR, and BHE Signals.
Operation of RD, WRL, and WRH Signals
Table 8.3
RD
Data Bus Width
16-bit
(BYTE pin input = “L”)
WRL
L
H
H
H
H
L
H
L
WRH
Status of External Data Bus
H
H
L
L
Read data
Write 1 byte of data to an even address
Write 1 byte of data to an odd address
Write data to both even and odd addresses
Operation of RD, WR, and BHE Signals
Table 8.4
Data Bus
Width
16-bit
(BYTE pin
input = “L”)
RD
WR
BHE
A0
H
L
H
L
H
L
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
8-bit
(BYTE pin
input = “H”)
H
L
− (1)
Write 1 byte of data to an odd address
Read 1 byte of data from an odd address
Write 1 byte of data to an even address
Read 1 byte of data from an even address
Write data to both even and odd addresses
Read data from both even and odd addresses
H or L Write 1 byte of data
L
H
− (1)
H or L Read 1 byte of data
Status of External Data Bus
NOTE:
1. Do not use.
8.2.5
ALE Signal
The ALE signal latches the address when accessing the multiplexed bus space. Latch the address
when the ALE signal falls.
When BYTE pin input = “H”
When BYTE pin input = “L”
ALE
ALE
A0/D0 to A7/D7
Address
A8 to A19
Data
Address (1)
A0
A1/D0 to A8/D7
Address
Address
A9 to A19
NOTE :
1. If
the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.
Figure 8.3
ALE Signal, Address Bus, Data Bus
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Data
Address
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
8. Bus
RDY Signal
8.2.6
This signal is provided for accessing external devices which need to be accessed at low speed. If input
on the RDY pin is low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the
bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus
cycle is executed. Figure 8.4 shows Examples in which the Wait State was Inserted into Read Cycle by
RDY Signal. To use the RDY signal, set the corresponding bit (bits CS3W to CS0W) in the CSR register to 0 (with wait state). When not using the RDY signal, the RDY pin need to be pulled-up.
In an instance of separate bus
BCLK
RD
CSi
(i = 0 to 3)
RDY
tsu (RDY-BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CSi
(i = 0 to 3)
RDY
tsu (RDY-BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
tsu (RDY - BCLK) :
Duration for RDY input setup
Shown above is the case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register
are 00b (one wait state).
Figure 8.4
Examples in Which Wait State Was Inserted into Read Cycle by RDY Signal
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Specification in this preliminary version is subject to change.
M16C/64 Group
8.2.7
8. Bus
HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
input on the HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access at
that time finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
which time the HLDA pin outputs a low-level signal.
Table 8.5 shows the Microcomputer Status in Hold State.
Bus-using priorities are given to HOLD, DMAC, and CPU in descending order. However, if the CPU is
accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate
accesses.
HOLD > DMAC > CPU
Figure 8.5
Bus-Using Priorities
Table 8.5
Microcomputer Status in Hold State
Item
Status
BCLK
Output
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH,
WR, BHE
High-impedance
I/O ports
P0, P1, P3, P4 (1)
High-impedance
P6 to P10
Maintains status when HOLD signal is received
HLDA
Output “L”
Internal Peripheral Circuits
On (but watchdog timer stops) (2)
ALE
Undefined
NOTES:
1. When I/O port function is selected.
2. The watchdog timer does not stop when the CSPRO bit in the CSPR register is set to 1 (count source
protection mode enabled).
8.2.8
BCLK Output
If the PM07 bit in the PM0 register is set to 0 (output enabled), a clock with the same frequency as that
of the CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 “CPU Clock and Peripheral
Function Clock”.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 8.6
8. Bus
Pin Functions for Each Processor Mode
Processor Mode
Memory Expansion Mode or Microprocessor Mode
Bits PM05 and PM04
00b (separate bus)
01b (CS2 is for multiplexed bus and 11b (multiplexed bus for
the others are for separate bus)
10b (CS1 is for multiplexed bus and the entire space)
(1)
the others are for separate bus)
Data Bus Width
BYTE Pin
8 bits
“H”
16 bits
“L”
8 bits
“H”
16 bits
“L”
8 bits
“H”
P0_0 to P0_7
D0 to D7
D0 to D7
D0 to D7 (4)
D0 to D7 (4)
I/O ports
P1_0 to P1_7
I/O ports
D8 to D15
I/O ports
P2_0
A0
A0
A0/D0
P2_1 to P2_7
A1 to A7
A1 to A7
P3_0
A8
A8
P3_1 to P3_3
A9 to A11
I/O ports
P3_4 to
P3_7
PM11 = 0
A12 to A15
I/O ports
PM11 = 1
I/O ports
P4_0 to
P4_3
PM06 = 0
A16 to A19
PM06 = 1
I/O ports
P4_4
CS0 = 0
I/O ports
CS0 = 1
CS0
CS1 = 0
I/O ports
CS1 = 1
CS1
CS2 = 0
I/O ports
CS2 = 1
CS2
CS3 = 0
I/O ports
CS3 = 1
CS3
PM02 = 0
WR
PM02 = 1
- (3)
PM02 = 0
BHE
PM02 = 1
− (3)
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
Memory
Expansion Mode
D8 to
D15(4)
I/O ports
A0
A0/D0
A1 to A7
/D1 to D7 (2)
A1 to A7
/D0 to D6 (2)
A1 to A7
/D1 to D7
A8
A8/D7 (2)
A8
(2)
I/O ports
WRL
− (3)
WRL
− (3)
WRH
− (3)
WRH
− (3)
RD
P5_3
BCLK
P5_4
HLDA
P5_5
HOLD
P5_6
ALE
P5_7
RDY
I/O ports : Function as I/O ports or peripheral function I/O pins.
NOTES:
1. When bits PM01 and PM00 are set to 01b (memory expansion mode) and bits PM05 and PM04 are
set to 11b (multiplexed bus assigned to the entire CS space), apply “H” to the BYTE pin (external
data bus 8 bits wide). While the CNVSS pin is held “H” (= VCC1), do not rewrite bits PM05 and
PM04 to 11b after reset. If bits PM05 and PM04 are set to 11b during memory expansion mode,
P3_1 to P3_7 and P4_0 to P4_3 become I/O ports, in which case the accessible area for each CS is
256 bytes.
2. In separate bus mode, these pins serve as the address bus.
3. If the data bus is 8 bits wide, make sure the PM02 bit is set to 0 (RD, BHE, WR).
4. When accessing the area that uses a multiplexed bus, these pins output an indeterminate value during a write.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
8.2.9
8. Bus
External Bus Status When Internal Area IS Accessed
Table 8.7 shows the External Bus Status When Internal Area Accessed.
Table 8.7
External Bus Status When Internal Area Accessed
Item
SFR Accessed
A0 to A19
Internal ROM, RAM Accessed
Address output
Maintain the last accessed address of
external area or SFR
When Read
High-impedance
High-impedance
When Write
Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Output “H”
BHE
BHE output
Maintain the last accessed status of external area or SFR
CS0 to CS3
Output “H”
Output “H”
ALE
Output “L”
Output “L”
D0 to D15
8.2.10
Software Wait
The PM17 bit in the PM1 register, which is a software-wait-related bit, has an influence over the internal
memory and the external area.
The SFR area is accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. Data flash, one of the internal ROMs, is affected by the PM17 bit and the FMR17 bit in the FMR1
register. See Table 8.8 “Bits and Bus Cycles Related to Software Wait (SFR, Internal Memory)”
for details.
Software waits can be inserted to the external area by setting the PM17 bit or setting the CSiW bit in the
CSR register or bits CSEi1W to CSEi0W in the CSE register for each CSi (i = 0 to 3). To use the RDY
signal, set the corresponding CSiW bit to 0 (with wait state). Refer to Table 8.9 “Bits and Bus Cycles
Related to Software Wait (External Area)” for details.
Table 8.8 shows the Bits and Bus Cycles Related to Software Wait (SFR, Internal Memory), Figure 8.6
shows the CSE register, and Table 8.9 shows the Bits and Bus Cycles Related to Software Wait (External Area).
Table 8.8
Bits and Bus Cycles Related to Software Wait (SFR, Internal Memory)
Area
Setting of Software-Wait-related Bits
PM2 Register FMR1 Register PM1 Register
FMR17 Bit
PM17 Bit
PM20 Bit (1)
Software
Wait
Bus cycle
SFR
1
-
-
1 wait
0
-
-
0
2 BCLK cycles(3)
3 BCLK cycles
Program ROM 1 Program ROM 2
-
1
0
2 waits
No wait 1 BCLK cycle(3)
1 wait
2 BCLK cycles
No wait 1 BCLK cycle(3)
-
0
1
-
1 wait
1 wait
Internal
RAM
Internal
ROM
Data Flash (2)
1
0
1
2 BCLK cycles
2 BCLK cycles(3)
No wait 1 BCLK cycle
1 wait
2 BCLK cycle
− indicates that either 0 or 1 can be set.
NOTES:
1. The PM 20 bit is valid when the PLC07 bit in the PLC0 register is set to 1 (PLL operation).
2. When 2.7 V ≤ VCC1 ≤ 3.0 V and f (BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f (BCLK) ≥
20 MHz, 1 wait is necessary to read data flash. Use the PM17 bit or the FMR 17 bit to set 1 wait.
3. Status after reset.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
8. Bus
Chip Select Expansion Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
CSE
001Bh
00h
Bit Symbol
Bit Name
Function
b1
CSE00W
CS0 wait expansion bit (1)
CSE01W
0
0
1
1
b3
CSE10W
CS1 wait expansion bit (1)
CSE11W
0
0
1
1
b5
CSE20W
CS2 wait expansion bit (1)
CSE21W
0
0
1
1
b7
CSE30W
CS3 wait expansion bit (1)
CSE31W
0
0
1
1
b0
0 : 1 wait
1 : 2 waits
0 : 3 waits
1 : Do not set
b2
0 : 1 wait
1 : 2 waits
0 : 3 waits
1 : Do not set
b4
0 : 1 wait
1 : 2 waits
0 : 3 waits
1 : Do not set
b6
0 : 1 wait
1 : 2 waits
0 : 3 waits
1 : Do not set
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTE :
1. Set the CSiW bit (i = 0 to 3) in the CSR register to 0 (wait state) before writing to bits CSEi1W to CSEi0W. If the CSiW bit
needs to be set to 1 (no wait state), set bits CSEi1W and CSEi0W to 00b before setting it.
Figure 8.6
CSE Register
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 8.9
8. Bus
Bits and Bus Cycles Related to Software Wait (External Area)
Area
Bus Mode
Setting of Software-Wait-related Bits
Software
Wait
CSE Register
PM1 Regis- CSR Register
Bits CSEi1W to
ter PM17 Bit CSiW Bit (1)
CSEi0W
0
1
00b
No wait
Bus Cycle
External
Area
Separate
Bus
-
0
00b
1 wait
1
0
0
0 (3)
01b
10b
00b
2 waits
3 waits
1 wait
2 BCLK cycles (4)
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
Multiplexed Bus
-
0 (2)
00b
1 wait
3 BCLK cycles
(2)
01b
2 waits
3 BCLK cycles
-
0 (2)
10b
3 waits
4 BCLK cycles
1
0 (2, 3)
00b
1 wait
3 BCLK cycles
0
1 BCLK cycle
(Read)
2 BCLK cycles
(Write)
i = 0 to 3
− indicates that either 0 or 1 can be set.
NOTES:
1. To use the RDY signal, set the CSiW bit to 0 (with wait state).
2. To access in multiplexed bus mode, set the CSiW bit to 0 (with wait state).
3. When the PM17 bit is set to 1 and accesses an external area, set the CSiW bit to 0 (with wait state).
4. After reset, the PM17 bit is set to 0 (without wait state), bits CS0W to CS3W are set to 0 (with wait
state), and the CSE register is set to 00h (one wait state for CS0 to CS3). Therefore, all external
areas are accessed with one wait state.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
8. Bus
(1) Separate Bus, No Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Address
Input
Address
CS
(2) Separate Bus, 1-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Input
Address
Address
CS
(3) Separate Bus, 2-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Address bus
Output
Address
Input
Address
CS
NOTE :
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and
write cycles in succession.
Figure 8.7
Typical Bus Timings Using Software Wait (1)
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
8. Bus
(1) Separate Bus, 3-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
Data bus
Input
Output
Address
Address bus
Address
CS
(2) Multiplexed Bus, 1- or 2-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
ALE
Address bus/
Data bus
Address
Address
Address bus
Address
Data output
Address
Input
CS
(3) Multiplexed Bus, 3-Wait Setting
Bus cycle (1)
Bus cycle (1)
BCLK
Write signal
Read signal
ALE
Address bus
Address bus/
Data bus
Address
Address
Address
Data output
Address
Input
CS
NOTE :
1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in
succession.
Figure 8.8
Typical Bus Timings Using Software Wait (2)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9.
9. Memory Space Expansion Function
Memory Space Expansion Function
The following describes a memory space expansion function.
During memory expansion or microprocessor mode, the memory space expansion function allows the
access space to be expanded using the appropriate register bits.
Table 9.1 shows Setting of Memory Space Expansion Function, Memory Space.
Table 9.1
Setting of Memory Space Expansion Function, Memory Space
Memory Space Expansion Function
1-Mbyte Mode
4-Mbyte Mode
9.1
Setting (PM15 to PM14)
00b
11b
Memory Space
1 Mbyte (no expansion)
4 Mbytes
1-Mbyte Mode
In this mode, the memory space is 1 Mbyte. In 1-Mbyte mode, the external area to be accessed is specified using the CSi (i = 0 to 3) signals (hereafter referred to as the CSi area). Figures 9.2 and 9.3 show the
Memory Mapping and CS Area in 1-Mbyte mode.
9.2
4-Mbyte Mode
In this mode, the memory space is 4 Mbytes. Figure 9.1 shows the DBR Register. Bits BSR2 to BSR0 in
the DBR register select a bank number which is to be accessed to read or write data. Setting the OFS bit
to 1 (with offset) allows the accessed address to be offset by 40000h.
In 4-Mbyte mode, the CSi (i = 0 to 3) pin function differs depending on an area to be accessed.
9.2.1
Addresses 04000h to 3FFFFh, C0000h to FFFFFh
• The CSi signal is output from the CSi pin (same operation as 1-Mbyte mode; however, the last
address of the CS1 area is 3FFFFh).
9.2.2
Addresses 40000h to BFFFFh
• The CS0 pin outputs “L”
• Pins CS1 to CS3 output the setting values of bits BSR2 to BSR0 (bank number)
Figures 9.4 and 9.5 show the Memory Mapping and CS Area in 4-Mbyte mode. Note that banks 0 to 6
are data-only areas. Locate the program in bank 7 or the CSi area.
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Data Bank Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
DBR
000Bh
00h
Bit Symbol
—
(b1-b0)
OFS
Bit Name
Function
No register bits. If necessary, set to 0. Read as 0
Offset bit
0 : Not offset
1 : Offset
Bank selection bits
b5 b4 b3
0 0 0 : Bank 0
0 1 0 : Bank 2
1 0 0 : Bank 4
1 1 0 : Bank 6
—
RW
BSR0
BSR1
RW
b5 b4 b3
0 0 1 : Bank 1
0 1 1 : Bank 3
1 0 1 : Bank 5
1 1 1 : Bank 7
BSR2
—
(b7-b6)
No register bits. If necessary, set to 0. Read as 0
DBR Register
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RW
RW
NOTE :
1. Effective when bits PM01 and PM00 in the PM0 register are set to 01b (memory expansion mode) or 11b
(microprocessor mode).
Figure 9.1
RW
Oct 12, 2007
—
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Memory expansion mode
00000h
00400h
XXXXXh
Microprocessor mode
SFR
SFR
Internal RAM
Internal RAM
Reserved area
Reserved area
04000h
CS3 (16 Kbytes)
08000h
0D000h
0D800h
0E000h
10000h
External area
SFR
SFR
Data flash
CS2 (20 Kbytes)
(3)
Prpgram ROM 2 (4)
Reserved, external area
(2)
Reserved, external area
(5)
14000h
27000h
Reserved area
Reserved area
External area
External area
28000h
30000h
CS2
CS2
CS2
(16 Kbytes)
CS2
(76 Kbytes)
(2 Kbytes)
(8 Kbytes)
CS2 (102 Kbytes )
CS1 (32 Kbytes)
CS0 (memory expansion mode : 640 Kbytes )
D0000h
Reserved area
CS0 (microprocessor mode : 832 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13 = 0
Internal RAM
Capacity
Address XXXXXh
Internal ROM
Capacity Address YYYYYh
128 Kbytes E0000h
256 Kbytes D0000h (1)
512 Kbytes D0000h (1)
12 Kbytes 033FFh
16 Kbytes 03FFFh (1)
31 Kbytes 03FFFh (1)
External Area
CS1
CS0
Memory expansion mode
30000h to CFFFFh
28000h to
2FFFFh
Microprocessor mode
30000h to FFFFFh
CS2
CS3
08000h to 0CFFFh
04000h to
0D800h to 26FFFh
Note that this applies to the 07FFFh
following areas only in the
conditions described below.
In memory expansion mode
or when PM10 = 0,
08000h to 0CFFFh
When PM10 = 0,
0E000h to 0FFFFh
When PRG2C0 = 1
10000h to 13FFFh
NOTES :
1. When the PM13 bit in the PM1 register is set to 0, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
2. When the PM10 bit is set to 0, this area is used as external area; when 1, reserved area.
3. When the PM10 bit is set to 0, this area is used as external area; when 1, internal ROM (data flash).
4. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, internal ROM (program ROM 2).
5. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, reserved area.
Figure 9.2
Memory Mapping and CS Area in 1-Mbyte Mode (PM13 = 0)
Memory expansion mode
00000h
00400h
XXXXXh
08000h
0D000h
0D800h
0E000h
10000h
Microprocessor mode
SFR
SFR
Internal RAM
Internal RAM
Reserved area
Reserved area
SFR
SFR
Data flash
(1)
Program ROM 2
(2)
Reserved, external area
(3)
Reserved, external area
(4)
14000h
27000h
Reserved area
(16 Kbytes)
CS2
(76 Kbytes)
(2 Kbytes)
(8 Kbytes)
CS2 (102 Kbytes)
Reserved area
28000h
30000h
CS2
CS2
CS2
CS1 (32 Kbytes)
External area
External area
CS0 (memory expansion mode : 320 Kbytes)
80000h
Reserved area
CS0 (misropocessor mode : 832 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13 = 1
Internal RAM
Internal ROM
Capacity Address XXXXXh Capacity Address YYYYYh
CS0
128 Kbytes
E0000h
12 Kbytes
033FFh
Memory expansion mode
30000h to 7FFFFh
256 Kbytes
C0000h
16 Kbytes
043FFh
Microprocessor mode
30000h to FFFFFh
External area
CS1
CS2
0D800h to 26FFFh
28000h to
Note that this applies to the
2FFFFh
following areas only in the
CS3
No area
conditions described below.
When PM10 = 0,
0E000h to 0FFFFh
When PRG2C0 = 1,
10000h to 13FFFh
NOTES :
1. When the PM10 bit is set to 0, this area is used as external area; when 1, internal ROM (data flash).
2. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, internal ROM (program ROM 2).
3. When the PM10 bit is set to 0, this area is used as external area; when 1, reserved area.
4. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, reserved area.
Figure 9.3
Memory Mapping and CS Area in 1-Mbyte Mode (PM13 = 1)
REJ09B0392-0064 Rev.0.64
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Memory expansion mode
00000h
00400h
XXXXXh
Microprocessor mode
SFR
SFR
Internal RAM
Internal RAM
Reserved area
Reserved area
04000h
08000h
0D000h
0D800h
0E000h
10000h
CS3 (16 Kbytes)
External area
SFR
SFR
Data flash
(4)
Program ROM 2
Reserved, external area
(5)
Reserved area
Reserved area
External area
External area
28000h
40000h
(3)
Reserved, external area (6)
14000h
27000h
CS2 (20 Kbytes)
CS2
CS2
CS2
(16 Kbytes)
CS2
(76 Kbytes)
(8 Kbytes)
CS2 (102 Kbytes)
CS1 (96 Kbytes)
Other than the CS area (512 Kbytes x 8 banks)
C0000h
D0000h
(2 Kbytes)
CS0 (memory expansion mode : 64 Kbytes)
Reserved area
CS0 (misropocessor mode : 256 Kbytes)
YYYYYh
Internal ROM
FFFFFh
PM13 = 0
Internal RAM
Internal ROM
Capacity Address XXXXXh Capacity Address YYYYYh
CS0
12 Kbytes 033FFh
128 Kbytes E0000h
Memory expansion mode
(2)
(2)
C0000h
to
CFFFFh
256
Kbytes
D0000h
03FFFh
16 Kbytes
512 Kbytes D0000h (2)
31 Kbytes 03FFFh (2)
Microprocessor mode
C0000h to FFFFFh
CS1
28000h to
3FFFFh
External area
CS2
08000h to 0CFFFh
0D800h to 26FFFh
Note that this applies to the
following areas only in the
conditions described below.
CS3
04000h to
07FFFh
Other than the CS area (1)
40000h to BFFFFh
Inmemory expansion mode
or when PM10 = 0,
08000h to 0CFFFh
When PM10 = 0,
0E000h to 0FFFFh:
When PRG2C0 = 1,
10000h to 13FFFh
NOTES :
1. The CS0 pin outputs a low signal, and pins CS1 to CS3 output a bank number.
2. When the PM13 bit is set to 0, 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
3. When the PM10 bit is set to 0, this area is used as external area; when 1, reserved area.
4. When the PM10 bit is set to 0, this area is used as external area; when 1, internal ROM (data flash).
5. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, internal ROM (program ROM 2).
6. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, reserved area.
Figure 9.4
Memory Mapping and CS Area in 4-Mbyte Mode (PM13 = 0)
Memory expansion mode
00000h
00400h
XXXXXh
08000h
0D000h
0D800h
0E000h
10000h
Microprocessor mode
SFR
SFR
Internal
RAM
Internal RAM
Reserved area
Reserved area
SFR
Data flash (2)
SFR
Reserved, external area
Program ROM 2 (3)
Reserved, external area (5)
Reserved area
Reserved area
14000h
27000h
28000h
40000h
YYYYYh
FFFFFh
CS2
CS2
CS2
(16 Kbytes)
CS2
(76 Kbytes)
(2 Kbytes)
(8 Kbytes)
CS2 (102 Kbytes)
CS1 (96 Kbytes)
External area
External area
80000h
C0000h
(4)
Other than the CS area (memory expansion mode: 256 Kbytes x 8 banks)
* Change offset to use 256 Kbytes x 8 banks x2
Other than the CS area (microprocessor mode: 512 Kbytes x 8 banks)
Reserved area
CS0 (misropocessor mode: 256 Kbytes)
Internal ROM
PM13 = 1
Internal RAM
Internal ROM
Capacity Address XXXXXh Capacity Address YYYYYh
CS0
12 Kbytes
033FFh
128 Kbytes
E0000h
Microprocessor mode
16 Kbytes
256 Kbytes
C0000h
C0000h to FFFFFh
043FFh
31 Kbytes
07FFFh
512 Kbytes
80000h
CS1
28000h to
3FFFFh
External Area
CS2
0D800h to 26FFFh
Note that this applies to the
following areas only in the
conditions described below.
CS3
No area
When PM10 = 0,
0E000h to 0FFFFh
When PRG2C0 = 1,
10000h to 13FFFh
NOTES :
1. The CS0 pin outputs a low signal, and pins CS1 to CS3 output a bank number.
2. When the PM10 bit is set to 0, this area is used as external area; when 1, internal ROM (data flash).
3. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, internal ROM (program ROM 2).
4. When the PM10 bit is set to 0, this area is used as external area; when 1, reserved area.
5. When the PRG2C0 bit in the PRG2C register is set to 1, this area is used as external area; when 0, reserved area.
Figure 9.5
Memory Mapping and CS Area in 4-Mbyte Mode (PM13 = 1)
REJ09B0392-0064 Rev.0.64
Page 69 of 373
Oct 12, 2007
Other than the CS area (1)
Memory expansion mode
40000h to 7FFFFh
Microprocessor mode
40000h to BFFFFh
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Figure 9.6 shows the External Memory Connect Example in 4-Mbyte Mode.
In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of the microcomputer. The 4Mbyte ROM address input pins AD21, AD20, and AD19 are connected to pins CS3, CS2, and CS1 of
the microcomputer, respectively. The address input AD18 pin is connected to the A19 pin of microcomputer. Figures 9.7 to 9.9 show the relationship of addresses between the 4-Mbyte ROM and the microcomputer for the case of a connection example in Figure 9.6.
In microprocessor mode or in memory expansion mode where the PM13 bit in the PM1 register is 0,
banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to 1 (offset) allows the
accessed address to be offset by 40000h, so that even the data overlapping at a bank boundary can be
accessed in succession.
In memory expansion mode where the PM13 bit is 1, each 512-Kbyte bank can be accessed in 256
Kbyte units by switching them over with the OFS bit.
Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and S1 = “L”,
CS0 and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins
which accept “H” active and “L” active chip select signals (S1, S2), CS0 and CS2 should be decoded
external to the chip.
17
DQ0 to DQ7
AD0 to AD16
A17
AD17
A19
AD18
CS1
AD19
CS2
AD20
CS3
AD21
OE
RD
CS0
CS
WR
DQ0 to
DQ7
AD0 to
AD16
OE
S2
S1 (1)
W
4-Mbyte ROM
Microcomputer
A0 to A16
8
128-Kbyte SRAM
D0 to D7
NOTE :
1. If only one chip select pin (S1 or S2) is present, using an external circuit is required for decode.
Figure 9.6
External Memory Connect Example in 4-Mbyte Mode
REJ09B0392-0064 Rev.0.64
Page 70 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Memory expansion mode where PM13 = 0
ROM address
Microcomputer address
OFS bit in DBR
register = 0
000000h
040000h
bank 0
(512 Kbytes)
080000h
40000h
0C0000h
bank 1
(512 Kbytes)
100000h
40000h
140000h
bank 2
(512 Kbytes)
180000h
BFFFFh
40000h
1C0000h
bank 3
(512 Kbytes)
200000h
BFFFFh
40000h
240000h
bank 4
(512 Kbytes)
280000h
BFFFFh
40000h
2C0000h
bank 5
(512 Kbytes)
300000h
BFFFFh
40000h
340000h
bank 6
(512 Kbytes)
380000h
BFFFFh
40000h
3C0000h
bank 7
(512 Kbytes)
3FFFFFh
BFFFFh
BFFFFh
Program
or data
Program
or data
Bank
Number
40000h
BFFFFh
Data only
OFS bit in DBR
register = 1
OFS
0
40000h
0
1
bank 0
(512 Kbytes)
BFFFFh
40000h
0
1
1
bank 1
(512 Kbytes)
BFFFFh
40000h
0
2
1
bank 2
(512 Kbytes)
BFFFFh
40000h
0
3
1
bank 3
(512 Kbytes)
BFFFFh
40000h
0
4
1
bank 4
(512 Kbytes)
BFFFFh
40000h
0
5
1
bank 5
(512 Kbytes)
BFFFFh
40000h
0
6
1
bank 6
(512 Kbytes)
BFFFFh
7
0
Output from the Microcomputer Pins
Access
Area
CS Output
Address Output
CS3
CS2
CS1
A19
A18
A17
40000h
0
0
0
0
1
0
A16 A15 to A0
0
0000h
BFFFFh
0
0
0
1
0
1
1
FFFFh
07FFFFh
40000h
0
0
0
1
0
0
0
0000h
040000h
BFFFFh
0
0
1
0
1
1
1
FFFFh
0BFFFFh
40000h
BFFFFh
40000h
0
0
1
0
1
0
0
0000h
080000h
0
0
1
1
0
1
1
FFFFh
0FFFFFh
0
0
1
1
0
0
0
0000h
0C0000h
BFFFFh
0
1
0
0
1
1
1
FFFFh
13FFFFh
40000h
0
1
0
0
1
0
0
0000h
100000h
BFFFFh
0
1
0
1
0
1
1
FFFFh
17FFFFh
40000h
0
1
0
1
0
0
0
0000h
140000h
BFFFFh
0
1
1
0
1
1
1
FFFFh
1BFFFFh
40000h
0
1
1
0
1
0
0
0000h
180000h
BFFFFh
0
1
1
1
0
1
1
FFFFh
1FFFFFh
40000h
0
1
1
1
0
0
0
0000h
1C0000h
BFFFFh
1
0
0
0
1
1
1
FFFFh
23FFFFh
40000h
1
0
0
0
1
0
0
0000h
200000h
BFFFFh
1
0
0
1
0
1
1
FFFFh
27FFFFh
40000h
1
0
0
1
0
0
0
0000h
240000h
BFFFFh
1
0
1
0
1
1
1
FFFFh
2BFFFFh
40000h
1
0
1
0
1
0
0
0000h
280000h
BFFFFh
1
0
1
1
0
1
1
FFFFh
2FFFFFh
40000h
1
0
1
1
0
0
0
0000h
2C0000h
BFFFFh
1
1
0
0
1
1
1
FFFFh
33FFFFh
40000h
1
1
0
0
1
0
0
0000h
300000h
BFFFFh
1
1
0
1
0
1
1
FFFFh
37FFFFh
40000h
1
1
0
1
0
0
0
0000h
340000h
BFFFFh
1
1
1
0
1
1
1
FFFFh
40000h
1
1
1
0
1
0
0
0000h
3BFFFFh
380000h
7FFFFh
1
1
1
0
1
1
1
FFFFh
80000h
1
1
1
1
0
0
0
0000h
BFFFFh
1
1
1
1
0
1
1
FFFFh
C0000h
1
1
1
1
1
0
0
0000h
CFFFFh
1
1
1
1
1
0
0
FFFFh
3BFFFFh
3C0000h
3FFFFFh
3C0000h
3CFFFFh
D0000h
Internal ROM access
DFFFFh
Internal ROM access
D0000h
Internal ROM access
DFFFFh
Internal ROM access
A21
A20
A19
A18
N.C.
A17
A16 A15 to A0
Address input for 4-Mbyte ROM
Figure 9.7
000000h
4-Mbyte ROM
access area
Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (1)
REJ09B0392-0064 Rev.0.64
Page 71 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Memory expansion mode where PM13 = 1
ROM address
Microcomputer address
OFS bit in DBR
register = 0
000000h
OFS bit in DBR
register = 1
Bank
Number
bank 0 40000h
0
(256 Kbytes)
7FFFFh
040000h
bank 0
40000h
0
1
(256 Kbytes)
7FFFFh
080000h
bank 1 40000h
0
(256 Kbytes)
7FFFFh
40000h
(256 Kbytes)
7FFFFh
bank 1
0C0000h
100000h
Data only
40000h
(256 Kbytes)
7FFFFh
bank 2
1C0000h
40000h
(256 Kbytes)
7FFFFh
bank 3
3
1
bank 4 40000h
240000h
0
bank 4
40000h
4
1
(256 Kbytes)
7FFFFh
bank 5 40000h
0
(256 Kbytes)
7FFFFh
40000h
(256 Kbytes)
7FFFFh
2C0000h
300000h
1
0
(256 Kbytes)
7FFFFh
280000h
2
bank 3 40000h
(256 Kbytes)
7FFFFh
200000h
1
0
(256 Kbytes)
7FFFFh
180000h
1
bank 2 40000h
140000h
bank 5
5
1
bank 6 40000h
0
(256 Kbytes)
7FFFFh
340000h
bank 6
40000h
6
1
(256 Kbytes)
7FFFFh
Program
or data
Data only
380000h
OFS
bank 7 40000h
(256 Kbytes)
7FFFFh
3C0000h
3FFFFFh
bank 7
40000h
7
0
(256 Kbytes)
7FFFFh
Output from the Microcomputer Pins
Access
Area
CS Output
Address Output
CS3
CS2
CS1
A19
A18
A17
A16
40000h
0
0
0
0
1
0
0
A15 to A0
0000h
000000h
7FFFFh
0
0
0
0
1
1
1
FFFFh
03FFFFh
40000h
0
0
0
1
0
0
0
0000h
040000h
7FFFFh
0
0
0
1
0
1
1
FFFFh
07FFFFh
40000h
0
0
1
0
1
0
0
0000h
080000h
7FFFFh
0
0
1
0
1
1
1
FFFFh
0BFFFFh
40000h
0
0
1
1
0
0
0
0000h
0C0000h
7FFFFh
0
0
1
1
0
1
1
FFFFh
0FFFFFh
40000h
0
1
0
0
1
0
0
0000h
100000h
7FFFFh
0
1
0
0
1
1
1
FFFFh
13FFFFh
40000h
0
1
0
1
0
0
0
0000h
140000h
7FFFFh
0
1
0
1
0
1
1
FFFFh
17FFFFh
40000h
0
1
1
0
1
0
0
0000h
180000h
7FFFFh
0
1
1
0
1
1
1
FFFFh
1BFFFFh
40000h
0
1
1
1
0
0
0
0000h
1C0000h
7FFFFh
0
1
1
1
0
1
1
FFFFh
1FFFFFh
40000h
1
0
0
0
1
0
0
0000h
200000h
7FFFFh
1
0
0
0
1
1
1
FFFFh
23FFFFh
40000h
1
0
0
1
0
0
0
0000h
240000h
7FFFFh
1
0
0
1
0
1
1
FFFFh
27FFFFh
40000h
1
0
1
0
1
0
0
0000h
280000h
7FFFFh
1
0
1
0
1
1
1
FFFFh
2BFFFFh
40000h
1
0
1
1
0
0
0
0000h
2C0000h
7FFFFh
1
0
1
1
0
1
1
FFFFh
2FFFFFh
40000h
1
1
0
0
1
0
0
0000h
300000h
7FFFFh
1
1
0
0
1
1
1
FFFFh
33FFFFh
40000h
1
1
0
1
0
0
0
0000h
340000h
7FFFFh
1
1
0
1
0
1
1
FFFFh
37FFFFh
40000h
1
1
1
0
1
0
0
0000h
380000h
7FFFFh
1
1
1
0
1
1
1
FFFFh
80000h
FFFFFh
7
1
Internal ROM access
40000h
1
1
1
1
0
0
0
0000h
7FFFFh
1
1
1
1
0
1
1
FFFFh
80000h
3C0000h
3FFFFFh
Internal ROM access
FFFFFh
Internal ROM access
A21
A20
A19
A18
N.C.
A17
A16 A15 to A0
Address input for 4-Mbyte ROM
Figure 9.8
3BFFFFh
Internal ROM access
4-Mbyte ROM
access area
Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (2)
REJ09B0392-0064 Rev.0.64
Page 72 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
9. Memory Space Expansion Function
Microprocessor mode
ROM address
Microcomputer address
OFS bit in DBR
register = 0
bank 0
(512 Kbytes)
BFFFFh
080000h
40000h
(512 Kbytes)
BFFFFh
40000h
100000h
140000h
(512 Kbytes)
BFFFFh
40000h
180000h
Data only
1C0000h
(512 Kbytes)
BFFFFh
40000h
240000h
(512 Kbytes)
BFFFFh
40000h
280000h
2C0000h
(512 Kbytes)
BFFFFh
40000h
300000h
bank 6
340000h
40000h
(512 Kbytes)
Program
or data
380000h
Program
or data
3C0000h
BFFFFh
bank 7 40000h
(512 Kbytes)
7FFFFh
C0000h
3FFFFFh
FFFFFh
0
1
1
bank 1
(512 Kbytes)
40000h
0
2
1
bank 2
(512 Kbytes)
40000h
0
3
1
bank 3
(512 Kbytes)
40000h
0
4
1
bank 4
(512 Kbytes)
BFFFFh
bank 5
1
(512 Kbytes)
BFFFFh
bank 4
0
bank 0
BFFFFh
bank 3
200000h
40000h
BFFFFh
bank 2
OFS
0
BFFFFh
bank 1
0C0000h
Output from the Microcomputer Pins
Bank
Number
40000h
000000h
040000h
OFS bit in DBR
register = 1
40000h
0
5
1
bank 5
(512 Kbytes)
BFFFFh
40000h
0
6
1
bank 6
(512 Kbytes)
BFFFFh
7
0
Access
Area
CS Output
Address Output
CS3
CS2
CS1
A19
A18
A17
40000h
0
0
0
0
1
0
A16 A15 to A0
0
0000h
000000h
BFFFFh
0
0
0
1
0
1
1
FFFFh
07FFFFh
40000h
0
0
0
1
0
0
0
0000h
040000h
BFFFFh
0
0
1
0
1
1
1
FFFFh
0BFFFFh
40000h
0
0
1
0
1
0
0
0000h
080000h
BFFFFh
0
0
1
1
0
1
1
FFFFh
0FFFFFh
40000h
0
0
1
1
0
0
0
0000h
0C0000h
BFFFFh
0
1
0
0
1
1
1
FFFFh
13FFFFh
40000h
0
1
0
0
1
0
0
0000h
100000h
BFFFFh
0
1
0
1
0
1
1
FFFFh
17FFFFh
40000h
0
1
0
1
0
0
0
0000h
140000h
BFFFFh
0
1
1
0
1
1
1
FFFFh
1BFFFFh
40000h
0
1
1
0
1
0
0
0000h
180000h
BFFFFh
0
1
1
1
0
1
1
FFFFh
1FFFFFh
40000h
0
1
1
1
0
0
0
0000h
1C0000h
BFFFFh
1
0
0
0
1
1
1
FFFFh
23FFFFh
40000h
1
0
0
0
1
0
0
0000h
200000h
BFFFFh
1
0
0
1
0
1
1
FFFFh
27FFFFh
40000h
1
0
0
1
0
0
0
0000h
240000h
BFFFFh
1
0
1
0
1
1
1
FFFFh
2BFFFFh
40000h
1
0
1
0
1
0
0
0000h
280000h
BFFFFh
1
0
1
1
0
1
1
FFFFh
2FFFFFh
40000h
1
0
1
1
0
0
0
0000h
2C0000h
BFFFFh
1
1
0
0
1
1
1
FFFFh
33FFFFh
40000h
1
1
0
0
1
0
0
0000h
300000h
BFFFFh
1
1
0
1
0
1
1
FFFFh
37FFFFh
40000h
1
1
0
1
0
0
0
0000h
340000h
BFFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
40000h
1
1
1
0
1
0
0
0000h
380000h
7FFFFh
1
1
1
0
1
1
1
FFFFh
3BFFFFh
80000h
1
1
1
1
0
0
0
0000h
3C0000h
BFFFFh
1
1
1
1
0
1
1
FFFFh
3FFFFFh
C0000h
1
1
1
1
1
0
0
0000h
3C0000h
FFFFFh
1
1
1
1
1
1
1
FFFFh
A21
A20
A19
A18
N.C.
A17
A16 A15 to A0
Address input for 4-Mbyte ROM
Figure 9.9
3FFFFFh
4-Mbyte ROM
access area
Relationship Between Addresses on 4-Mbyte ROM and Those on Microcomputer (3)
REJ09B0392-0064 Rev.0.64
Page 73 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
10. Clock Generation Circuit
10.1
Type of the Clock Generation Circuit
4 circuits are incorporated to generate the system clock signal:
• Main clock oscillation circuit
• Sub clock oscillation circuit
• 125 kHz on-chip oscillator
• PLL frequency synthesizer
Table 10.1 lists the Clock Generation Circuit Specifications. Figure 10.1 shows the System Clock Generation Circuit.
Figures 10.2 to 10.6 show the clock-related registers.
Table 10.1
Clock Generation Circuit Specifications
Item
Use of Clock
Clock Frequency
Usable Oscillator
Pins to Connect
Oscillator
Oscillation Stop,
Restart Function
Oscillator Status
After Reset
Other
Main Clock
Oscillation Circuit
CPU clock source
Peripheral function
clock source
Sub Clock
Oscillation Circuit
CPU clock source
Clock source of
timer A and B.
PLL Frequency
Synthesizer
CPU clock source
Peripheral function
clock source
32.768 kHz
Crystal oscillator
125 kHz On-Chip
Oscillator
CPU clock source
Peripheral function
clock source
CPU and peripheral
function clock
sources when the
main clock stops
oscillating
About 125 kHz
-
0 to 20 MHz
Ceramic oscillator
Crystal oscillator
XIN, XOUT
XCIN, XCOUT
-
- (1)
Presence
Presence
Presence
Presence
Oscillating
Stopped
Oscillating
Stopped
-
- (1)
Externally derived clock can be input
10 to 25 MHz
- (1)
NOTE:
1. The PLL frequency synthesizer uses the main clock oscillation circuit as a reference clock source.
The items above are based on those of the main clock oscillation circuit.
REJ09B0392-0064 Rev.0.64
Page 74 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
Subclock
oscillation circuit
XCIN
I/O ports
CM01 to CM00 = 00b
PM01 to PM00 = 00b, CM01 to CM00 = 01b
PM01 to PM00 = 00b, CM01 to CM00 = 10b
XCOUT
1/32
CM04
fC32
CLKOUT
PM01 to PM00 = 00b,
CM01 to CM00 = 11b
Subclock
fC
CM14
125 kHz
on-chip
oscillator
Oscillation
stop,
re-oscillation
detection
circuit
CM10 = 1 (stop mode)
S Q
XIN
XOUT
R
Main
clock
CM05
PLL
frequency
synthesizer
PLL
clock
1
0
Main clock
oscillation circuit
f8
125 kHz
on-chip
oscillator
clock
f32
fOCO-S
f1
PM25
b c
a
CM21=1
d
Divider
CPU clock
fC
CM21=0
CM11
D4INT clock
CM07=0
BCLK
CM07=1
CM02
S
WAIT instruction
Q
R
c
b
a
RESET
Software reset
1/2
1/2
1/2
1/2
1/2
1/2
1/4
1/8
1/32
1/16
NMI
CM06 = 0
CM17 to CM16 = 11b
PM24 Interrupt request level judgement output
Brown-out reset
Watchdog timer reset
Oscillation stop detect reset
CM06 = 1
CM06 = 0
CM17 to CM16 = 10b
CM02, CM04, CM05, CM06, CM07 : bits in the CM0 register
CM10, CM11, CM14, CM16, CM17 : bits in the CM1 register
PCLK0, PCLK1 : bits in the PCLKR register
CM21, CM27
: bits in the CM2 register
d
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
Details of the Divider
Oscillation Stop, Re-Oscillation Detection Circuit
Pulse generation
circuit for clock
edge detection
and charge /
discharge control
Main
clock
CM27 = 0
Reset
generating
circuit
CM27 = 1
Oscillation stop,
re-oscillation
detection interrupt
generating circuit
Charge /
discharge
circuit
Oscillation stop
detection reset
Oscillation stop,
re-oscillation
detection interrupt
signal
CM21 switch signal
PLL Frequency Synthesizer
1/32
Divider
Phase
comparator
Main clock
Reference
clock divider
Charge
pump
Voltage
control
oscillator
(VCO)
Internal lowpass
filter
Figure 10.1
System Clock Generation Circuit
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Oct 12, 2007
PLL clock
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
System Clock Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
0006h
Bit Name
Bit Symbol
CM00
CM01
After Reset
01001000b
Function
b1
Clock output function select bit 0
0
(valid only in single-chip
1
mode)
1
b0
0 : I/O port P5_7
1 : Output fC
0 : Output f8
1 : Output f32
0 : Peripheral function clock f1 does not
stop in wait mode
1 : Peripheral function clock f1 stops in
wait mode (8)
CM02
WAIT mode peripheral
function clock stop bit (10)
CM03
XCIN-XCOUT drive capacity select 0 : Low
bit (2)
1 : High
CM04
Port XC select bit (2)
CM05
CM06
CM07
Main clock stop bit
(3, 4, 10, 12, 13)
Main clock division
select bit 0 (7, 13, 14)
System clock select bit
(6, 10, 11, 12)
RW
RW
RW
RW
0 : I/O ports P8_6, P8_7
1 : XCIN-XCOUT oscillation function (9)
RW
0 : On
1 : Off (5)
RW
0 : CM16 and CM17 enabled
1 : Division-by-8 mode
RW
0 : Main clock, PLL clock, or 125 kHz onchip oscillator clock
1 : Sub clock
RW
NOTES :
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. The CM03 bit is set to 1 (high) while the CM04 bit is set to 0 (I/O port) or when entering stop mode.
3. This bit is provided to stop the main clock when the low power consumption mode or 125 kHz on-chip oscillator
low power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock
stops or not. To stop the main clock, set bits as follows:
(a) Set the CM07 bit to 1 (sub clock selected) with the sub-clock stably oscillates, or set the CM21 bit in
the CM2 register to 1 (125 kHz on-chip oscillator selected).
(b) Set the CM20 bit in the CM2 register to 0 (oscillation stop, re-oscillation detection function
disabled).
(c) Set the CM05 bit to 1 (stop).
4. During external clock input, set the CM05 bit to 0 (oscillate).
5. When the CM05 bit is set to 1, the XOUT pin is held “H”. Because the internal feedback resistor remains
connected, the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
6. After setting the CM04 bit to 1 (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably
before switching the CM07 bit from 0 to 1 (sub clock).
7. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
8. The fC32 and fOCO-S clock do not stop.
9. To use a sub-clock, set this bit to 1. Also make sure ports P8_6 and P8_7 are directed for input, with no pullups.
10. When the PM21 bit in the PM2 register is set to 1 (disable clock modification), this bit remains unchanged
even if writing to bits CM02, CM05, and CM07.
11. When setting the PM21 bit to 1, set the CM07 bit to 0 (main clock) before setting the PM21 bit to 1.
12. To use the main clock as the clock source for the CPU clock, set bits as follows.
(a) Set the CM05 bit to 0 (oscillate).
(b) Wait the main clock oscillation stabilizes.
(c) Set bits CM11, CM21, and CM07 to 0.
13. When the CM07 bit is set to 1 (sub clock) and the CM05 bit is set to 1 (main clock stops), the
CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capacity high).
14. To return from 125 kHz on-chip oscillator mode to high-speed or middle-speed mode, set bits CM06 and
CM15 to 1.
Figure 10.2
CM0 Register
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
System Clock Control Register 1 (1)
Symbol
CM1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Address
0007h
Bit Name
Bit Symbol
After Reset
00100000b
Function
(4, 6)
RW
0 : Clock on
1 : All clocks off (stop mode)
RW
0 : Main clock
1 : PLL clock (5)
RW
Set to 0
RW
CM10
All clock stop control bit
CM11
System clock select bit 1
—
(b3-b2)
Reserved bits
CM14
125 kHz on-chip oscillator stop 0 : 125 kHz on-chip oscillator on
bit (8, 9)
1 : 125 kHz on-chip oscillator off
RW
CM15
XIN-XOUT drive capacity
select bit (2)
0 : Low
1 : High
RW
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
RW
(6, 7)
CM16
Main clock division select bit 1
(3)
CM17
NOTES :
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. When entering stop mode or the CM05 bit is set to 1 (main clock stops) in low speed mode, the CM15 bit is set to
1 (drive capacity high).
3. This bit is valid when the CM06 bit is set to 0 (bits CM16 and CM17 enabled).
4. If the CM10 bit is set to 1 (stop mode), XOUT is held “H” and the internal feedback resistor is disconnected. Pins
XCIN and XCOUT are in high-impedance state. When the CM11 bit is set to 1 (PLL clock), or the CM20 bit in the
CM2 register is set to 1 (oscillation stop detection function enabled), do not set the CM10 bit to 1.
5. After setting the PLC07 bit in the PLC0 register to 1 (PLL operation), wait tsu (PLL) elapses before setting the
CM11 bit to 1 (PLL clock).
6. When the PM21 bit in the PM2 register is set to 1 (disable clock modification), this bit remains unchanged even if
writing to bits CM10 and CM11. When the CSPRO bit in the CSPR register is set to 1 (count source protection
mode), this bit remains unchanged even if writing to the CM10 bit.
7. The CM11 bit is valid when bits CM07 and CM21 are set to 0.
8. The CM14 bit can be set to 1 (125 kHz on-chip oscillator off) when the CM21 bit is set to 0 (main clock or PLL
clock). When the CM21 bit is set to 1 (125 kHz on-chip oscillator clock), the CM14 bit is set to 0 (125 kHz on-chip
oscillator on) and remains unchanged even if writing 1 to this bit.
9. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode), the CM14 bit is automatically
set to 0 (125 kHz on-chip oscillator on) and remains unchanged even if writing a 1 to this bit (125 kHz on-chip
oscillator does not stop).
Figure 10.3
CM1 Register
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
Oscillation Stop Detection Register (1)
Symbol
CM2
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Address
000Ch
Bit Name
Bit Symbol
CM20
CM21
After Reset
0X000010b (11)
Function
0: Oscillation stop and re-oscillation
Oscillation stop and
detection function disabled
re-oscillation detection enable
1: Oscillation stop and re-oscillation
bit (7, 9, 10,11)
detection function enabled
System clock select bit 2
(2, 3, 6, 8, 11, 12)
RW
RW
0: Main clock or PLL clock
1: 125 kHz on-chip oscillator clock
RW
CM22
Oscillation stop and
re-oscillation detection
flag (4)
0: Main clock stops and re-oscillation not
detected
1: Main clock stops and re-oscillation
detected
RW
CM23
XIN monitor flag (5)
0: Main clock oscillates
1: Main clock stops
RO
—
(b5-b4)
Reserved bits
Set to 0
RW
—
(b6)
CM27
No register bit. If necessary, set to 0. Read as undefined value
Operation select bit
0: Oscillation stop detection reset
(when an oscillation stops and 1: Oscillation stop, re-oscillation detection
re-oscillation is detected) (11)
interrupt
—
RW
NOTES :
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. When the CM20 bit is set to 1 (oscillation stop and re-oscillation detection function enabled), the CM27 bit is
set to 1 (oscillation stop and re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is set to 1 (125 kHz on-chip oscillator clock) if the main clock stop is detected.
3. If the CM20 bit is set to 1 and the CM23 bit is set to 1 (main clock stops), do not set the CM21 bit to 0.
4. This bit is set to 1 when the main clock stop is detected and the main clock re-oscillation is detected. When
this flag changes state from 0 to 1, an oscillation stop or a re-oscillation detection interrupt is generated. Use
this bit in an interrupt routine to determine the factors of interrupts between the oscillation stop, re-oscillation
etection interrupt and the watchdog timer interrupt. This bit is set to 0 by writing 0 in a program.
(This bit remains unchanged even if a 1 is written. Nor is it set to 0 when an oscillation stop or a re-oscillation
detection interrupt request is acknowledged.) When the CM22 bit is set to 1 and an oscillation stop or a reoscillation is detected, an oscillation stop or a re-oscillation detection interrupt is not generated.
5. Determine the main clock status by reading the CM23 bit several times in an oscillation stop or a re-oscillation
detection interrupt routine.
6. This bit is valid when the CM07 bit in the CM0 register is set to 0.
7. When the PM21 bit in the PM2 register is set to 1 (disable clock modification), this bit remains unchanged even
if writing to the CM20 bit.
8. When the CM20 bit is set to 1 (oscillation stop and re-oscillation detection function enabled), the CM27 bit is 1
(oscillation stop and re-oscillation detection interrupt), and the CM11 bit is set to 1 (PLL clock is selected as
the CPU clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the
CM22 bit is set to 0 under these conditions, an oscillation stop, a re-oscillation detection interrupt request is
generated at main clock stop detection. Set the CM21 bit to 1 (125 kHz on-chip oscillator clock) in the interrupt
routine.
9. Set the CM20 bit to 0 (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit back to
1 (enabled).
10. Set the CM20 bit in the CM2 register to 0 (disabled) before setting the CM05 bit in the CM0 register to 1 (main
clock stops).
11. Bits CM20, CM21, and CM27 remain unchanged at the oscillation stop detection reset.
12. When the CM21 bit is set to 0 (main clock or PLL clock) and the CM05 bit is set to 1 (main clock stops), the
CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capacity high).
Figure 10.4
CM2 Register
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
Peripheral Clock Select Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
PCLKR
Address
0012h
Bit Symbol
Bit Name
After Reset
00000011b
Function
RW
PCLK0
Timers A and B clock select bit
(clock source for Timers A , B,
and the dead time timer)
PCLK1
SI/O clock select bit
0 : f2SIO
(clock source for UART0 to
UART2, UART5 to UART7, SI/ 1 : f1SIO
O3, and SI/O4)
RW
—
(b7-b2)
Reserved bits
RW
0 : f2TIMAB
1 : f1TIMAB
RW
Set to 0. Read as undefined value
NOTE :
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
Processor Mode Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM2
Address
001Eh
Bit Name
Bit Symbol
PM20
PM21
After Reset
XX000X01b
Function
Specifying wait when
accessing SFR at PLL
operation (2)
System clock protection bit
(3, 4)
RW
0 : 2 waits
1 : 1 wait
RW
0 : Clock is protected by PRCR register
1 : Clock modification disabled
RW
—
(b2)
No register bit. If necessary, set to 0. Read as undefined value
—
(b3)
Reserved bit
Set to 0
RW
P8_5 / NMI function select bit (3)
0 : Port P8_5 function
1 : NMI function
RW
0 : provide enabled
1 : provide disabled
RW
PM24
PM25
—
(b7-b6)
D4INT clock provide enable bit
(5)
No register bits. If necessary, set to 0. Read as undefined value
—
—
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. The PM20 bit becomes effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20
bit when the PLC07 bit is set to 0 (PLL off).
3. Once this bit is set to 1, it cannot be cleared to 0 in a program.
4. If the PM21 bit is set to 1, writing to the following bits has no effect:
CM02 bit in CM0 register
CM05 bit in CM0 register (main clock does not stop)
CM07 bit in CM0 register (clock source for the CPU clock does not change)
CM10 bit in CM1 register (stop mode is not entered)
CM11 bit in CM1 register (clock source for the CPU clock does not change)
CM20 bit in CM2 register (oscillation stop and re-oscillation detection function settings do not change)
All bits in PLC0 register (PLL frequency synthesizer settings do not change)
Be aware that the WAIT instruction cannot be executed when the PM21 bit = 1.
5. When using low voltage detection interrupt, set the PM25 bit to 1 (provide enabled).
Figure 10.5
PCLKR Register and PM2 Register
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Page 79 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
PLL Control Register 0 (1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
PLC0
001Ch
Bit Name
Bit Symbol
PLL multiplying factor
select bit (3)
PLC02
—
(b3)
Reserved bit
Reference frequency counter
set bit (3)
PLC05
PLC07
RW
0 : Do not set
1 : Multiply by 2
0 : Multiply by 4
1 : Multiply by 6
0 : Multiply by 8
1:
0:
Do not set
1:
RW
Read as undefined value
RO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
b5 b4
PLC04
—
(b6)
Function
b2 b1 b0
PLC00
PLC01
After Reset
0X01X010b
0
0
1
1
0 : No division
1 : Divide-by-2
0 : Divide-by-4
1 : Do not set
No register bit. If necessary, set to 0. Read as undefined value
Operation enable bit (4)
0 : PLL off
1 : PLL on
RW
RW
RW
RW
—
RW
NOTES :
1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. When the PM21 bit in the PM2 register is 1 (clock modification disabled), writing to this register has no
effect.
3. Bits PLC00 to PLC02, PLC04, and PLC5 can only be modified when the PLC07 bit = 0 (PLL turned off). The
value once written to this bit cannot be modified.
4. Before setting the PLC07 bit to 1, set the CM05 bit to 0 (main clock oscillation).
Figure 10.6
PLC0 Register
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
The following describes the clocks generated by the clock generation circuit.
10.1.1
Main Clock
This clock is provided by the main clock oscillation circuit and used as the clock source for the CPU and
peripheral function clocks. The main clock oscillation circuit is configured by connecting a resonator
between pins XIN and XOUT. The main clock oscillation circuit contains a feedback resistor, which is disconnected from the oscillation circuit during stop mode in order to reduce the amount of power consumed
in the chip. The main clock oscillation circuit may also be configured by feeding an externally generated
clock to the XIN pin. Figure 10.7 shows the Examples of Main Clock Connection Circuit.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to 1 (main
clock oscillation circuit turned off) after switching the clock source for the CPU clock to a sub clock or 125
kHz on-chip oscillation clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback
resistor remains on, XIN is pulled “H” to XOUT via the feedback resistor.
During stop mode, all clocks including the main clock are turned off. Refer to 10.4 “Power Control” for
details.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
CIN
XIN
External clock
XIN
Oscillator
VCC1
VSS
XOUT
Rd
(1)
COUT
XOUT Open
VSS
NOTE :
1. Place a damping resistor if required. The resistance will vary depending on the
oscillator and the oscillation drive capacity setting. Use the value recommended by
each oscillator manufacturer.
When the oscillation drive capacity is set to low, check if oscillation is stable at low.
Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer
recommends placing the resistor externally.
Figure 10.7
Examples of Main Clock Connection Circuit
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Oct 12, 2007
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Specification in this preliminary version is subject to change.
M16C/64 Group
10.1.2
10. Clock Generation Circuit
Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillation circuit is configured by connecting a crystal resonator between pins XCIN and
XCOUT. The sub clock oscillation circuit contains a feedback resistor, which is disconnected from the
oscillation circuit during stop mode in order to reduce the amount of power consumed in the chip. The
sub clock oscillation circuit may also be configured by feeding an externally generated clock to the
XCIN pin.
Figure 10.8 shows the Examples of Sub Clock Connection Circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillation circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to 1 (sub clock) after the
sub clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 10.4 “Power Control” for
details.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
CCIN
XCIN
External clock
XCIN
Oscillator
VCC1
VSS
XCOUT
RCd (1)
CCOUT
XCOUT Open
VSS
NOTE :
1. Place a damping resistor if required. The resistance will vary depending on the
oscillator and the oscillation drive capacity setting. Use the value recommended by
each oscillator manufacturer.
When the oscillation drive capacity is set to low, check if oscillation is stable at low.
Also, place a feedback resistor between XCIN and XCOUT if the oscillator
manufacturer recommends placing the resistor externally.
Figure 10.8
Examples of Sub Clock Connection Circuit
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Oct 12, 2007
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Specification in this preliminary version is subject to change.
M16C/64 Group
10.1.3
10. Clock Generation Circuit
125 kHz On-Chip Oscillator Clock (fOCO-S)
This clock, approximately 125 kHz, is supplied by 125 kHz on-chip oscillator. This clock is used as the
clock source for the CPU and peripheral function clocks. In addition, if the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), this clock is used as the count source for the watchdog timer (Refer to 13.2 “Count Source Protection Mode Enabled”).
After reset, the 125 kHz on-chip oscillator divided by 8 provides the CPU clock. It stops when the CM14
bit in the CM1 register is set to 0 (125 kHz on-chip oscillator stops). If the main clock stops oscillating
when the CM20 bit in the CM2 register is 1 (oscillation stop, re-oscillation detection function enabled)
and the CM27 bit is 1 (oscillation stop, re-oscillation detection interrupt), the 125 kHz on-chip oscillator
automatically starts operating and supplying the necessary clock for the microcomputer.
10.1.4
PLL Clock
The PLL clock is generated by the PLL frequency synthesizer. This clock is used as the clock source for
the CPU and peripheral function clocks. After reset, the PLL frequency synthesizer is turned off. The
PLL frequency synthesizer is activated by setting the PLC07 bit to 1 (PLL operation). When the PLL
clock is used as the clock source for the CPU clock, wait for tsu (PLL) until the PLL clock to be stable,
and then set the CM11 bit in the CM1 register to 1.
Before entering wait mode or stop mode, be sure to set the CM11 bit to 0 (CPU clock source is the
main clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register
to 0 (PLL stops). Figure 10.10 shows the Procedure to Use PLL Clock as CPU Clock Source.
The PLL clock is the main clock divided by the selected values of bits PLC05 and PLC04 in the PLC0
register, and then multiplied by the selected values of bits PLC02 to PLC00. Set bits PLC05 and PLC04
to fit divided frequency between 2 MHz and 5 MHz. Figure 10.9 shows the Relation between the Main
Clock and the PLL Clock.
Divided by n
Main clock
n
m
(1)
Multiplied by m
(2)
PLL clock
: 1, 2, 4 (selected by bits PLC05 and PLC04 in the PLC0 register)
: 2, 4, 6, 8 (selected by bits PLC02 to PLC00 in the PLC0 register)
NOTES :
1. Set the frequency divided by n between 2 MHz and 5 MHz.
2. Set 10 MHz ≤ PLL clock frequency ≤ 25 MHz
Figure 10.9
Relation between the Main Clock and the PLL Clock
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
Bits PLC05 and PLC04 and bits PLC02 to PLC00 can be set only once after reset. Table 10.2 shows
the Example for Setting PLL Clock Frequencies.
Table 10.2
Example for Setting PLL Clock Frequencies
Main Clock
10 MHz
5 MHz
12 MHz
6 MHz
Setting Value
Bits PLC05 and PLC04
Bits PLC02 to PLC00
01b (divided by 2)
010b (multiplied by 4)
00b (not divided)
010b (multiplied by 4)
10b (divided by 4)
100b (multiplied by 8)
01b (divided by 2)
100b (multiplied by 8)
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PLL Clock
20 MHz
24 MHz
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
10. Clock Generation Circuit
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to 0 (main clock)
Set bits PLC05 and PLC04 (reference clock divided).
Set bits PLC02 to PLC00 (multiplying factor)
Set the PLC07 bit to 1 (PLL operation)
Wait until the PLL clock becomes stable (tsu(PLL))
Set the CM11 bit to 1 (PLL clock for the CPU clock source)
END
Figure 10.10 Procedure to Use PLL Clock as CPU Clock Source
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M16C/64 Group
10.2
10. Clock Generation Circuit
CPU Clock and Peripheral Function Clock
Two types of clock exists: CPU clock to operate the CPU
Peripheral function clocks to operate the peripheral functions.
10.2.1
CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The main clock, sub clock, 125 kHz on-chip oscillator clock, or the PLL clock can be selected as the
clock source for the CPU clock.
When the main clock, PLL clock, or 125 kHz on-chip oscillator clock is selected as the clock source for
the CPU clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the
CPU clock. Use the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register to
select a divide-by-n value.
After reset, the 125 kHz on-chip oscillator clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the
CPU clock can be output from the BCLK pin by setting the PM07 bit in the PM0 register to 0 (output
enabled).
Note that when entering stop mode or when the CM05 bit in the CM0 register is set to 1 (stop) in lowspeed mode, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode).
REJ09B0392-0064 Rev.0.64
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M16C/64 Group
10.2.2
10. Clock Generation Circuit
Peripheral Function Clock (f1, fC32)
These are operating clocks for the peripheral functions.
f1 is produced from the main clock, the PLL clock, or the 125 kHz on-chip oscillator clock, and is used
for timers A and B, UART0 to UART2, UART5 to UART7, SI/O3, SI/O4, and A/D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral
function clock f1 turned off during wait mode), or when the microcomputer is in low power consumption
mode, the f1 clock is turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used
when the sub clock is on.
fOCO-S is used for timers A and B. fOCO-S can be used when the CM14 bit in the CM1 register is set
to 0 (125 kHz on-chip oscillator oscillates).
Figure 10.11 shows the Peripheral Function Clock.
1/32
fC
fOCO-S
CM11 = 0
fC32
fOCO-S
UART0 to UART2
CM21 = 1
f1
Main clock
PLL clock
Timer A, Timer B
CM02
CM11 = 1
CM21 = 0
SI/O3, SI/O4
UART5 to UART7
A/D converter
Figure 10.11 Peripheral Function Clock
10.3
Clock Output Function
During single-chip mode, the f8, f32, or fC clock can be output from the CLKOUT pin. Use bits CM01 and
CM00 in the CM0 register to select.
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10.4
10. Clock Generation Circuit
Power Control
Normal operating mode, wait mode, and stop mode are provided as the power consumption control. All
mode states, except wait mode and stop mode, are called normal operating mode in this document.
10.4.1
Normal Operating Mode
Normal operating mode is further classified into seven modes.
In normal operating mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU
clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower
the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator
circuits are turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which
switched must be oscillating stably. If the new clock source is the main clock, sub clock, or PLL clock,
allow a sufficient wait time in a program until it becomes oscillating stably.
When the CPU clock source is changed from the 125 kHz on-chip oscillator to the main clock, change
the operating mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8
(the CM06 bit in the CM0 register was set to 1) in the 125 kHz on-chip oscillator mode.
10.4.1.1
High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
10.4.1.2
PLL Operating Mode
The PLL clock serves as the CPU clock. If the sub clock is on, fC32 can be used as the count source
for timers A and B. If fOCO-S is oscillating, fOCO-S can be used as the count source for timers A and
B. PLL operating mode can be entered from high-speed mode or medium-speed mode. If PLL operating mode is to be changed to wait or stop mode, first go to high-speed mode or medium-speed
mode before changing.
10.4.1.3
Medium-Speed Mode
The main clock divided by 2, 4, 8, or 16 provides the CPU clock. If the sub clock is on, fC32 can be
used as the count source for timers A and B. If fOCO-S is oscillating, fOCO-S can be used as the
count source for timers A and B.
10.4.1.4
Low-Speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit in the CM2 register is set to 0 (main clock or PLL clock), and the
125 kHz on-chip oscillator clock is used when the CM21 bit is set to 1 (125 kHz on-chip oscillator
clock).
The fC32 clock can be used as the count source for timers A and B.
10.4.1.5
Low Power Consumption Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the CPU clock. The fC32 clock can be used as the count source for timers A and B. If fOCO-S
is oscillating, fOCO-S can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes 1 (divided by
8 mode). In the low power consumption mode, do not change the CM06 bit. Consequently, the
medium-speed (divided by 8) mode is to be selected when the main clock is operated next.
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10.4.1.6
10. Clock Generation Circuit
125 kHz On-Chip Oscillator Mode
The 125 kHz on-chip oscillator clock divided by 1 (undivided), 2, 4, 8, or 16 provides the CPU clock.
The 125 kHz on-chip oscillator clock is also the clock source for the peripheral function clocks. If the
sub clock is on, fC32 can be used as the count source for timers A and B. When the operating mode
is returned to the high- and medium-speed modes, set the CM06 bit in the CM0 register to 1 (divided
by 8 mode).
10.4.1.7
125 kHz On-Chip Oscillator Low Power Consumption Mode
The main clock is turned off after being placed in 125 kHz on-chip oscillator mode. The CPU clock
can be selected as in the 125 kHz on-chip oscillator mode. The 125 kHz on-chip oscillator clock is the
clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count
source for timers A and B.
Table 10.3
Setting Clock Related Bit and Modes
CM2
RegisMode
ter
CM21
PLL
divided by 1 0
Operating
divided by 2 0
Mode
divided by 4 0
divided by 8 0
divided by 16 0
High-Speed Mode
0
Mediumdivided by 2 0
Speed Mode divided by 4 0
divided by 8 0
divided by 16 0
Low-Speed Mode
Low Power Consumption
0
Mode
125 kHz
divided by 1 1
On-chip
divided by 2 1
Oscillator
divided by 4 1
Mode
divided by 8 1
divided by 16 1
125 kHz On-Chip Oscillator 1
Low Power Consumption
Mode
- indicates that either 0 or 1 is set.
CM1 Register
CM0 Register
CM11
1
1
1
1
1
0
0
0
0
0
0
0
CM14
-
CM17, CM16
00b
01b
10b
11b
00b
01b
10b
11b
-
CM07
0
0
0
0
0
0
0
0
0
0
1
1
CM06
0
0
0
1
0
0
0
0
1
0
-
CM05
0
0
0
0
0
0
0
0
0
0
0
1 (1)
1 (1)
CM04
1
1
0
0
0
0
0
0
0
0
0
0
0
0
00b
01b
10b
11b
(2)
0
0
0
0
0
0
0
0
0
1
0
(2)
0
0
0
0
0
1
-
NOTES:
1. When the CM05 bit is set to 1 (main clock turned off) in low-speed mode, the mode goes to low
power consumption mode and the CM06 bit is set to 1 (divided by 8 mode) simultaneously.
2. The divide-by-n value can be selected the same way as in 125 kHz on-chip oscillator mode.
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10.4.2
10. Clock Generation Circuit
Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because they are
operated by the CPU clock. However, if the CSPRO bit in the CSPR register is 1 (count source protection enabled), the watchdog timer remains active. Because the main clock, sub clock, and 125 kHz onchip oscillator clock all are on, the peripheral functions using these clocks keep operating.
10.4.2.1
Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is 1 (peripheral function clock f1 turned off during wait mode), the
f1 clock is turned off while in wait mode, with the power consumption reduced that much. However,
fC32 and fOCO-S (clock source of Timers A and B) remain on for the CM02 bit.
10.4.2.2
Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to clear the CM11 bit in the CM1
register to 0 (CPU clock source is the main clock) before going to wait mode. The power consumption
of the chip can be reduced by clearing the PLC07 bit in the PLC0 register to 0 (PLL stops).
10.4.2.3
Pin Status during Wait Mode
Table 10.4 lists Pin Status during Wait Mode.
Table 10.4
Pin Status during Wait Mode
Memory Expansion Mode
Microprocessor Mode
Pin
Single-Chip Mode
A0 to A19, D0 to D15,
CS0 to CS3, BHE
Retains status just prior to enter- Cannot be used as a bus control pin
ing wait mode
RD, WR, WRL, WRH
“H”
HLDA, BCLK
“H”
ALE
“L”
I/O ports
Retains status just prior to enter- Retains status before wait mode
ing wait mode
CLKOUT
When fC
selected
Cannot be used as a CLKOUT
pin
When f8, f32
selected
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Does not stop
Does not stop when the CM02 bit is 0.
When the CM02 bit is 1, the status
immediately prior to entering wait
mode is maintained
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M16C/64 Group
10.4.2.4
10. Clock Generation Circuit
Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt.
If the microcomputer is to exit wait mode by a hardware reset, NMI interrupt, or low voltage detection
interrupt, set the peripheral function interrupt bits ILVL2 to ILVL0 to 000b (interrupts disabled) before
executing the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is 0 (peripheral function clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait
mode. If the CM02 bit is 1 (peripheral function clocks turned off during wait mode), the peripheral
functions using the peripheral function clocks stop operating, so that only the peripheral functions
activated by external signals can be used to exit wait mode.
Table 10.5
Resets and Interrupts to Exit Wait Mode and Use Conditions
Reset, Interrupt
NMI Interrupt
CM02 = 0
Usable
CM02 = 1
Usable
Serial Interface Interrupt Usable when operating with internal or
external clock
Usable when operating with external clock
Key Input Interrupt
Usable
Usable
A/D Conversion
Interrupt
Usable in one-shot mode or single sweep Do not use
mode
Timer A Interrupt
Timer B Interrupt
Usable in all modes
Usable in event counter mode or
when the count source is fC32
INT Interrupt
Usable
Usable
Low Voltage Detection
Interrupt
Usable
Usable
Hardware Reset 1
Usable
Brown-out Reset
Usable (See 6.1 Brown-out Reset)
Watchdog Timer Reset
Usable when count source protection mode is enabled (CSPRO = 1)
Table 10.5 lists the Resets and Interrupts to Exit Wait Mode and Use Conditions.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the WAIT instruction.
(1) Set bits ILVL2 to ILVL0 in the interrupt control register, for peripheral function interrupts used to
exit wait mode.
Bits ILVL2 to ILVL0 in all other interrupt control registers, for peripheral function interrupts not
used to exit wait mode, are set to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Start operating the peripheral functions used to exit wait mode.
When the peripheral function interrupt is used, an interrupt routine is performed after an interrupt
request is generated and then the CPU clock is supplied again.
When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the
same clock as the CPU clock executing the WAIT instruction.
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10.4.3
10. Clock Generation Circuit
Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function
clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to pins VCC1 and VCC2 is VRAM or
greater, the internal RAM is retained. When applying 2.7 or less voltage to pins VCC1 and VCC2, make
sure VCC1 = VCC2 ≥ VRAM.
However, the peripheral functions activated by external signals keep operating. The following resets
and interrupts can be used to exit stop mode. Table 10.6 lists Resets and Interrupts to Stop Mode and
Use Conditions
Table 10.6
Resets and Interrupts to Stop Mode and Use Conditions
Reset, Interrupt
Condition
NMI Interrupt
Usable
Key Input Interrupt
Usable
INT Interrupt
Usable
Timer A Interrupt
Timer B Interrupt
Usable when counting external pulses in event counter
mode
Serial Interface Interrupt
Usable when external clock is selected
Low Voltage Detection Interrupt
Usable (See 6.2 Low Voltage Detection Interrupt)
Hardware Reset 1
Usable
Brown-out Reset
Usable when digital filter is disabled (VW0C = 1)
10.4.3.1
Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to 1 (all
clocks turned off). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode)
and the CM15 bit in the CM1 register is set to 1 (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit in the CM2 register to 0 (oscillation stop, re-oscillation
detection function disabled).
Also, if the CM11 bit in the CM1 register is 1 (PLL clock for the CPU clock source), set the CM11 bit to
0 (main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to 0 (PLL turned off)
before entering stop mode.
10.4.3.2
Pin Status in Stop Mode
Table 10.7 lists Pin Status in Stop Mode.
Table 10.7
Pin Status in Stop Mode
Memory Expansion Mode
Microprocessor Mode
Pin
Single-Chip Mode
A0 to A19, D0 to D15,
CS0 to CS3, BHE
Retains status just prior to stop mode Cannot be used as a bus control pin
RD, WR, WRL, WRH
“H”
HLDA, BCLK
“H”
ALE
indeterminate
I/O ports
Retains status just prior to stop mode Retains status just prior to stop mode
CLKOUT
Cannot be used as a CLKOUT pin
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“H”
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10.4.3.3
10. Clock Generation Circuit
Exiting Stop Mode
Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt, or peripheral
function interrupt.
When the hardware reset, NMI interrupt, or low voltage detection interrupt is used to exit stop mode,
set bits ILVL2 to ILVL0 in the interrupt control registers for the peripheral function interrupt to 000b
(interrupt disabled) before setting the CM10 bit to 1.
When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to 1 after the following settings are completed.
(1) Set bits ILVL2 to ILVL0 in the interrupt control registers to decide the peripheral priority level of
the peripheral function interrupt.
Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to 0 by setting
bits ILVL2 to ILVL0 to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Start operation of peripheral function being used to exit stop mode.
When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed
after an interrupt request is generated and then the CPU clock is supplied again.
When stop mode is exited by the peripheral function interrupt, low voltage detection interrupt, or NMI
interrupt, the CPU clock source is as follows, in accordance with the CPU clock source setting before
the microcomputer had entered stop mode.
• When the sub clock is the CPU clock before entering stop mode: sub clock
• When the main clock is the CPU clock source before entering stop mode: main clock divided by 8
• When the 125 kHz on-chip oscillator clock is the CPU clock source before entering stop mode: 125
kHz on-chip oscillator clock divided by 8
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10. Clock Generation Circuit
Figure 10.12 shows the power Control Transition
Power Control Mode State Transition
Reset
Normal Operation
Mode
125 kHz on-chip oscillator mode
CM07 = 0, CM21 = 1
CM14 = 0, CM05 = 0
125 kHz on-chip oscillator
low power consumption mode
CM14 = 0
CM21 = 1
CM04 = 1
CM07 = 1
CM05 = 1, CM07 = 0
CM14 = 0, CM21 = 1
CM07 = 0
CM14 = 0
CM21 = 1
CM21 = 0
PLL operation mode
CM05 = 0
CM07 = 0
CM11 = 1
CM21 = 0
PLC07 = 1
PLC07 = 0
CM11 = 0
CM11 = 1
PLC07 = 1
High-speed mode,
medium-speed mode
CM05 = 0
CM07 = 0
CM11 = 0
CM21 = 0
Interrupt
CM04 = 1, CM05 = 0, CM07 = 1
Low power
consumption mode
CM07 = 0
CM21 = 0
WAIT instruction
CM04 = 1, CM05 = 1
CM07 = 1
Interrupt
CM10 = 1
Wait mode
Stop mode
CPU operation stopped
All the oscillations stopped
CM04, CM05, CM06, CM07: bits in the CM0 register
CM11, CM14, CM16, CM17: bits in the CM1 register
CM21: bits in the CM2 register
Figure 10.12 Power Control Transition
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Low-speed mode
CM04 = 1
CM07 = 1
Oct 12, 2007
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10.5
10. Clock Generation Circuit
System Clock Protection Function
The system clock protection function prohibits the CPU clock from changing clock sources when the main
clock is selected as the CPU clock source. This is to prevent the CPU clock from stopping by an unexpected program operation.
When the PM21 bit in the PM2 register is set to 1 (clock change disabled), the following bits cannot be
written to:
• Bits CM02, CM05, and CM07 in the CM0 register
• Bits CM10 and CM11 in the CM1 register
• The CM20 bit in the CM2 register
• All bits in the PLC0 register
When using the system clock protection function, set the CM05 bit in the CM0 register to 0 (main clock
oscillation) and CM07 bit to 0 (main clock as CPU clock source) and follow the procedure below.
(1) Set the PRC1 bit in the PRCR register to 1 (write to the PM2 register enabled).
(2) Set the PM21 bit in the PM2 register to 1 (clock change disabled).
(3) Set the PRC1 bit in the PRCR register to 0 (write to the PM2 register disabled).
When the PM21 bit is set to 1, do not execute the WAIT instruction.
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10.6
10. Clock Generation Circuit
Oscillation Stop and Re-Oscillation Detect Function
The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and reoscillation are detected. At oscillation stop or re-oscillation detection, reset oscillation stop or re-oscillation
detection interrupt are generated. Which is to be generated can be selected using the CM27 bit in the
CM2 register. The oscillation stop and re-oscillation detect function can be enabled and disabled by the
CM20 bit in the CM2 register. Table 10.8 lists a Specification Overview of Oscillation Stop and Re-Oscillation Detect Function.
Table 10.8
Specification Overview of Oscillation Stop and Re-Oscillation Detect Function
Item
Oscillation Stop Detectable Clock and
Frequency Bandwidth
Enabling Condition for Oscillation Stop,
Re-Oscillation Detect Function
Operation at Oscillation Stop,
Re-Oscillation Detection
10.6.1
Specification
f(XIN) ≥ 2 MHz
Set CM20 bit to 1 (enabled)
Reset occurs (when CM27 bit = 0)
Oscillation stop, re-oscillation detection interrupt generated
(when CM27 bit = 1)
Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)
When main clock stop is detected when the CM20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset. Refer to 4. “Special Function Registers (SFRs)”, 5. “Reset”).
This status is reset with hardware reset 1 or brown-out reset. Also, even when re-oscillation is detected,
the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage (During main clock stop, do not set the CM20 bit to 1 and the CM27 bit to 0).
10.6.2
Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect
Interrupt)
When the main clock corresponds to the CPU clock source and the CM20 bit is 1 (oscillation stop and
re-oscillation detect function enabled), the system is placed in the following state if the main clock
comes to a halt.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM14 bit = 0 (125 kHz on-chip oscillator clock oscillates)
• CM21 bit = 1 (125 kHz on-chip oscillator clock for CPU clock source and clock source of peripheral
function.)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
When the PLL clock corresponds to the CPU clock source and the CM20 bit is 1, the system is placed
in the following state if the main clock comes to a halt. Since the CM21 bit remains unchanged, set it to
1 (125 kHz on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM14 bit = 0 (125 kHz on-chip oscillator clock oscillates)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
When the CM20 bit is 1, the system is placed in the following state if the main clock re-oscillates from
the stop condition.
• Oscillation stop and re-oscillation detect interrupt request occurs.
• CM14 bit = 0 (125 kHz on-chip oscillator clock oscillates)
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
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10.6.3
10. Clock Generation Circuit
How to Use Oscillation Stop and Re-Oscillation Detect Function
• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer
interrupt and low voltage detection interrupt. If the oscillation stop, re-oscillation detection and
watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine
which interrupt source is requesting the interrupt.
• When the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and
peripheral functions must be switched to the main clock in a program. Figure 10.13 shows the Procedure to Switch Clock Source from 125 kHz On-chip Oscillator to Main Clock.
• Simultaneously with oscillation stop and re-oscillation detection interrupt occurrence, the CM22 bit
becomes 1. When the CM22 bit is set to 1, oscillation stop and re-oscillation detection interrupt are
disabled. By setting the CM22 bit to 0 in a program, oscillation stop and re-oscillation detection
interrupt are enabled.
• If the main clock stops during low speed mode where the CM20 bit is 1, an oscillation stop and reoscillation detection interrupt request is generated. At the same time, the 125 kHz on-chip oscillator starts oscillating. In this case, although the CPU clock is derived from the sub clock as it was
before the interrupt occurred, the peripheral function clocks now are derived from the 125 kHz onchip oscillator clock.
• To enter wait mode while using the oscillation stop and re-oscillation detection function, set the
CM02 bit to 0 (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop and re-oscillation detection function is provided in preparation for main
clock stop due to external factors, set the CM20 bit to 0 (oscillation stop and re-oscillation detection
function disabled) where the main clock is stopped or oscillated in a program, that is where the
stop mode is selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the
CM20 bit to 0.
Switch the main clock
NO
Determine several times whether
the CM23 bit is set to 0
(main clock oscillates)
YES
Set the CM06 bit to 1
(divide-by-8)
Set the CM22 bit to 0
(main clock stop, re-oscillation not detected)
Set the CM21 bit to 0
(main clock or PLL clock)
End
Bits CM21 to CM23: bits in the CM2 register
Figure 10.13 Procedure to Switch Clock Source From 125 kHz On-chip Oscillator to Main Clock
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11. Protection
11. Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 11.1 shows the PRCR Register. The following lists the registers protected by
the PRCR register.
• The PRC0 bit protects registers CM0, CM1, CM2, PLC0, and PCLKR.
• The PRC1 bit protects registers PM0, PM1, PM2, TB2SC, INVC0, and INVC1.
• The PRC2 bit protects registers PD9, S3C, and S4C.
• The PRC3 bit protects registers VCR2, D4INT, and VW0C.
• The PRC6 bit protects the PRG2C register.
Set the PRC2 bit to 1 (write enabled) and then write to given SFR address, and the PRC2 bit will be cleared
to 0 (write protected). The registers protected by the PRC2 bit should be changed in the next instruction
after setting the PRC2 bit to 1. Make sure no interrupts or DMA transfers will occur between the instruction
in which the PRC2 bit is set to 1 and the next instruction. Bits PRC0, PRC1, PRC3, and PRC6 are not automatically cleared to 0 by writing to given SFR address. They can only be cleared in a program.
Protect Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0
PRCR
000Ah
0 0
Bit Name
Bit Symbol
After Reset
00h
Function
Enable write to registers CM0, CM1,
CM2, PLC0 and PCLKR
0 : Write protected
1 : Write enabled
Enable write to registers PM0, PM1, PM2,
TB2SC, INVC0, and INVC1
0 : Write protected
1 : Write enabled
Enable write to registers PD9, S3C, and
S4C
0 : Write protected
1 : Write enabled
Enable write to registers VCR2, D4INT,
and VW0C
0 : Write protected
1 : Write enabled
PRC0
Protect bit 0
PRC1
Protect bit 1
PRC2
Protect bit 2
PRC3
Protect bit 3
—
(b5-b4)
Reserved bits
Set to 0
RW
PRC6
Protect bit 6
Enable write to the PRG2C register
0 : Write protected
1 : Write enabled
RW
—
(b7)
Reserved bit
Set to 0
RW
NOTE :
1. The PRC2 bit is set to 0 by writing to given SFR address after setting it to 1. Other bits are not set to 0
automatically by the same token. Therefore, set them to 0 in a program.
Figure 11.1
PRCR Register
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RW
Oct 12, 2007
RW
RW
RW
RW
Under development
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M16C/64 Group
12. Interrupt
12. Interrupt
12.1
Type of Interrupts
Figure 12.1 shows Type of Interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Software
(non-maskable interrupt)
Interrupt
Special
(non-maskable interrupt)
Hardware
Peripheral function (1)
(maskable interrupt)
NMI
DBC (2)
Watchdog timer
Oscillation stop
and re-oscillation detection
Low voltage detection
Single step (2)
Address match
NOTES :
1. The peripheral functions in the microcomputer are used to generate the peripheral
interrupt.
2. Do not normally use this interrupt because it is provided exclusively for use by
development tools.
Figure 12.1
Type of Interrupts
• Maskable Interrupt
• Non-Maskable Interrupt
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: The interrupt priority can be changed by enabling (disabling) an interrupt with the interrupt enable flag (I flag) or by using interrupt priority
levels.
: The interrupt priority cannot be changed by enabling (disabling) an
interrupt with the interrupt enable flag (I flag) or by using interrupt priority levels.
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.2
12. Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
12.2.1
Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
12.2.2
Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set
to 1 (the operation resulted in an overflow). The followings are instructions whose O flag changes by
arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
12.2.3
BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
12.2.4
INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63
can be specified for the INT instruction. Because software interrupt Nos. 2 to 31 and 41 to 51 are
assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is
cleared to 0 (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not
change state during instruction execution, and the SP selected at the time is used.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.3
12. Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types: special interrupts and peripheral function interrupts.
12.3.1
Special Interrupts
Special interrupts are non-maskable interrupts.
12.3.1.1
NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details
about the NMI interrupt, refer to 12.7 “NMI Interrupt”.
12.3.1.2
DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
12.3.1.3
Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize
the watchdog timer. For details about the watchdog timer, refer to 13. “Watchdog Timer”.
12.3.1.4
Oscillation Stop and Re-Oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop and re-oscillation detection function, refer to 10. “Clock Generation Circuit”.
12.3.1.5
Low Voltage Detection Interrupt
Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to 6.
“Voltage Detection Circuit”.
12.3.1.6
Single-Step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development tools.
12.3.1.7
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by registers RMAD0 to RMAD3 that correspond to one of the AIER0 or AIER1 bit in the
AIER register or the AIER20 or AIER21 bit in the AIER2 register which is 1 (address match interrupt
enabled). For details about the address match interrupt, refer to 12.9 “Address Match Interrupt”.
12.3.2
Peripheral Function Interrupts
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupt is a maskable interrupt. See Tables 12.2 and
12.3 Relocatable Vector Tables. Refer to the descriptions of each function for details about how the
peripheral function interrupt occurs.
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.4
12. Interrupt
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows the Interrupt Vector.
MSB
LSB
Vector address (L)
Low-order address
Middle-order address
Vector address (H)
Figure 12.2
12.4.1
0000
High-order
address
0000
0000
Interrupt Vector
Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 12.1 lists the
Fixed Vector Table. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to 22.2 “Functions to Prevent Flash
Memory from Rewriting”.
Table 12.1
Fixed Vector Table
Interrupt Source
Vector Table Addresses
Address (L) to Address (H)
Reference
Undefined Instruction
(UND instruction)
FFFDCh to FFFDFh
M16C/60, M16C/20 series software
manual
Overflow (INTO instruction)
FFFE0h to FFFE3h
BRK Instruction (2)
FFFE4h to FFFE7h
Address Match
FFFE8h to FFFEBh
12.9 “Address Match Interrupt”
Single Step (1)
FFFECh to FFFEFh
-
Watchdog Timer,
FFFF0h to FFFF3h
Oscillation Stop and Re-Oscillation Detection,
Low Voltage Detection
13. “Watchdog Timer”
10. “Clock Generation Circuit”
6. “Voltage Detection Circuit”
DBC (1)
FFFF4h to FFFF7h
-
NMI
FFFF8h to FFFFBh
12.7 “NMI Interrupt”
Reset
FFFFCh to FFFFFh
5. “Reset”
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.4.2
12. Interrupt
Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector
table area. Tables 12.3 and 12.3 list the Relocatable Vector Tables. Setting an even address in the
INTB register results in the interrupt sequence being executed faster than setting an odd address.
Table 12.2
Relocatable Vector Table (1)
Software
Interrupt
Number
Vector Address (1)
Address (L) to Address (H)
Interrupt Source
Reference
+0 to +3 (0000h to 0003h)
0
1
M16C/60, M16C/20 series
software manual
INT7
+8 to +11 (0008h to 000Bh)
2
12.6 “INT Interrupt”
INT6
+12 to +15 (000Ch to 000Fh)
3
INT3
+16 to +19 (0010h to 0013h)
4
Timer B5
+20 to +23 (0014h to 0017h)
5
15. “Timers”
Timer B4, UART1 Bus Collision Detect +24 to +27 (0018h to 001Bh)
6
15. “Timers”
17. “Serial Interface”
BRK Instruction (5)
− (Reserved)
(4, 6)
Timer B3, UART0 Bus Collision Detect +28 to +31 (001Ch to 001Fh)
7
(4, 6)
SI/O4, INT5 (2)
+32 to +35 (0020h to 0023h)
8
+36 to +39 (0024h to 0027h)
9
12.6 “INT Interrupt”
17. “Serial Interface”
+40 to +43 (0028h to 002Bh)
10
17. “Serial Interface”
DMA0
+44 to +47 (002Ch to 002Fh)
11
14. “DMAC”
DMA1
+48 to +51 (0030h to 0033h)
12
Key Input Interrupt
+52 to +55 (0034h to 0037h)
13
12.8 “Key Input Interrupt”
A/D
+56 to +59 (0038h to 003Bh)
14
18. “A/D Converter”
UART2 Transmit, NACK2 (3)
+60 to +63 (003Ch to 003Fh)
15
17. “Serial Interface”
UART2 Receive, ACK2 (3)
+64 to +67 (0040h to 0043h)
16
SI/O3, INT4
(2)
UART2 Bus Collision Detection
(6)
+68 to +71 (0044h to 0047h)
17
+72 to +75 (0048h to 004Bh)
18
UART1 Transmit, NACK1 (3)
+76 to +79 (004Ch to 004Fh)
19
UART1 Receive, ACK1 (3)
+80 to +83 (0050h to 0053h)
20
UART0 Transmit, NACK0
UART0 Receive, ACK0
(3)
(3)
Timer A0
+84 to +87 (0054h to 0057h)
21
Timer A1
+88 to +91 (0058h to 005Bh)
22
Timer A2
+92 to +95 (005Ch to 005Fh)
23
Timer A3
+96 to +99 (0060h to 0063h)
24
Timer A4
+100 to +103 (0064h to 0067h)
25
Timer B0
+104 to +107 (0068h to 006Bh)
26
Timer B1
+108 to +111 (006Ch to 006Fh)
27
Timer B2
+112 to +115 (0070h to 0073h)
28
15. “Timers”
NOTES:
1. Address relative to address in INTB.
2. Use bits IFSR6 and IFSR7 in the IFSR register to select.
3. During I2C mode, interrupts NACK and ACK comprise the interrupt source.
4. Use bits IFSR26 and IFSR27 in the IFSR2A register to select.
5. These interrupts cannot be disabled using the I flag.
6. Bus collision detection: During IE mode, this bus collision detection constitutes the interrupt source.
During I2C mode, however, a start condition or a stop condition detection constitutes the interrupt
source.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 12.3
12. Interrupt
Relocatable Vector Table (2)
Vector Address (1)
Address (L) to Address (H)
Interrupt Source
Software
Interrupt
Number
INT0
+116 to +119 (0074h to 0077h)
29
INT1
+120 to +123 (0078h to 007Bh)
30
INT2
+124 to +127 (007Ch to 007Fh)
31
INT Instruction Interrupt (3)
+128 to +131 (0080h to 0083h)
to
+160 to +163 (00A0h to 00A3h)
32 to 40
DMA2
+164 to +167 (00A4h to 00A7h)
41
DMA3
+168 to +171(00A8h to 00ABh)
42
UART5 Bus Collision Detection(4)
+172 to +175(00ACh to 0AFh)
UART5 Transmit, NACK5(2)
+176 to +179(00B0h to 00B3h)
44
UART5 Receive, ACK5 (2)
+180 to +183(00B4h to 00B7h)
45
UART6 Bus Collision Detection (4)
+184 to +187(00B8h to 00BBh)
UART6 Transmit, NACK6 (2)
+188 to +191(00BCh to 00BFh)
47
UART6 Receive, ACK6 (2)
+192 to +195(00C0h to 00C3h)
48
UART7 Bus Collision Detection (4)
+196 to +199(00C4h to 00C7h)
UART7 Transmit, NACK7 (2)
+200 to +203(00C8h to 00CBh)
50
UART7 Receive, ACK7 (2)
+204 to +207(00CCh to 00CFh)
51
- (Reserved)
43
Reference
12.6 “INT Interrupt”
M16C/60, M16C/20
series software manual
14. “DMAC”
17. “Serial Interface”
46
49
52 to 63
NOTES:
1. Address relative to address in INTB.
2. During I2C mode, interrupts NACK and ACK comprise the interrupt source.
3. These interrupts cannot be disabled using the I flag.
4. Bus collision detection: During IE mode, this bus collision detection constitutes the factor of an interrupt.
5. Bus collision detection: During IE mode, this bus collision detection constitutes the interrupt source.
During I2C mode, however, a start condition or a stop condition detection constitutes the interrupt
source.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.5
12. Interrupt
Interrupt Control
The following describes how to enable / disable the maskable interrupts, and how to set the priority in
which order they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to
enable / disable the maskable interrupts. Whether an interrupt is requested or not is indicated by the IR
bit in each interrupt control register.
Figures 12.3 and 12.4 show the Interrupt Control Registers.
Interrupt Control Register 1 (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB5IC
TB4IC / U1BCNIC (3)
TB3IC / U0BCNIC (3)
BCNIC
DM0IC to DM3IC
KUPIC (4)
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
U5BCNIC to U7BCNIC
S5TIC to S7TIC
S5RIC to S7RIC
Address
After Reset
0045h
0046h
0047h
004Ah
004Bh, 004Ch, 0069h, 006Ah
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
006Bh, 006Eh, 0071h
006Ch, 006Fh, 0072h
006Dh, 0070h, 0073h
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Bit Name
Bit Symbol
ILVL0
ILVL1
Interrupt priority level select
bit
ILVL2
IR
—
(b7-b4)
Interrupt request bit
Function
b2
b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Level 0 (interrupt disabled)
1 : Level 1
0 : Level 2
1 : Level 3
0 : Level 4
1 : Level 5
0 : Level 6
1 : Level 7
0: Interrupt not requested
1: Interrupt requested
No register bits. If necessary, set to 0. Read as undefined value
RW
RW
RW
RW
RW (1)
—
NOTES :
1. The IR bit can only be reset by writing a 0. (Do not write a 1).
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register.
3. Use the IFSR2A register to select.
4. To use the key input interrupts, set the PCR7 bit in the PCR register to 0 (key input enabled).
Figure 12.3
Interrupt Control Register (1)
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
12. Interrupt
Interrupt Control Register 2 (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
0
INT7IC (6,7)
INT6IC (6,7)
INT3IC (4)
S4IC/INT5IC (4)
S3IC/INT4IC (4)
INT0IC to INT2IC
Address
After Reset
0042h
0043h
0044h
0048h
0049h
005Dh to 005Fh
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
Bit Name
Bit Symbol
ILVL0
ILVL1
Interrupt priority level select
bit
ILVL2
Function
b2
b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Level 0 (interrupt disabled)
1 : Level 1
0 : Level 2
1 : Level 3
0 : Level 4
1 : Level 5
0 : Level 6
1 : Level 7
RW
RW
RW
RW
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
POL
Polarity select bit (3, 5)
0 : Select falling edge
1 : Select rising edge
RW
—
(b5)
Reserved bit
Set to 0
RW
IR
—
(b7-b6)
No register bits. If necessary, set to 0. Read as undefined value
RW (1)
—
NOTES :
1. The IR bit can only be reset by writing a 0. (Do not write a 1).
2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register.
3. If the IFSRi bit in the IFSR register are 1 (both edges), set the POL bit in the INTiIC register to 0
(falling edge) (i = 0 to 5). Similarly, if bits IFSR30 and IFSR31 in the IFSR3A register are 1 (both edges), set
the POL bits in registers INT6IC and INT7IC to 0 (falling edge).
4. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set bits
ILVL2 to ILVL0 in registers INT5IC to INT3IC to 000b (interrupts disabled).
5. Set the POL bit in the S3IC or S4IC register to 0 (falling edge) when the IFSR6 bit in the IFSR register = 0 (SI/
O3 selected) or IFSR7 bit = 0 (SI/O4 selected), respectively.
6. When the processor mode is memory expansion or microprocessor mode, set bits ILVL2 to ILVL0 in registers
INT6IC and INT7IC to 000b (interrupts disabled).
7. To use the INT6 interrupts, set the PCR5 bit in the PCR register to 0 (INT6 input enabled).
To use the INT7 interrupts, set the PCR6 bit in the PCR register to 0 (INT7 input enabled).
Figure 12.4
Interrupt Control Register (2)
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.5.1
12. Interrupt
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the
maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.5.2
IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted, the IR bit is cleared to 0 (interrupt not requested).
The IR bit can be cleared to 0 in a program. Do not write a 1 to this bit.
12.5.3
Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.4 shows the Settings of Interrupt Priority Levels and Table 12.5 shows the Interrupt Priority
Levels Enabled by IPL.
The followings are conditions under which an interrupt is accepted:
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0 and IPL are independent each other. In no case do they affect one
another.
Table 12.4
Bits ILVL2 to
ILVL0
000b
001b
010b
011b
100b
101b
110b
111b
Settings of Interrupt Priority Levels
Interrupt Priority Level
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
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Priority
Order
Low
High
Oct 12, 2007
Table 12.5
IPL
000b
001b
010b
011b
100b
101b
110b
111b
Interrupt Priority Levels Enabled by IPL
Enabled Interrupt Priority Levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.5.4
12. Interrupt
Interrupt Sequence
An interrupt sequence − what are performed over a period from the instant an interrupt request is
accepted to the instant the interrupt routine is executed − is described here.
If an interrupt request occurs during execution of an instruction, the processor determines its priority
when the execution of the instruction is completed, and transfers control to the interrupt sequence from
the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA
instruction, the processor temporarily suspends the instruction being executed, and transfers control to
the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 12.5 shows Time Required
for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 00000h. Then, the IR bit applicable to the interrupt information is set to 0 (interrupt not
requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register (1) within the
CPU.
(3) Flags I, D, and U in the FLG register become as follows:
• The I flag is set to 0 (interrupt disabled)
• The D flag is set to 0 (single-step interrupt disabled)
• The U flag is set to 0 (ISP selected)
Note that the U flag does not change states if an INT instruction for software interrupt Nos. 32 to 63
is executed.
(4) The temporary register (1) within the CPU is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt in IPL is set.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
NOTE:
1. Temporary register cannot be modified by users.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address 00000h
Address bus
Interrupt
information
Data bus
RD
Indeterminate (1)
Indeterminate (1)
SP-2
SP-4
SP-2
contents
SP-4
contents
Indeterminate (1)
WR (2)
NOTES :
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 12.5
Time Required for Executing Interrupt Sequence
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Oct 12, 2007
vec
vec
contents
vec+2
vec+2
contents
PC
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.5.5
12. Interrupt
Interrupt Response Time
Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till
when the executing instruction is completed ((a) on Figure 12.6) and a time during which the interrupt
sequence is executed ((b) on Figure 12.6).
Interrupt request
generated
Interrupt request
acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in
interrupt routine
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction at the time executing is
completed. The length of this time varies with the instruction being executed. The DIVX instruction
requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a
register).
(b) A time during which the interrupt sequence is executed. For details, see the table below. Note,
however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle
for the address match and single-step interrupts.
Interrupt Vector Address SP Value
Figure 12.6
12.5.6
16-Bit Bus, Without Wait
8-Bit Bus, Without Wait
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Interrupt Response Time
Variation of IPL when Interrupt Request IS Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 12.6 is set in the IPL. Table 12.6 lists the IPL Level That is Set to IPL When a Software
or Special Interrupt is Accepted.
Table 12.6
IPL Level That is Set to IPL When a Software or Special Interrupt is Accepted
Interrupt Sources
Watchdog Timer, NMI, Oscillation Stop and Re-Oscillation Detection, Low
Voltage Detection
Software, Address Match, DBC, Single-Step
REJ09B0392-0064 Rev.0.64
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Level Set to IPL
7
Not changed
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.5.7
12. Interrupt
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 12.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
Stack
Address
MSB
LSB
Stack
LSB
m-4
m-4
PCL
m-3
m-3
PCM
m-2
m-2
FLGL
m-1
m-1
m
Content of previous stack
m+1
Content of previous stack
[SP]
SP value before
interrupt request is accepted.
FLGH
PCH
m
Content of previous stack
m+1
Content of previous stack
Stack status
before interrupt request is acknowledged
Figure 12.7
[SP]
New SP value
PCL
PCM
PCH
FLGL
FLGH
: 8 low-order bits of PC
: 8 middle-order bits of PC
: 4 high-order bits of PC
: 8 low-order bits of FLG
: 4 high-order bits of FLG
Stack status
after interrupt request is acknowledged
Stack Status Before and After Acceptance of Interrupt Request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
(1), at the time of acceptance of an interrupt request, is even or odd. If the SP (1) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure
12.8 shows the Operation of Saving Register.
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
(2) SP contains odd number
Stack
[SP] - 5 (Odd)
[SP] - 4 (Odd)
PCL
[SP] - 3 (Odd)
PCM
[SP] - 2 (Even)
FLGL
[SP]
FLGH
(2) Saved simultaneously,
all 16 bits
[SP] - 3 (Even)
[SP] - 2 (Odd)
PCH
(Even)
(1) Saved simultaneously,
all 16 bits
[SP] - 1 (Even)
Completed saving registers
in two operations.
[SP]
Sequence in which order
registers are saved
Operation of Saving Register
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FLGH
PCL
(3)
PCM
(4)
FLGL
(1)
PCH
Saved, 8 bits at a time
(2)
(Odd)
NOTE :
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 12.8
Stack
[SP] - 5 (Even)
[SP] - 4 (Even)
[SP] - 1 (Odd)
Address
Sequence in which order
registers are saved
Completed saving registers
in four operations.
PCL
PCM
PCH
FLGL
FLGH
: 8 low-order bits of PC
: 8 middle-order bits of PC
: 4 high-order bits of PC
: 8 low-order bits of FLG
: 4 high-order bits of FLG
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.5.8
12. Interrupt
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
Register bank is switched back to the bank used prior to the interrupt sequence by the REIT instruction.
12.5.9
Interrupt Priority
If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether
an interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using
bits ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their
interrupt priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 12.9
shows the Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
Reset
High
NMI
DBC
Watchdog Timer
Oscillation Stop
and Re-Oscillation Detection,
Low Voltage Detection
Peripheral Function
Single Step
Address Match
Figure 12.9
Low
Hardware Interrupt Priority
12.5.10 Interrupt Priority Level Select Circuit
The interrupt priority level select circuit selects the highest priority interrupt in a sampled interrupt
request(s) at the same sampling point.
Figure 12.10 shows the Interrupts Priority Select Circuit.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12. Interrupt
Higher
Priority level of each interrupt
Level 0
(initial value)
Priority level of each interrupt
UART7 transmit, NACK7
UART0 receive, ACK0
UART6 receive, ACK6
UART2 receive, ACK2
UART6 bus collision detection
A/D conversion
UART5 transmit, NACK5
DMA1
DMA3
UART2 bus collision
UART7 receive, ACK7
SI/O4, INT5
UART7 bus collision detection
Timer A0
UART6 transmit, NACK6
UART1 transmit, NACK1
UART5 receive, ACK5
UART0 transmit, NACK0
UART5 bus collision detection
UART2 transmit, NACK2
DMA2
Key input interrupt
INT1
DMA0
Timer B2
Priority of peripheral
function interrupts
(if priority levels are same)
SI/O3, INT4
Timer B0
INT6
Timer A3
INT7
Timer A1
Timer B4, UART1 bus collision
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3, UART0 bus collision
Timer B5
UART1 receive, ACK1
Lower
IPL
Interrupt request level determinate
output to clock generating circuit
(Figure 10.1 Clock Generation Circuit)
I flag
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Low voltage detection
DBC
NMI
Figure 12.10 Interrupts Priority Select Circuit
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Interrupt request
accepted
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.6
12. Interrupt
INT Interrupt
INTi interrupt (i = 0 to 7) is triggered by the edges of external inputs. The edge polarity is selected using
the IFSRi bit in the IFSR register, or the IFSR30 or IFSR31 bit in the IFSR3A register.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to 1 (INT4). To use the INT5 interrupt, set
the IFSR7 bit in the IFSR register to 1 (INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to 0 (interrupt not requested) before
enabling the interrupt.
To use the INT6 interrupt, set the PCR5 bit in the PCR register to 0 (INT6 input enabled). To use the INT7
interrupt, set the PCR6 bit in the PCR register to 0 (INT7 input enabled).
Figure 12.11 shows the IFSR Register, and Figure 12.12 shows Registers IFSR2A, IFSR3A, and PCR.
Interrupt Source Select Register
Symbol
IFSR
b7 b6 b5 b4 b3 b2 b1 b0
Address
0207h
Bit Name
Bit Symbol
After Reset
00h
Function
RW
IFSR0
INT0 interrupt polarity switch 0 : One edge
bit
1 : Both edges (1)
RW
IFSR1
INT1 interrupt polarity switch 0 : One edge
bit
1 : Both edges (1)
RW
IFSR2
INT2 interrupt polarity switch 0 : One edge
bit
1 : Both edges (1)
RW
IFSR3
INT3 interrupt polarity switch 0 : One edge
bit
1 : Both edges (1)
RW
IFSR4
INT4 interrupt polarity switch 0 : One edge
bit
1 : Both edges (1)
RW
IFSR5
INT5 interrupt polarity switch 0 : One edge
bit
1 : Both edges (1)
RW
IFSR6
Interrupt request source
select bit (2)
0 : SI/O3 (3)
1 : INT4
RW
IFSR7
Interrupt request source
select bit (2)
0 : SI/O4 (3)
1 : INT5
RW
NOTES :
1. When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC are set to 0
(falling edge).
2. During memory expansion and microprocessor modes, when the data bus is 16 bits wide (BYTE pin is “L”), set
this bit to 0 (SI/O3, SI/O4).
3. When setting this bit to 0 (SI/O3, SI/O4), make sure the POL bit in registers S3IC and S4IC are set to 0
(falling edge).
Figure 12.11 IFSR Register
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12. Interrupt
Interrupt Source Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
IFSR2A
After Reset
00h
Address
0206h
Bit Name
Bit Symbol
Function
RW
—
(b5-b0)
Reserved bits
IFSR26
Interrupt request source select 0 : Timer B3
bit (1)
1 : UART0 bus collision detection
RW
IFSR27
Interrupt request source select 0 : Timer B4
bit (2)
1 : UART1 bus collision detection
RW
Set to 0
RW
NOTES :
1. Timer B3 and UART0 bus collision detection share the vector and interrupt control register. When using Timer
B3 interrupt, clear the IFSR26 bit to 0 (Timer B3). When using UART0 bus collision detection, set the IFSR26
bit to 1.
2. Timer B4 and UART1 bus collision detection share the vector and interrupt control register. When using
Timer B4 interrupt, clear the IFSR27 bit to 0 (Timer B4). When using UART1 bus collision detection, set the
IFSR27 bit to 1.
Interrupt Source Select Register 3
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
IFSR3A
Address
0205h
After Reset
00h
Bit Name
Bit Symbol
Function
RW
IFSR30
INT6 interrupt polarity switch
bit
0 : One edge
1 : Both edges (1)
RW
IFSR31
INT7 interrupt polarity switch
bit
0 : One edge
1 : Both edges (1)
RW
—
(b7-b2)
Reserved bits
Set to 0
RW
NOTE :
1. When setting this bit to 1 (both edges), make sure the POL bit in registers INT6IC and INT7IC are set to 0 (falling
edge).
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCR
Address
0366h
Bit Name
Bit Symbol
After Reset
00000XX0b
Function
RW
Operation performed when the P1 register is
read
0 : When the port is set for input, the input
levels of pins P1_0 to P1_7 are read.
When set for output, the port latch is read.
1 : The port latch is read regardless of
whether the port is set for input or output.
RW
PCR0
Port P1 control bit
—
(b4-b1)
No register bits. If necessary, set to 0. Read as 0
PCR5
INT6 input enable bit (1)
0 : Enabled
1 : Disabled
RW
(2)
0 : Enabled
1 : Disabled
RW
0 : Enabled
1 : Disabled
RW
PCR6
INT7 input enable bit
PCR7
Key input enable bit (3)
NOTES :
1. To use the AN2_4 pin as an analog input pin, set the PCR5 bit to 1 (INT6 input disabled).
2. To use the AN2_5 pin as an analog input pin, set the PCR6 bit to 1 (INT7 input disabled).
3. To use pins AN4 to AN7 as analog input pins, set the PCR7 bit to 1 (key input disabled).
Figure 12.12 Registers IFSR2A, IFSR3A, and PCR
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—
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.7
12. Interrupt
NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. To use the NMI interrupt, set the PM24 bit in the PM2 register to 1
(NMI function).
12.8
Key Input Interrupt
Of P10_4 to P10_7, a key input interrupt is generated when input on any of pins P10_4 to P10_7 which
has had bits PD10_4 to PD10_7 in the PD10 register set to 0 (input) goes low. Key input interrupts can be
used as a key-on wake up function, the function which gets the microcomputer out of wait or stop mode.
However, if using the key input interrupt, do not use P10_4 to P10_7 as analog input pins. Figure 12.13
shows the block diagram of the Key Input Interrupt. Note, however, that while input on any pin which has
had bits PD10_4 to PD10_7 set to 0 (input mode) is pulled low, inputs on all other pins of the port are not
detected as interrupts. Set the PCR7 bit in the PCR register to 0 (key input enabled) to use key input interrupts.
PU25 bit in
PUR2 register
Pull-up
transistor
PD10_7 bit in
PD10 register
KUPIC register
PD10_7 bit in PD10 register
KI3
Pull-up
transistor
PD10_6 bit in
PD10 register
Interrupt control circuit
KI2
Pull-up
transistor
PD10_5 bit in
PD10 register
KI1
Pull-up
transistor
PD10_4 bit in
PD10 register
KI0
Figure 12.13 Key Input Interrupt
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Key input
interrupt request
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12.9
12. Interrupt
Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register.
Use bits AIER0 and AIER1 in the AIER register and bits AIER20 and AIER21 in the AIER2 register to
enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
When address match interrupt requests are acknowledged, the value of the PC that is saved to the stack
area (refer to 12.5.7 “Saving Registers”) varies depending on the instruction at the address indicated by
the RMADi register (The value of the PC that is saved to the stack area is not the correct return address.)
Therefore, follow one of the methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 12.7 shows the Value of the PC That Is Saved to the Stack Area When an Address Match Interrupt
Request is Accepted. Note that when using the external bus in 8 bits width, no address match interrupts
can be used for external areas.
Figure 12.14 shows Registers AIER, AIER2, and RMAD0 to RMAD3.
Table 12.7
Value of the PC That Is Saved to the Stack Area When an Address Match Interrupt
Request is Accepted
Instruction at the Address Indicated by the RMADi Register
16-bit op-code instruction
Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8, dest SUB.B:S #IMM8, dest AND.B:S #IMM8, dest
OR.B:S
#IMM8, dest MOV.B:S #IMM8, dest STZ.B:S #IMM8, dest
STNZ.B:S #IMM8, dest STZX.B:S #IMM81, #IMM82,dest
CMP.B:S
#IMM8, dest PUSHM src POPM dest
JMPS
#IMM8 JSRS #IMM8
MOV.B:S
#IMM, dest (However, dest = A0 or A1)
Instructions other than the above
Value of the PC that is
saved to the stack area
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
NOTE:
Value of the PC that is saved to the stack area: Refer to 12.5.7 “Saving Registers”.
Table 12.8
Relationship between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Sources
Address Match Interrupt 0
Address Match Interrupt 1
Address Match Interrupt 2
Address Match Interrupt 3
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Address Match Interrupt Enable Bit
AIER0
AIER1
AIER20
AIER21
Oct 12, 2007
Address Match Interrupt Register
RMAD0
RMAD1
RMAD2
RMAD3
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
12. Interrupt
Address Match Interrupt Enable Register
Symbol
AIER
b7 b6 b5 b4 b3 b2 b1 b0
After Reset
XXXXXX00b
Address
020Eh
Bit Name
Bit Symbol
Function
RW
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
—
(b7-b2)
No register bits. If necessary, set to 0. Read as undefined value
—
Address Match Interrupt Enable Register 2
Symbol
AIER2
b7 b6 b5 b4 b3 b2 b1 b0
After Reset
XXXXXX00b
Address
020Fh
Bit Name
Bit Symbol
Function
RW
AIER20
Address match interrupt 2
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
AIER21
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
—
(b7-b2)
No register bits. If necessary, set to 0. Read as undefined value
—
Address Match Interrupt Register i (i = 0 to 3)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
Address
RMAD0
RMAD1
RMAD2
RMAD3
0212h to 0210h
0216h to 0214h
021Ah to 0218h
021Eh to 021Ch
Function
Address setting register for address match interrupt
(b19 to b0)
No register bits. If necessary, set to 0. Read as undefined value
Figure 12.14 Registers AIER, AIER2, and RMAD0 to RMAD3
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After Reset
X00000h
X00000h
X00000h
X00000h
Setting Range
RW
00000h to FFFFFh
RW
—
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
13. Watchdog Timer
13. Watchdog Timer
The watchdog timer detects whether the program is out of control. Therefore, we recommend using the
watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter, and count
source protection mode (enabled / disabled) is set here.
Table 13.1 shows the Watchdog Timer Specification.
Refer to 5.4 “Watchdog Timer Reset” for details of watchdog timer reset.
Figure 13.1 shows the Watchdog Timer Block Diagram. Figure 13.2 shows the Registers WDTR, WDTS,
and WDC. Figure 13.3 shows the CSPR Register and OFS1 Address.
Table 13.1
Watchdog Timer Specification
Item
Count Source
Count Operation
Count Start Condition
Count Stop Condition
Watchdog Timer
Reset Condition
Operation When the
Timer Underflows
Select Function
When count source protection mode
When count source protection mode is
is disabled
enabled
CPU clock
125kHz on-chip oscillator clock
Decrement
Either of the followings can be selected.
Count automatically starts after reset.
Count starts by writing to the WDTS register.
Stop mode, wait mode, hold state
None
Reset
Write 00h, and then FFh to the WDTR register.
Underflow
Watchdog timer interrupt or watchdog
Watchdog timer reset
timer reset
Prescaler divide ratio
Set the WDC7 bit in the WDC register to select this mode.
Count source protection mode
Set the CSPROINI bit (flash memory) in the OFS1 address to select whether this
mode is enabled or disabled after reset. If this mode is set to disabled after reset,
set the CSPRO bit (program) in the CSPR register.
Start up or stop watchdog timer after reset
Set the WDTON bit in the OFS1 address to select startup or stop.
Prescaler
1/16
1/128
CPU
clock
1/2
HOLD
CM07 = 0,
WDC7 = 0
CSPRO = 0
CM07 = 0,
WDC7 = 0
PM12 = 0
Watchdog timer
interrupt request
Watchdog timer
CM07 = 1
PM12 = 1
Watchdog timer
reset
foco-s
CSPRO = 1
Set to 7FFFh (1)
Write to WDTR register
Internal reset signal
(“L” active)
CSPRO
WDC7
PM12
CM07
: bit in CSPR register
: bit in WDC register
: bit in PM1 register
: bit in CM0 register
NOTE :
1. 0FFFh is set when the CSPRO bit is set to 1 (count source protection mode enabled).
Figure 13.1
Watchdog Timer Block Diagram
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
13. Watchdog Timer
Watchdog Timer Reset Register
b7
Symbol
WDTR
b0
After Reset
Indeterminate
Address
037Dh
Function
RW
Setting 00h and then FFh initializes the watchdog timer. (1, 3)
The watchdog timer is initialized to 7FFFh when count source protection mode is disabled,
and to 0FFFh when count source protection mode is enabled. (2)
WO
NOTES :
1. Make sure no interrupts or DMA transfers will occur before writing FFh after writing 00h.
2. The watchdog timer is set to 0FFFh when the CSPRO bit in the CSPR register is set to 1 (count source
protection mode enabled).
3. After the watchdog timer interrupt occurs, reset the watchdog timer by setting the WDTR register.
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
037Eh
After Reset
Indeterminate
Function
RW
The watchdog timer starts counting after a write instruction to this register
WO
Watchdog Timer Control Register
Symbol
WDC
b7 b6 b5 b4 b3 b2 b1 b0
0
Address
037Fh
Bit Name
Bit Symbol
—
(b4-b0)
RW
RO
—
(b5)
No register bit. If necessary, set to 0. Read as 0
—
—
(b6)
Reserved bit
Set to 0
RW
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
RW
Registers WDTR, WDTS, and WDC
REJ09B0392-0064 Rev.0.64
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Function
Higher-order bits of watchdog timer
WDC7
Figure 13.2
After Reset
00XXXXXXb
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
13. Watchdog Timer
Count Source Protection Mode Register
Symbol
CSPR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
After Reset (1)
00h
Address
037Ch
Bit Name
Bit Symbol
Function
RW
—
(b6-b0)
Reserved bits
Set to 0
RW
CSPRO
Count source protection mode
select bit (2)
0 : Count source protection mode
disabled
1 : Count source protection mode enabled
RW
NOTES :
1. When a 0 is written to the CSPROINI bit in the OFS1 address, 10000000b is set after reset.
2. Write a 0 and then a 1 to set the CSPRO bit to 1. 0 cannot be set in a program.
Optional Feature Select Address (1)
Symbol
OFS1
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1
1 1
Address
FFFFFh
Bit Name
Bit Symbol
WDTON
—
(b2-b1)
Function
RW
(3)
0 : Watchdog timer starts automatically
after reset
1 : Watchdog timer is in a stopped state
after reset
RW
Reserved bits
Set to 1
RW
0 : ROM code protection enabled
1 : ROM code protection disabled
RW
Set to 1
RW
0 : Count source protection mode
enabled after reset
1 : Count source protection mode
disabled after reset
RW
Watchdog timer start select bit
ROMCP1 ROM code protection bit
—
(b6-b4)
After Reset
FFh (2)
Reserved bits
After-reset count source
CSPROINI
protection mode select bit (3)
NOTES :
1. The OFS1 address exists in flash memory. Set the values when writing a program.
2. The OFS1 address is set to FFh when a block including the OFS1 address is erased.
3. Set the WDTON bit to 0 (watchdog timer starts automatically after reset) when setting the CSPROINI bit to 0
(count source protection mode enabled after reset).
Figure 13.3
CSPR Register and OFS1 Address
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
13.1
13. Watchdog Timer
Count Source Protection Mode Disabled
The CPU clock is used for the watchdog timer count source when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (When Count Source Protection Mode is Disabled).
Table 13.2
Watchdog Timer Specifications (When Count Source Protection Mode is Disabled)
Item
Count Source
Count Operation
Period
Watchdog Timer
Reset Condition
Count Start Condition
Count Stop Condition
Operation when the
Timer Underflows
Specification
CPU Clock
Decrement
Prescaler divide ratio (n) x watchdog timer count value (32768) (1)
CPU clock
n: 16 or 128 (selected by the WDC7 bit in the WDC register)
example: When CPU clock frequency = 16 MHz and prescaler divided by 16,
period = approximately 32.8ms
• Reset
• Write 00h, and then FFh to the WDTR register.
• Underflow
Set the WDTON bit (2) in the OFS1 address (FFFFFh) to select the watchdog timer
operation after reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset)
The watchdog timer and prescaler stop after reset and count starts by writing to
the WDTS register.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset)
The watchdog timer and prescaler start counting automatically after reset.
Stop mode, wait mode, hold state (count resumes from the hold value after exiting.)
• When the PM 12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM 12 bit in the PM1 register is set to 1
Watchdog timer reset (see 5.4 “Watchdog Timer Reset”)
NOTES:
1. Write 00h, and then FFh to the WDTR register to initialize the watchdog timer. The prescaler is initialized after reset. Some errors in the period of the watchdog timer may be caused by the prescaler.
2. The WDTON bit cannot be changed by a program. Write a 0 to bit 0 of address FFFFFh with a flash
programmer to set the WDTON bit.
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
13.2
13. Watchdog Timer
Count Source Protection Mode Enabled
The 125 kHz on-chip oscillator clock is used for the watchdog timer count source when count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be
supplied to the watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (When Count Source Protection Mode is Enabled).
Table 13.3
Watchdog Timer Specifications (When Count Source Protection Mode is Enabled)
Item
Count Source
Count Operation
Period
Watchdog Timer
Reset Condition
Count Start Condition
Count Stop Condition
Operation when the
Timer Underflows
Registers, Bits
Specification
125 kHz on-chip oscillator clock
Decrement
Watchdog timer count value (4096)
125 kHz on-chip oscillator clock
example: When 125 kHz on-chip oscillator clock = 125 kHz, period = approximately
32.8ms
• Reset
• Write 00h, and then FFh to the WDTR register.
• Underflow
Set the WDTON bit (1) in the OFS1 address (FFFFFh) to select the watchdog timer
operation after reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset)
The watchdog timer and prescaler stop after reset and count starts by writing to
the WDTS register.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset)
The watchdog timer and prescaler start counting automatically after reset.
None (Count does not stop in wait mode or in hold state once count starts. The
MCU does not enter stop mode.)
Watchdog timer reset (see 5.4 “Watchdog Timer Reset” )
• When the CSPRO bit in the CSPR register is set to 1 (count source protection
mode enabled) (2), the followings are set automatically.
-Set 0FFFh to the watchdog timer.
-Set the CM14 bit in the CM1 register to 0 (125 kHz on-chip oscillator on).
-Set the PM12 bit in the PM1 register to 1 (The watchdog timer reset is generated
when watchdog timer underflows.).
• The following conditions apply in count source protection mode.
-Writing to the CM10 bit in the CM1 register is disabled (It remains unchanged
even if it is set to 1. The MCU does not enter stop mode.).
-Writing to the CM14 bit in the CM1 register is disabled (It remains unchanged
even if it is set to 1. The 125 kHz on-chip oscillator does not stop.).
NOTES:
1. The WDTON bit cannot be changed by a program. Write 0 to bit 0 of address FFFFFh with a flash
programmer to set the WDTON bit.
2. Even if 0 is written to the CSPROINI bit in the OFS1 address, the CSPRO is set to 1. The CSPROINI
bit cannot be changed by a program. Write 0 to bit 7 of address FFFFFh with a flash programmer to
set the CSPROINI bit.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
14. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Four DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by
the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a
cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after
a DMA request is generated. Figure 14.1 shows the DMAC Block Diagram. Table 14.1 lists the DMAC
Specifications. Figures 14.2 to 14.5 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0 (20)
(addresses 0182h to 0180h)
DMA0 destination pointer DAR0 (20)
(addresses 0186h to 0184h)
DMA0 forward address pointer (20) (1)
DMA1 source pointer SAR1 (20)
(addresses 0192h to 0190h)
DMA1 destination pointer DAR1 (20)
(addresses 0196h to 094h)
DMA0 transfer counter reload register TCR0 (16)
DMA1 forward address pointer (20) (1)
(addresses 0189h, 0188h)
DMA0 transfer counter TCR0 (16)
DMA2 source pointer SAR2 (20)
DMA1 transfer counter reload register TCR1 (16)
DMA2 destination pointer DAR2 (20)
(addresses 01A2h to 01A0h)
(addresses 01A6h to 01A4h)
(addresses 0199h, 0198h)
DMA1 transfer counter TCR1 (16)
DMA2 forward address pointer (20) (1)
DMA2 transfer counter reload register TCR2 (16)
DMA3 source pointer SAR3 (20)
(addresses 01B2h to 01B0h)
(addresses 01A9h, 01A8h)
DMA2 transfer counter TCR2 (16)
DMA3 destination pointer DAR3 (20)
DMA3 transfer counter reload register TCR3 (16)
DMA3 forward address pointer (20) (1)
(addresses 01B6h to 01B4h)
(addresses 01B9h, 01B8h)
DMA3 transfer counter TCR3 (16)
DMA latch high-order bits
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
NOTE :
1. Pointer is incremented by a DMA request.
Figure 14.1
DMAC Block Diagram
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0 to 3), as well as by an
interrupt request which is generated by any function specified by bits DMS and DSEL4 to DSEL0 in the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I
flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt
request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not
affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register = 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
not match. Refer to 14.4 “DMA Request” for details.
Table 14.1
DMAC Specifications (3)
Item
No. of Channels
Transfer Memory Space
Maximum No. of Bytes
Transferred
Specification
4 (cycle steal method)
• From given address in the 1-Mbyte space to a fixed address
• From a fixed address to given address in the 1-Mbyte space
• From a fixed address to a fixed address
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
DMA Request Factors (1, 2) Falling edge of INT0 to INT7
Both edges of INT0 to INT7
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 to 2, UART5 to 7 transmission interrupt requests
UART0 to 2, UART5 to 7 reception / ACK interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Software triggers
Channel Priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 takes precedence)
Transfer Unit
8 bits or 16 bits
Transfer Address Direction Forward or fixed (The source and destination addresses cannot both be in
the forward direction.)
Transfer
Single
Transfer is completed when the DMAi transfer counter underflows.
Mode
Transfer
Repeat
When the DMAi transfer counter underflows, it is reloaded with the value of
Transfer
the DMAi transfer counter reload register and a DMA transfer is continued
with it.
DMA Interrupt Request
When the DMAi transfer counter underflowed
Generation Timing
DMA Transfer Start
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register = 1 (enabled).
DMA Trans- Single
• When the DMAE bit is set to 0 (disabled)
fer Stop
Transfer
• After the DMAi transfer counter underflows
Repeat
When the DMAE bit is set to 0 (disabled)
Transfer
Reload Timing for Forward When a data transfer is started after setting the DMAE bit to 1 (enabled), the
Address Pointer and DMAi forward address pointer is reloaded with the value of the SARi or DARi
Transfer Counter
pointer whichever is specified to be in the forward direction and the DMAi
transfer counter is reloaded with the value of the DMAi transfer counter
reload register.
DMA Transfer Cycles
Minimum 3 cycles between SFR and internal RAM
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable factors of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0180h to 01BFh) are accessed by the DMAC.
i = 0 to 3
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
DMAi Source Select Register (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Address
0398h
039Ah
0390h
0392h
Symbol
DM0SL
DM1SL
DM2SL
DM3SL
Bit Symbol
Bit Name
After Reset
00h
00h
00h
00h
Function
DSEL0
RW
DSEL1
DSEL2
RW
DMA request source select
bit
RW
(NOTE 1)
RW
DSEL3
RW
DSEL4
—
(b5)
No register bit. If necessary, set to 0. Read as 0
DMS
DMA request source
expansion select bit
0: Basic request source
1: Extended request source
RW
Software DMA request bit
A DMA request is generated by setting this
bit to 1 when the DMS bit is 0 (basic
source) and bits DSEL4 to DSEL0 are
00001b (software trigger).
Read as 0
RW
DSR
—
NOTE :
1. The sources of DMAi requests can be selected by a combination of the DMS bit and bits DSEL4 to DSEL0 in
the manner described in Figure 14.3.
Figure 14.2
Registers DM0SL, DM1SL, DM2SL, and DM3SL (1)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
DMA0
DMA2
DSEL4 to DSEL0 DMS = 0 (Basic Factor of Request)
00000b
Falling edge of INT0 pin
Software trigger
00001b
Timer A0
00010b
Timer A1
00011b
Timer A2
00100b
Timer A3
00101b
Timer A4
00110b
Timer B0
00111b
Timer B1
01000b
Timer B2
01001b
UART0 transmission
01010b
UART0 reception
01011b
UART2 transmission
01100b
UART2 reception
01101b
A/D conversion
01110b
UART1 transmission
01111b
UART1 reception
10000b
UART5 transmission
10001b
UART5 reception
10010b
UART6 transmission
10011b
UART6 reception
10100b
UART7 transmission
10101b
UART7 reception
10110b
10111b
11XXXb
X indicates 0 or 1. - indicates no setting.
DMS = 1 (Extended Factor of Request)
Both edges of INT0 pin
Timer B3
Timer B4
Timer B5
Falling edge of INT4 pin
Both edges of INT4 pin
-
DMA1
DSEL4 to DSEL0
DMS = 0 (Basic Factor of Request) DMS = 1 (Extended Factor of Request)
Falling edge of INT1 pin
00000b
Software trigger
00001b
Timer A0
00010b
Timer A1
00011b
Timer A2
00100b
Timer A3
00101b
Timer A4
00110b
Timer B0
00111b
Timer B1
01000b
Timer
B2
01001b
UART0 transmission
01010b
UART0 reception / ACK0
01011b
UART2 transmission
01100b
UART2 reception / ACK2
01101b
A/D conversion
01110b
UART1 reception / ACK1
01111b
UART1 transmission
10000b
UART5 transmission
10001b
UART5 reception / ACK5
10010b
UART6 transmission
10011b
UART6 reception / ACK6
10100b
UART7 transmission
10101b
UART7 reception / ACK7
10110b
10111b
11XXXb
X indicates 0 or 1. - indicates no setting.
Figure 14.3
SI / O3
SI / O4
Both edges of INT1 pin
Falling edge of INT5 pin
Both edges of INT5 pin
-
DSEL4 to DSEL0 DMS = 0 (Basic Factor of Request)
00000b
Falling edge of INT2 pin
Software trigger
00001b
00010b
Timer A0
00011b
Timer A1
00100b
Timer A2
00101b
Timer A3
00110b
Timer A4
Timer B0
00111b
01000b
Timer B1
01001b
Timer B2
01010b
UART0 transmission
01011b
UART0 reception
01100b
UART2 transmission
01101b
UART2 reception
01110b
A/D conversion
01111b
UART1 transmission
10000b
UART1 reception
UART5 transmission
10001b
UART5 reception
10010b
UART6 transmission
10011b
UART6 reception
10100b
UART7 transmission
10101b
UART7 reception
10110b
10111b
11XXXb
X indicates 0 or 1. - indicates no setting.
Oct 12, 2007
Both edges of INT2 pin
Timer B3
Timer B4
Timer B5
Falling edge of INT6 pin
Both edges of INT6 pin
-
DMA3
DSEL4 to DSEL0 DMS = 0 (Basic Factor of Request) DMS = 1 (Extended Factor of Request)
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
Falling edge of INT3 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmission
UART0 reception / ACK0
UART2 transmission
UART2 reception / ACK2
A/D conversion
UART1 reception / ACK1
UART1 transmission
UART5 transmission
UART5 reception / ACK5
UART6 transmission
UART6 reception / ACK6
UART7 transmission
UART7 reception / ACK7
-
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11XXXb
X indicates 0 or 1. - indicates no setting.
Registers DM0SL, DM1SL, DM2SL, and DM3SL (2)
REJ09B0392-0064 Rev.0.64
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DMS = 1 (Extended Factor of Request)
-
SI / O3
SI / O4
Both edges of INT3 pin
Falling edge of INT7 pin
Both edges of INT7 pin
-
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
DMAi Control Register (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
DM0CON
DM1CON
DM2CON
DM3CON
018Ch
019Ch
01ACh
01BCh
00000X00b
00000X00b
00000X00b
00000X00b
Bit Symbol
Bit Name
Function
0 : 16 bits
1 : 8 bits
RW
DMBIT
Transfer unit bit select bit
DMASL
Repeat transfer mode select 0 : Single transfer
bit
1 : Repeat transfer
DMAS
DMA request bit
0 : DMA not requested
1 : DMA requested
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
RW
DSD
Source address direction select 0 : Fixed
bit (2)
1 : Forward
RW
DAD
Destination address direction
select bit (2)
RW
—
(b7-b6)
0 : Fixed
1 : Forward
No register bits. If necessary, set to 0. Read as 0
RW
RW
RW (1)
—
NOTES :
1. The DMAS bit can be set to 0 by writing a 0 in a program (This bit remains unchanged even if 1 is written).
2. Set at least either the DAD bit or DSD bit to 0 (address direction fixed).
Figure 14.4
Registers DM0CON, DM1CON, DM2CON, and DM3CON
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
DMAi Source Pointer (i = 0 to 3) (1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
SAR2
SAR3
Address
0182h to 0180h
0192h to 0190h
01A2h to 01A0h
01B2h to 01B0h
Function
Set the source address of transfer
After Reset
0XXXXXh
0XXXXXh
0XXXXXh
0XXXXXh
Setting Range
RW
00000h to FFFFFh
RW
No register bits. If necessary, set to 0. Read as 0
—
NOTE :
1. If the DSD bit in the DMiCON register is 0 (fixed), write to this register when the DMAE bit in the
DMiCON register is 0 (DMA disabled).
If the DSD bit is 1 (forward direction), this register can be written to at any time.
If the DSD bit is 1 and the DMAE bit is 1 (DMA enabled), the DMAi forward address pointer can be read from this
register. Otherwise, the value written to it can be read.
DMAi Destination Pointer (i = 0 to 3) (1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
Address
0186h to 0184h
0196h to 0194h
01A6h to 01A4h
01B6h to 01B4h
DAR0
DAR1
DAR2
DAR3
Function
Set the destination address of transfer
After Reset
0XXXXXh
0XXXXXh
0XXXXXh
0XXXXXh
Setting Range
RW
00000h to FFFFFh
RW
No register bits. If necessary, set to 0. Read as 0
—
NOTE :
1. If the DAD bit in the DMiCON register is 0 (fixed), write to this register when the DMAE bit in the
DMiCON register is 0 (DMA disabled).
If the DAD bit is 1 (forward direction), this register can be written to at any time.
If the DAD bit is 1 and the DMAE bit is 1 (DMA enabled), the DMAi forward address pointer can be read from this
register. Otherwise, the value written to it can be read.
DMAi Transfer Counter (i = 0 to 3)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
TCR2
TCR3
Figure 14.5
Address
0189h to 0188h
0199h to 0198h
01A9h to 01A8h
01B9h to 01B8h
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
Setting Range
RW
Set the transfer count minus 1. The written value is stored in the
DMAi transfer counter reload register, and when the DMAE bit
in the DMiCON register is set to 1 (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit in the DMiCON
register is 1 (repeat transfer), the value of the DMAi transfer
counter reload register is transferred to the DMAi transfer
counter.
When read, the DMAi transfer counter is read.
0000h to FFFFh
RW
Registers SAR0, SAR1, SAR2, SAR3, DAR0, DAR1, DAR2, DAR3, TCR0, TCR1, TCR2,
and TCR3
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14.1
14. DMAC
Transfer Cycles
Transfer cycle is composed of a bus cycle to read data from source address (source read) and a bus
cycle to write data to destination address (destination write). The number of read and write bus cycles
depends on source and destination addresses. During memory extension and microprocessor modes, it
is also affected by the BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or
RDY signal.
14.1.1
Effect of Source and Destination Addresses
When a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd
address, source-read cycle is incremented by one bus cycle, compared to a source address starting
with an even address.
When a 16-bit data is transferred with a 16-bit data bus and a destination address starts with an odd
address, destination-write cycle is incremented by one bus cycle, compared to a destination address
starting with an even address.
14.1.2
Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit
data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike in
the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
14.1.3
Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
14.1.4
Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area are
affected by the RDY signal. Refer to 8.2.6 “RDY Signal”.
Figure 14.6 shows the example of the Transfer Cycles for Source Read. For convenience, the destination
write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In
reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) on Figure 14.6), two source read bus cycles and two
destination write bus cycles are required.
REJ09B0392-0064 Rev.0.64
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
14. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
CPU use
Source
Dummy
cycle
Destination
CPU use
RD signal
WR signal
Data bus
CPU use
Source
Dummy
cycle
Destination
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
NOTE :
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 14.6
Transfer Cycles for Source Read
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14.2
14. DMAC
DMA Transfer Cycles
The number of DMA transfer cycles can be calculated as follows.
Table 14.2 lists the DMAC Transfer Cycles. Table 14.3 lists the Coefficients j and k.
Number of transfer cycles per transfer unit = Number of read cycles × j + Number of write cycles × k
Table 14.2
DMAC Transfer Cycles
Transfer Unit
8-bit Transfers
(DMBIT= 1)
Bus Width
Single-Chip Mode
Access
Address
16-bit
(BYTE = “L”)
No. of Read
Cycles
1
1
1
2
-
Even
Odd
Even
Odd
Even
Odd
Even
Odd
8-bit
(BYTE = “H”)
16-bit Transfers 16-bit
(DMBIT= 0)
(BYTE = “L”)
8-bit
(BYTE = “H”)
No. of Write
Cycles
1
1
1
2
-
Memory Expansion Mode
Microprocessor Mode
No. of Read No. of Write
Cycles
Cycles
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
- indicates that no condition exists.
Table 14.3
Coefficients j and k
Internal Area
Internal ROM,
SFR
RAM
1-Wait 2-Wait
No
With
(2)
(2)
Wait
Wait
j
k
1
1
2
2
2
2
3
3
External Area
Separate Bus
No
Wait
1
2
With Wait (1)
1-Wait 2-Wait 3-Wait
2
3
4
2
3
4
NOTES:
1. It depends on the set value of the CSE register.
2. It depends on the set value of the PM20 bit in the PM2 register.
REJ09B0392-0064 Rev.0.64
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Multiplex Bus
With Wait (1)
1-Wait 2-Wait 3-Wait
3
3
4
3
3
4
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14.3
14. DMAC
DMA Enabled
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0 to 3) to 1 (enabled),
the DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON
register is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1
(forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to 1 again while it remains set, the DMAC performs the above operation. However,
if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
14.4
DMA Request
The DMAC can generate a DMA request as triggered by the factor of request that is selected with the
DMS bit and bits DSEL4 to DSEL0 in the DMiSL register (i = 0 to 3) on either channel. Table 14.1 lists
the Timing at Which the DMAS Bit Changes State.
Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of
whether or not the DMAE bit is set. If the DMAE bit is set to 1 (enabled) when this occurs, the DMAS bit
is set to 0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 in
a program (it can only be set to 0).
The DMAS bit may be set to 1 when the DMS bit or bits DSEL4 to DSEL0 change state. Therefore,
always be sure to set the DMAS bit to 0 after changing the DMS bit or bits DSEL4 to DSEL0.
Because if the DMAE bit is 1, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is 0 when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 14.4
Timing at Which the DMAS Bit Changes State
DMA Factor
Software Trigger
Peripheral Function
DMAS Bit in the DMiCON Register
Timing at which the bit is set to 1
Timing at which the bit is set to 0
When the DSR bit in the DMiSL register • Immediately before a data transfer
is set to 1
starts
•
When
set by writing a 0 in a program
When the interrupt control register for
the peripheral function that is selected
by bits DSEL4 to DSEL0 and DMS in
the DMiSL register has its IR bit set to 1
i = 0 to 3
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
14.5
14. DMAC
Channel Priority and DMA Transfer Timing
If several channels of DMA0 to DMA3 are enabled and DMA transfer request signals are detected active
in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS
bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA requests are
arbitrated according to the channel priority: DMA0 > DMA1 > DMA2 > DMA3. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 14.7 shows an example of DMA Transfer by External Factors.
In Figure 14.7, DMA0 request having priority is received first to start a transfer when DMA0 and DMA1
requests are generated simultaneously. After one DMA0 transfer is completed, a bus access privilege is
returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one
DMA1 transfer is completed, the bus access privilege is again returned to the CPU.
In addition, DMA requests cannot be incremented since each channel has one DMAS bit. Therefore,
when DMA requests, as DMA1 in Figure 14.7, occurs more than one time, the DMAS bit is set to 0 after
getting the bus access privilege. The bus access privilege is returned to the CPU when one transfer is
completed.
Refer to 8.2.7 “HOLD Signal” for details about bus access privilege.
An example when DMA requests for external factors are detected active
at the same time and DMA transfer is executed in the shortest cycle
BCLK
DMA0
Bus
access
privilege
DMA1
CPU
INT0
DMAS bit
in DMA0
INT1
DMAS bit
in DMA1
Figure 14.7
DMA Transfer by External Factors
REJ09B0392-0064 Rev.0.64
Page 133 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
15. Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as
either Timer A (five) and Timer B (six). The count source for each timer acts as a clock, to control such timer
operations as counting, reloading, etc. Figure 15.1 shows Timers A and B count source, and Figures 15.2
and 15.3 show block diagrams of Timer A and Timer B configuration, respectively.
Clock Generation Circuit
Main clock
generation circuit
or PLL frequency
synthesizer
CM21 = 0
f1TIMAB PCLK0 = 1
f1
1/2
CM21 = 1
f1TIMAB
or
f2TIMAB
f2TIMAB
PCLK0 = 0
f8TIMAB
1/8
125 KHz
on-chip
oscillator
Subclock
generation
circuit
fOCO-S
fOCO-S
1/2
fC
1/32
fOCO-S
Reset
Timers A and B Count Source
REJ09B0392-0064 Rev.0.64
Page 134 of 373
Oct 12, 2007
f64TIMAB
fC32
Set the CPSR bit in the CPSRF
register to 1 (prescaler reset).
Figure 15.1
f32TIMAB
1/4
fC32
CM21 : bit in the CM2 register
PCLK0 : bit in the PCLKR register
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
fC32
fOCO-S
f64TIMAB
f32TIMAB
f8TIMAB
f1TIMAB
or f2TIMAB
00
TCK1 to TCK0
01
10
0
10
11
000
TMOD1 to TMOD0
TCS3
00: Timer mode
10: One-shot timer mode
11: PWM mode
1
TCS2 to TCS0
01
00
001
010
011
101
11
Timer A0
Timer A0 interrupt
01: Event counter mode
TA0TGH to TA0TGL
110
Noise
filter
TA0IN (1)
00
TCK1 to TCK0
01
10
0
10
11
000
TMOD1 to TMOD0
TCS7
1
TCS6 to TCS4
001
010
011
101
01
00
11
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A1
Timer A1 interrupt
01: Event counter mode
TA1TGH to TA1TGL
110
Noise
filter
TA1IN
00
TCK1 to TCK0
01
10
0
10
11
000
TMOD1 to TMOD0
TCS3
00: Timer mode
10: One-shot timer mode
11: PWM mode
1
TCS2 to TCS0
01
00
001
010
011
101
11
Timer A2
Timer A2 interrupt
01: Event counter mode
TA2TGH to TA2TGL
110
Noise
filter
TA2IN
00
01
10
TCK1 to TCK0
0
10
11
000
TMOD1 to TMOD0
TCS7
1
TCS6 to TCS4
001
01
00
11
010
011
101
00: Timer mode
10: One-shot timer mode
11: PWM mode
Timer A3
Timer A3 interrupt
01: Event counter mode
TA3TGH to TA3TGL
110
Noise
filter
TA3IN
00
01
10
TCK1 to TCK0
0
10
11
000
TMOD1 to TMOD0
TCS3
TCS2 to TCS0
00: Timer mode
10: One-shot timer mode
11: PWM mode
1
001
010
011
101
01
00
11
Timer A4
01: Event counter mode
TA4TGH to TA4TGL
110
Noise
filter
TA4IN
Timer B2 overflow or underflow
TCK1 to TCK0, TMOD1 to TMOD0 : bits in the TAiMR register
TAiGH to TAiGL
: bits in the ONSF register or TRGSR register
TCS0 to TCS7
: bits in registers TACS0 to TACS2
i = 0 to 4
NOTE:
1. Be aware that TA0IN shares pins with TB5IN.
Figure 15.2
Timer A Configuration
REJ09B0392-0064 Rev.0.64
Page 135 of 373
Oct 12, 2007
Timer A4 interrupt
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
fC32
fOCO-S
f64TIMAB
f32TIMAB
f8TIMAB
f1TIMAB
or f2TIMAB
Timer B2 overflow or underflow
(to a count source of Timer A)
↑
00
01
10
TMOD1 to TMOD0
TCK1 to TCK0
0
00: Timer mode
10: Pulse width / pulse period measurement mode
TCS3
11
000
1
TCS2 to TCS0
1
0
Timer B0
TCK1
001
010
011
101
Timer B0 interrupt
01: Event counter mode
110
Noise
filter
TB0IN
00
01
10
TCK1 to TCK0
TMOD1 to TMOD0
0
00: Timer mode
10: Pulse width / pulse period measurement mode
TCS7
11
000
1
TCS6 to TCS4
1
0
Timer B1
TCK1
001
010
011
101
Timer B1 interrupt
01: Event counter mode
110
Noise
filter
TB1IN
00
01
10
TCK1 to TCK0
TMOD1 to TMOD0
0
00: Timer mode
10: Pulse width / pulse period measurement mode
TCS3
11
000
1
TCS2 to TCS0
1
0
001
010
011
101
Timer B2
TCK1
Timer B2 interrupt
01: Event counter mode
110
Noise
filter
TB2IN
00
TCK1 to TCK0
01
10
TMOD1 to TMOD0
0
00: Timer mode
10: Pulse width / pulse period measurement mode
TCS3
11
000
1
TCS2 to TCS0
1
0
001
010
011
101
Timer B3
TCK1
Timer B3 interrupt
01: Event counter mode
110
Noise
filter
TB3IN
00
TCK1 to TCK0
01
10
TMOD1 to TMOD0
0
00: Timer mode
10: Pulse width / pulse period measurement mode
TCS7
11
000
001
1
TCS6 to TCS4
1
0
Timer B4
TCK1
Timer B4 interrupt
01: Event counter mode
010
011
101
110
Noise
filter
TB4IN
00
TMOD1 to TMOD0
TCK1 to TCK0
01
10
0
00: Timer mode
10: Pulse width / pulse period measurement mode
TCS3
11
000
TCS2 to TCS0
1
001
010
011
101
Figure 15.3
Noise
filter
Timer B Configuration
REJ09B0392-0064 Rev.0.64
Page 136 of 373
Timer B5
TCK1
Timer B5 interrupt
01: Event counter mode
TCK1 to TCK0, TMOD1 to TMOD0 : bits in the TBiMR register (i = 0 to 5)
TCS0 to TCS7
: bits in registers TBCS0 to TBCS3
110
TB5IN (1)
1
0
Oct 12, 2007
NOTE:
1. Be aware that TB5IN shares pins with TA0IN.
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.1
15. Timers
Timer A
Figure 15.4 shows a Timer A Block Diagram. Figures 15.5 to 15.9 show registers related to Timer A.
Timer A supports the following four modes. Except in event counter mode, Timers A0 to A4 all have the
same function. Use bits TMOD1 to TMOD0 in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer Mode
The timer counts an internal count source.
• Event Counter Mode
The timer counts pulses from an external device or overflows and
underflows of other timers.
• One-shot Timer Mode
The timer outputs a pulse only once before it reaches the minimum
count 0000h.
• Pulse Width Modulation (PWM) Mode
The timer outputs pulses in a given width successively.
fC32
fOCO-S
f64TIMAB
f32TIMAB
f8TIMAB
f1TIMAB
or f2TIMAB
Count source select
00
TCK1 to TCK0
01
10
0
TCS3
or
TCS7
11
000
TCS2 to TCS0
or TCS6 to TCS4
Data Bus
·Timer:
TMOD1 to TMOD0 = 00, MR2 = 0
·One-shot timer:
TMOD1 to TMOD0 = 10
TMOD1 to TMOD0,
·Pulse width modulation: TMOD1 to TMOD0 = 11
MR2
1
·Timer (gate function):
TMOD1 to TMOD0 = 00, MR2 = 1
Reload Register
·Event counter: TMOD1 to TMOD0 = 01
001
010
011
101
Counter
TAiS
110
Decrement
Polarity
Select
TAiIN
00
10
11
01
00
TB2 overflow (1)
TAj overflow (1)
TAk overflow (1)
Increment / decrement
Always decrement except
in event counter mode
TMOD1 to TMOD0
01
10
To external
trigger circuit
11
TAiTGH to TAiTGL
TAiUD
0
1
POFSi
TAiOUT
MRO
0
MR2
Toggle Flip Flop
1
NOTES:
1. Overflow or underflow
TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1 : bits in the TAiMR register
TAiTGH to TAiTGL : bits in the ONSF register when i=0, bits in the TRGSR register when i = 1 to 4
TAiS
: bits in the TABSR register
TAiUD
: bits in the UDF register
TCS0 to TCS7
: bits in the registers TACS0 to TACS2
POFSi
: bits in the TAPOFS register
Figure 15.4
Timer A Block Diagram
REJ09B0392-0064 Rev.0.64
Page 137 of 373
Oct 12, 2007
i = 0 to 4
j = i - 1, however, j = 4 if i = 0
k = i + 1, however, k = 0 if i = 4
Tai
TAj
TAk
Timer A0
Timer A4
Timer A1
Timer A1
Timer A0
Timer A2
Timer A2
Timer A1
Timer A3
Timer A3
Timer A2
Timer A4
Timer A4
Timer A3
Timer A0
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Ai Mode Register (i= 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TA0MR to TA4MR
Bit Name
Bit Symbol
TMOD0
Operation mode select bit
TMOD1
After Reset
00h
0336h to 033Ah
Function
RW
b1
b0
0
0
1
1
0 : Timer mode
1 : Event counter mode
0 : One-shot timer mode
1 : Pulse width modulation (PWM)
mode
RW
MR0
MR1
MR2
RW
RW
Function varies with each operation mode
RW
MR3
TCK0
TCK1
RW
RW
RW
Count source select bit (1)
(Function varies with each operation mode)
RW
NOTE :
1. Valid when the bit3 or the bit 7 in registers TACS0 to TACS2 is set to 0 (TCK0, TCK1 enabled).
Timer Ai Register (i= 0 to 4) (1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Mode
Timer mode
Address
0327h to 0326h
0329h to 0328h
032Bh to 032Ah
032Dh to 032Ch
032Fh to 032Eh
Function
Setting Range
RW
0000h to FFFFh
RW
0000h to FFFFh
RW
0000h to FFFFh (2, 4)
WO
Modify the pulse width as follows:
PWM period: (216 – 1) / fj
PWM pulse width: n / fj
where n = set value, fj = count source
frequency
0000h to FFFEh (3, 4)
WO
Modify the pulse width as follows:
PWM period: (28 – 1) × (m + 1) / fj
PWM pulse width: (m + 1)n / fj
where n = high-order address set
value, m = low-order address set
value,
fj = count source frequency
00h to FEh
(High-order
address)
00h to FFh
(Low-order address)
Divide the count source by n + 1 where
n = set value
Divide the count source by FFFFh – n +
Event counter mode 1 where n = set value when counting up
or by n + 1 when counting down (5)
One-shot timer mode
Pulse width
modulation mode
(16-bit PWM)
Pulse width
modulation mode
(8-bit PWM)
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Divide the count source by n where n =
set value, and the counter stops
WO
(3, 4)
NOTES :
1. Access to the register in 16-bit units.
2. If the TAi register is set to 0000h, the counter does not work and timer Ai interrupt requests are not generated
either. Furthermore, if pulse output is selected, no pulses are output from the TAiOUT pin.
3. If the TAi register is set to 0000h, the pulse width modulator does not work, the output level on the TAiOUT pin
remains low, and timer Ai interrupt requests are not generated either. The same applies when the 8 high-order
bits of the timer TAi register are set to 00h while operating as an 8-bit pulse width modulator.
4. Use the MOV instruction to write to the TAi register.
5. The timer counts pulses from an external device or overflows or underflows in other timers.
Figure 15.5
Registers TA0MR to TA4MR and TA0 to TA4
REJ09B0392-0064 Rev.0.64
Page 138 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TABSR
0320h
00h
Bit Name
Bit Symbol
Function
RW
0 : Stop counting
1 : Start counting
TA0S
Timer A0 count start flag
RW
TA1S
Timer A1 count start flag
RW
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
Up / Down Flag
Symbol
UDF
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
Address
After Reset
0324h
00h
Bit Name
TA0UD
Timer A0 up / down flag
TA1UD
Timer A1 up / down flag
Function
0 : Decrement
1 : Increment
RW
RW
RW
Enabled during event counter mode (when not
using two-phase pulse signal)
TA2UD
Timer A2 up / down flag
TA3UD
Timer A3 up / down flag
RW
TA4UD
Timer A4 up / down flag
RW
TA2P
Timer A2 two-phase
pulse signal processing
select bit
TA3P
Timer A3 two-phase
pulse signal processing
select bit
TA4P
Timer A4 two-phase
pulse signal processing
select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
enabled (1, 2)
RW
RW
RW
RW
NOTES :
1. Set the port direction bits for pins TA2IN to TA4IN and pins TA2OUT to TA4OUT to 0 (input mode).
2. When not using the two-phase pulse signal processing function, set the bit corresponding to Timer A2 to Timer
A4 to 0.
Figure 15.6
Registers TABSR and UDF
REJ09B0392-0064 Rev.0.64
Page 139 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
ONSF
0322h
00h
Bit Name
Bit Symbol
Function
RW
The timer starts counting by setting this bit
to 1 while bits TMOD1 and TMOD0 in the
TAiMR register (i = 0 to 4) = 10b (one-shot
timer mode) and the MR2 bit in the TAiMR
register = 0 (TAiOS bit enabled). Read as 0
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
RW
TA3OS
Timer A3 one-shot start flag
RW
TA4OS
Timer A4 one-shot start flag
RW
TAZIE
Z-phase input enable bit
0 : Z-phase input disabled
1 : Z-phase input enabled
b7
TA0TGL
Timer A0 event / trigger
select bit
TA0TGH
0
0
1
1
RW
RW
b6
0:
1:
0:
1:
RW
Input on TA0IN pin is selected (1)
TB2 is selected (2)
TA4 is selected (2)
TA1 is selected (2)
RW
RW
NOTES :
1. Make sure the PD7_1 bit in the PD7 register is set to 0 ( input mode).
2. Overflow or underflow.
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRGSR
0323h
00h
Bit Name
Bit Symbol
TA1TGL
Timer A1 event / trigger
select bit
TA1TGH
TA2TGL
Timer A2 event / trigger
select bit
TA2TGH
TA3TGL
Timer A3 event / trigger
select bit
TA3TGH
TA4TGL
Timer A4 event / trigger
select bit
TA4TGH
Function
b1
0
0
1
1
b0
0 : Input on TA1IN is selected
1 : TB2 is selected (2)
0 : TA0 is selected (2)
1 : TA2 is selected (2)
b3
0
0
1
1
b2
0 : Input on TA2IN is selected
1 : TB2 is selected (2)
0 : TA1 is selected (2)
1 : TA3 is selected (2)
b5
0
0
1
1
b4
0 : Input on TA3IN is selected
1 : TB2 is selected (2)
0 : TA2 is selected (2)
1 : TA4 is selected (2)
b7
0
0
1
1
b6
0 : Input on TA4IN is selected
1 : TB2 is selected (2)
0 : TA3 is selected (2)
1 : TA0 is selected (2)
NOTES :
1. Set the port direction bits for the pins TA1IN to TA4IN to 0 (input mode).
2. Overflow or underflow
Figure 15.7
Registers ONSF and TRGSR
REJ09B0392-0064 Rev.0.64
Page 140 of 373
Oct 12, 2007
RW
(1)
RW
RW
(1)
RW
RW
(1)
RW
RW
(1)
RW
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Clock Prescaler Reset Flag
Symbol
CPSRF
b7 b6 b5 b4 b3 b2 b1 b0
Address
0015h
After Reset
0XXXXXXXb
Bit Name
Bit Symbol
Function
—
(b6-b0)
No register bits. If necessary, set to 0. Read as undefined value
CPSR
Clock prescaler reset flag
RW
—
Initializing the clock prescaler.
(Read as 0)
RW
Timer A Count Source Select Register 0, Timer A Count Source Select Register 1
Symbol
b7 b6 b5 b4 b3 b2 b1 b0
TACS0 to TACS1
After Reset
00h
Bit Name
Bit Symbol
TCS0
Address
01D0h to 01D1h
TAi count source select bit
TCS1
TCS2
TCS3
TAi count source option
specified bit
TCS4
TCS5
TAj count source select bit
TCS6
TCS7
TACS0 register: i = 0, j = 1
TAj count source option
specified bit
Registers CPSRF, TACS0, and TACS1
REJ09B0392-0064 Rev.0.64
Page 141 of 373
b2
b1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Oct 12, 2007
RW
b0
0 : f1TIMAB or f2TIMAB
1 : f8TIMAB
0 : f32TIMAB
1 : f64TIMAB
0 : Do not set
1 : fOCO-S
0 : f C32
1 : Do not set
(1)
b6
b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
RW
RW
RW
1 : TCK0, TCK1 enabled, TCS0 to TCS2
disabled
0 : TCK0, TCK1 disabled, TCS0 to TCS2
enabled
RW
b4
0 : f1TIMAB or f2TIMAB
1 : f8TIMAB
0 : f32TIMAB
1 : f64TIMAB
0 : Do not set
1 : fOCO-S
0 : fC32
1 : Do not set
(1)
1 : TCK0, TCK1 enabled, TCS4 to TCS6
disabled
0 : TCK0, TCK1 disabled, TCS4 to TCS6
enabled
TACS1 register: i = 2, j = 3
NOTE :
1. Set this value at the PCLK0 bit in the PCLKR register.
Figure 15.8
Function
RW
RW
RW
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer A Count Source Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TACS2
01D2h
X0h
Bit Name
Bit Symbol
TCS0
Function
TA4 count source select bit
TCS1
TCS2
TCS3
—
(b7-b4)
TA4 count source option
specified bit
b2
b1
b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
:
:
:
:
:
:
:
:
f1TIMAB or f2TIMAB
f8TIMAB
f32TIMAB
f64TIMAB
Do not set
fOCO-S
fC32
Do not set
RW
(1)
RW
RW
RW
1 : TCK0, TCK1 enabled, TCS0 to TCS2
disabled
0 : TCK0, TCK1 disabled, TCS0 to TCS2
enabled
RW
No register bits. If necessary, set to 0. Read as undefined value.
—
NOTE :
1. Set this value at the PCLK0 bit in the PCLKR register.
Timer A Waveform Output Function Select Register
Symbol
b7 b6 b5 b4 b3 b2 b1 b0
TAPOFS
Figure 15.9
Address
After Reset
01D5h
XXX00000b
Bit Symbol
Bit Name
POFS0
TA0OUT output polar control bit
POFS1
TA1OUT output polar control bit
POFS2
TA2OUT output polar control bit
RW
POFS3
TA3OUT output polar control bit
RW
POFS4
TA4OUT output polar control bit
RW
—
(b7-b5)
No register bits. If necessary, set to 0. Read as undefined value
Registers TACS2 and TAPOFS
REJ09B0392-0064 Rev.0.64
Page 142 of 373
Oct 12, 2007
Function
0 : Output waveform "H" active
1 : Output waveform "H" active
(output reversed)
RW
RW
RW
—
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.1.1
15. Timers
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 15.1). Figure 15.10
shows TAiMR Register in Timer Mode.
Table 15.1
Specifications in Timer Mode
Item
Count Source
Count Operation
Specification
f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32
• Decrement
• When the timer underflows, it reloads the reload register contents and continues counting
1 / (n+1)
n: set value of TAi register 0000h to FFFFh
Set the TAiS bit in the TABSR register to 1 (start counting)
Set the TAiS bit to 0 (stop counting)
Timer underflow
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request Generation
Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
I/O port or gate input
I/O port or pulse output
Count value can be read by reading the TAi register
• When not counting
Value written to the TAi register is written to both reload register and counter
• When counting
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Counting can be started and stopped by an input signal to the TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When the TAiS bit is set to 0 (stop counting), the pin outputs “L.”
• Output polarity control
While the output polarity of the TAiOUT pin is inverted (the TAiS bit is set to 0
(stop counting)), the pin outputs “H.”
Select Function
i = 0 to 4
Timer Ai Mode Register (i = 0 to 4)
Symbol
Address
After Reset
TA0MR to TA4MR
0336h to 033Ah
00h
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Bit Name
Bit Symbol
TMOD0
Operation mode select bit
TMOD1
MR0
Pulse output function
select bit
RW
RW
b1 b0
0
0 : Timer mode
RW
0 : No pulse output
(TAiOUT pin functions as I/O port)
1 : Pulse output (1)
(TAiOUT pin functions as a pulse output pin)
b4 b3
MR1
Gate function select bit
MR2
MR3
Function
0
0
1
1
0:
Gate function not available
1:
(TAiIN pin functions as I/O port)
0 : Counts while input on the TAiIN pin is low (2)
1 : Counts while input on the TAiIN pin is high (2)
Set to 0 in timer mode
RW
RW
RW
b1 b0
TCK0
Count source select bit (4)
TCK1
0
0
1
1
0 : f1TIMAB or f2TIMAB
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
(3)
NOTES :
1. The TA0OUT pin is N-channel open drain output.
2. Set the port direction bit for the TAiIN pin to 0 (input mode).
3. Selected by the PCLK0 bit in the PCLKR register.
4. Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0, TCK1 enabled).
Figure 15.10 TAiMR Register in Timer Mode
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RW
Oct 12, 2007
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.1.2
15. Timers
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 15.2 lists Specifications in Event Counter Mode (When Not Processing Two-Phase Pulse Signal). Figure 15.11 shows the
TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing).
Table 15.2
Specifications in Event Counter Mode (When Not Processing Two-Phase Pulse Signal)
Item
Count Source
Specification
• External signals input to the TAiIN pin (effective edge can be selected in a
program)
• Timer B2 overflows or underflows,
Timer Aj (j = i - 1, except j = 4 if i = 0) overflows or underflows,
Timer Ak (k = i + 1, except k=0 if i = 4) overflows or underflows
Count Operation
• Increment or decrement can be selected by program.
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divide Ratio
• 1/ (FFFFh - n + 1) for increment
• 1/ (n + 1) for decrement
n: set value of the TAi register 0000h to FFFFh
Count Start Condition
Set the TAiS bit in the TABSR register to 1 (start counting)
Count Stop Condition
Set the TAiS bit to 0 (stop counting)
Interrupt Request Genera- Timer overflow or underflow
tion Timing
TAiIN Pin Function
I/O port or count source input
TAiOUT Pin Function
I/O port, pulse output
Read from Timer
Count value can be read by reading the TAi register
Write to Timer
• When not counting
Value written to the TAi register is written to both reload register and
counter
• When counting
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select Function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of the
TAiOUT pin is inverted. When the TAiS bit is set to 0 (stop counting), the pin
outputs low.
• Output polarity control
While the output polarity of the TAiOUT pin is inverted (the TAiS bit is set to
0 (stop counting)), the pin outputs high.
i = 0 to 4
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Ai Mode Register (i = 0 to 4)
(When Not Using Two-Phase Pulse Signal Processing)
Symbol
Address
After Reset
TA0MR to TA4MR
0336h to 033Ah
00h
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 1
Bit Symbol
Bit Name
TMOD0
Function
b1 b0
Operation mode select bit 0
RW
RW
1 : Event counter mode (1)
TMOD1
RW
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (3)
(TAiOUT pin functions as pulse output pin)
RW
MR1
Count polarity select bit (2)
0 : Counts falling edge of external signal
1 : Counts rising edge of external signal
RW
MR2
Write 0 in event counter mode
RW
MR3
Write 0 in event counter mode
RW
TCK0
Count operation type
select bit
RW
TCK1
Can be 0 or 1 when not using two-phase pulse signal processing
0 : Reload type
1 : Free-run type
RW
NOTES :
1. During event counter mode, the count source can be selected using registers ONSF and TRGSR.
2. Valid when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 00b (TAiIN pin input).
3. The TA0OUT pin is N-channel open drain output.
Figure 15.11 TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Table 15.3 lists Specifications in Event Counter Mode (when processing two-phase pulse signal with
Timers A2, A3, and A4). Figure 15.12 shows Registers TA2MR to TA4MR in Event Counter Mode
(when using two-phase pulse signal processing with Timers A2, A3, and A4).
Table 15.3
Specifications in Event Counter Mode (when processing two-phase pulse signal with
Timers A2, A3, and A4)
Item
Specification
Count Source
Count Operation
Two-phase pulse signals input to TAiIN or TAiOUT pin
• Increment or decrement can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading.
Divide Ratio
• 1/ (FFFFh - n + 1) for increment
• 1/ (n + 1) for decrement
n: set value of the TAi register 0000h to FFFFh
Count Start Condition
Set the TAiS bit in the TABSR register to 1 (start counting)
Count Stop Condition
Set the TAiS bit to 0 (stop counting)
Interrupt Request Generation Timing Timer overflow or underflow
TAiIN Pin Function
Two-phase pulse input
TAiOUT Pin Function
Two-phase pulse input
Read from Timer
Count value can be read by reading Timer A2, A3, or A4 register
Write to Timer
When not counting
Value written to the TAi register is written to both reload register and counter
When counting
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select Function (1)
Normal processing operation (Timer A2 and Timer A3)
The timer increments rising edges or decrements falling edges on the TAjIN pin when input
signals on the TAjOUT pin is “H”.
TAjOUT
TAjIN
Increment Increment Increment
Decrement Decrement Decrement
Multiply-by-4 processing operation (Timer A3 and Timer A4)
If the phase relationship is such that TAkIN pin goes “H” when the input signal on the TAkOUT pin is “H,” the timer increments rising and falling edges on pins TAkOUT and TAkIN.
If the phase relationship is such that the TAkIN pin goes “L” when the input signal on the
TAkOUT pin is “H,” the timer counts down rising and falling edges on pins TAkOUT and
TAkIN.
TAkOUT
Increment all edges
Decrement all edges
TAkIN
Increment all edges
Decrement all edges
Counter initialization by Z-phase input (Timer A3)
The timer count value is initialized to 0 by Z-phase input.
i = 2 to 4, j = 2, 3, k = 3, 4
NOTE:
1. Only Timer A3 is selectable. Timer A2 is fixed to normal processing operation, and Timer A4 is fixed
to multiply-by-4 processing operation.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Ai Mode Register (i = 2 to 4)
(When Using Two-Phase Pulse Signal Processing)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 1
Symbol
TA2MR to TA4MR
Address
After Reset
0338h to 033Ah
00h
Bit Name
Bit Symbol
TMOD0
Operation mode select bit
TMOD1
Function
b1 b0
0
1 : Event counter mode
RW
RW
RW
MR0
Set to 0 to use two-phase pulse signal processing
RW
MR1
Set to 0 to use two-phase pulse signal processing
RW
MR2
Set to 1 to use two-phase pulse signal processing
RW
MR3
Set to 0 to use two-phase pulse signal processing
RW
TCK0
Count operation type select
bit
0 : Reload type
1 : Free-run type
RW
TCK1
Two-phase pulse signal
processing operation type
select bit (1, 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
NOTES :
1. The TCK1 bit can be set only for Timer A3 mode register. No matter how this bit is set, Timers A2 and A4 always
operate in normal processing mode and x4 processing mode, respectively.
2. To use two-phase pulse signal processing, following the register setting below:
• Set the TAiP bit in the UDF register to 1 (two-phase pulse signal processing function enabled).
• Set bits TAiTGH and TAiTGL in the TRGSR register to 00b (TAiIN pin input).
• Set the port direction bits for TAiIN and TAiOUT to 0 (input mode).
Figure 15.12 Registers TA2MR to TA4MR in Event Counter Mode (when using two-phase pulse
signal processing with Timers A2, A3, and A4)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.1.2.1
15. Timers
Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to 0 by Z-phase (counter initialization) input during twophase pulse signal processing.
This function can only be used in Timer A3 event counter mode during two-phase pulse signal processing, free-running type, multiply-by-4 processing, with Z phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing 0000h to the TA3 register and setting the
TAZIE bit in the ONSF register to 1 (Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse
width applied to the ZP pin must be equal to or greater than one clock cycle of Timer A3 count
source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 15.13 shows
the Relationship between the Two-Phase Pulse (A Phase and B Phase) and the Z Phase.
If Timer A3 overflow or underflow coincides with the counter initialization by Z phase input, a Timer
A3 interrupt request is generated twice in succession. Do not use Timer A3 interrupt when using this
function.
TA3OUT
(A phase)
TA3IN
(B phase)
Count source
ZP (1)
Input equal to or greater than one clock cycle
of count source
Timer A3
m
m+1
1
2
3
4
5
NOTE :
1. This timing diagram is for the case where the POL bit in the INT2IC register = 1
(rising edge).
Figure 15.13 Relationship between the Two-Phase Pulse (A Phase and B Phase) and the Z Phase
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.1.3
15. Timers
One-Shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger (see Table 15.4). When the trigger occurs, the timer starts up and continues operating for a given period. Figure 15.14 shows the
TAiMR Register in One-Shot Timer Mode.
Table 15.4
Specifications in One-shot Timer Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Select Function
Specification
f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32
• Decrement
• When the counter reaches 0000h, it stops counting after reloading a new
value.
• If a trigger occurs when counting, the timer reloads a new count and restarts
counting.
1/n
n: set value of the TAi register
0000h to FFFFh
However, the counter does not work if the divide-by-n value is set to 0000h.
The TAiS bit in the TABSR register = 1 (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
Timer Aj (j = i - 1, except j = 4 if i = 0) overflow or underflow,
Timer Ak (k = i + 1, except k = 0 if i = 4) overflow or underflow
• The TAiOS bit in the ONSF register is set to 1 (timer starts)
• When the counter is reloaded after reaching 0000h
• The TAiS bit is set to 0 (stop counting)
When the counter reaches 0000h
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading the TAi register
• When not counting and until the 1st count source is input after counting starts
Value written to the TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
The timer outputs low when not counting and high when counting.
• Output polarity control
While the output polarity of TAiOUT pin is inverted (the TAiS bit is set to 0
(stop counting)), the pin outputs high.
i = 0 to 4
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Ai Mode Register (i = 0 to 4)
Symbol
Address
After Reset
TA0MR to TA4MR
0336h to 033Ah
00h
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Bit Symbol
TMOD0
Bit Name
Function
Operation mode select bit b1 b0
1 0 : One-shot timer mode
TMOD1
RW
RW
RW
MR0
Pulse output function
select bit
0 : No pulse output
(TAiOUT pin functions as I/O port)
1 : Pulse output (1)
(TAiOUT pin functions as a pulse output
pin)
MR1
External trigger select
bit (2)
0 : Falling edge of input signal to TAiIN pin (3)
1 : Rising edge of input signal to TAiIN pin (3)
RW
MR2
Trigger select bit
0 : TAiOS bit enabled
1 : Selected by bits TAiTGH and TAiTGL
RW
MR3
Set to 0 in one-shot timer mode
RW
RW
b7 b6
TCK0
Count source select bit (5)
TCK1
0
0
1
1
0 : f1TIMAB or f2TIMAB (4)
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
RW
NOTES :
1. The TA0OUT pin is N-channel open drain output.
2. Valid when bits TAiTGH and TAiTGL in the ONSF register or TRGSR register are set to 00b (TAiIN pin input).
3. Set the port direction bit for the TAiIN pin to 0 (input mode).
4. Selected by the PCLK0 bit in the PCLKR register.
5. Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0, TCK1 enabled).
Figure 15.14 TAiMR Register in One-Shot Timer Mode
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.1.4
15. Timers
Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 15.5). The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 15.15 shows
TAiMR Register in PWM Mode. Figures 15.16 and 15.17 show an Example of 16-Bit Pulse Width Modulator Operation and 8-bit Pulse Width Modulator Operation, respectively.
Table 15.5
Specifications in PWM Mode
Item
Count Source
Count Operation
16-bit PWM
8-bit PWM
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Select Function
Specification
f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32
• Decrement (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues
counting.
• The timer is not affected by a trigger that occurs during counting.
• Pulse width n / fj
n: set value of the TAi register
16
fj: count source frequency (1TIMAB, f2TIMAB,
• Cycle time (2 - 1) / fj fixed
f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32)
• Pulse width n × (m+1) / fj
n: set value of the TAi register high-order
address
m: set value of the TAi register low-order
• Cycle time (28-1) × (m+1) / fj
address
• The TAiS bit of the TABSR register is set to 1 (start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
Timer B2 overflow or underflow,
Timer Aj (j = i - 1, except j = 4 if i = 0) overflow or underflow,
Timer Ak (k = i + 1, except k = 0 if i = 4) overflow or underflow
The TAiS bit is set to 0 (stop counting)
On the falling edge of PWM pulse
I/O port or trigger input
Pulse output
An indeterminate value is read by reading the TAi register
• When not counting
Value written to the TAi register is written to both reload register and counter
• When counting
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Output polarity control
While the output polarity of TAiOUT pin is inverted (the TAiS bit is set to 0
(stop counting)), the pin outputs high.
i = 0 to 4
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Ai Mode Register (i = 0 to 4)
Symbol
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Address
TA0MR to TA4MR
Bit Symbol
TMOD0
After Reset
00h
0336h to 033Ah
Bit Name
Function
RW
Operation mode select bit b1 b0
1 1 : PWM mode
RW
TMOD1
RW
MR0
Pulse output function
select bit (4)
0 : No pulse output
(TAiOUT pin functions as I/O port)
1 : Pulse output (1)
(TAiOUT pin functions as a pulse output
pin)
RW
MR1
External trigger select
bit (2)
0 : Falling edge of input signal to TAiIN pin (3)
1 : Rising edge of input signal to TAiIN pin (3)
RW
MR2
Trigger select bit
0 : Write 1 to the TAiS bit in the TABSR register
1 : Selected by bits TAiTGH and TAiTGL
RW
MR3
16 / 8-bit PWM mode select 0 : Functions as a 16-bit pulse width modulator
bit
1 : Functions as an 8-bit pulse width modulator
b7
TCK0
Count source select bit (6)
TCK1
0
0
1
1
RW
b6
0 : f1TIMAB or f2TIMAB
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
(5)
RW
NOTES :
1. The TA0OUT pin is N-channel open drain output.
2. Valid when bits TAiTGH and TAiTGL bit in the ONSF register or TRGSR register are set to 00b (TAiIN pin
input).
3. Set the port direction bit for the TAiIN pin to 0 (input mode).
4. Set this bit to 1 (pulse output) to output PWM pulse.
5. Selected by the PCLK0 bit in the PCLKR register.
6. Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0, TCK1 enabled).
Figure 15.15 TAiMR Register in PWM Mode
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
1 / fj × (216 - 1)
Count source
Input signal to TAiIN pin “H”
“L”
Trigger is not generated by this signal.
PWM pulse output
from TAiOUT pin
When TOFSi = 0
“H”
(waveform output = “H”
active, not inverted)
“L”
When TOFSi = 1
(waveform output = “L”
active, inverted)
IR bit in TAiIC register
1 / fj × n
“H”
“L”
“1”
“0”
fj: count source frequency
(f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB,
f64TIMAB, fOCO-S, fC32)
Set to 0 upon accepting an interrupt
request or by writing in program.
i = 0 to 4
TOFSi: bit in the TAPOFS register
NOTES :
1. n = 0000h to FFFEh
2. This timing diagram is for the case where the TAi register is 0003h, bits TAiTGH and TAiTGL in the
ONSF register or TRGSR register are 00b (input to the TAiIN pin), the MR1 bit in the TAiMR register is 1
(rising edge), and the MR2 bit in the TAiMR register is 1 (trigger selected by bits TAiTGH and TAiTGL).
Figure 15.16 Example of 16-Bit Pulse Width Modulator Operation
1 / fj × (m + 1) × (28 - 1)
Count source (1)
Input signal to TAiIN pin
“H”
“L”
1 / fj × (m+1)
8-bit prescaler
underflow signal (2)
“H”
“L”
1 / fj × (m + 1) × n
PWM pulse output
from TAiOUT pin
When TOFSi = 0
“H”
(waveform output = “H”
H”ctive, not inverted)
“L”
“H”
When TOFSi = 1
(waveform output = “L” “L”
active, inverted)
IR bit in TAiIC register
“1”
“0”
fj: count source frequency
(f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB,
f64TIMAB, fOCO-S, fC32)
Set to 0 upon accepting an interrupt request or by
writing in program.
i = 0 to 4
TOFSi: bit in TAPOFS register
NOTES :
1. The 8-bit prescaler counts the count source.
2. The 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler.
3. m = 00h to FFh, n=00h to FEh
4. This timing diagram is for the case where the TAi register is 0202h, bits TAiTGH and TAiTGL in the
ONSF register or TRGSR register are 00b (input to the TAiIN pin), the MR1 bit in the TAiMR register is 0
(falling edge), and the MR2 bit in the TAiMR register is 1 (trigger selected by bits TAiTGH and TAiTGL).
Figure 15.17 Example of 8-Bit Pulse Width Modulator Operation
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.2
15. Timers
Timer B
Figure 15.18 shows Timer B Block Diagram. Figures 15.19 to 15.21 show registers related to Timer B.
Timer B supports the following three modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to
5) to select the desired mode.
• Timer Mode
: The timer counts an internal count source.
• Event Counter Mode
: The timer counts pulses from an external device
or overflows or underflows of other timers.
• Pulse Period, Pulse Width Measurement Mode: The timer measures pulse period or pulse width of
an external signal.
Data Bus
f1TIMAB
or
f2TIMAB
f8TIMAB
f32TIMAB
fC32
f1TIMAB
or
f2TIMAB
f8TIMAB
f32TIMAB
f64TIMAB
fOCO-S
fC32
Select Clock Source
00
01
10
TCK1 to TCK0
0
TCS3
or TCS7
00: Timer
10: Pulse Period
and Pulse Width Measurement
Reload Register
TMOD1 to TMOD0
11
000
TCS2 to TCS0
or TCS6 to TCS4
1
1
TBj
Overflow (1)
001
010
011
101
TCK1
Counter
01: Event Counter
0
110
TBiIN
Polarity
Switching and
Edge Pulse
TBiS
Counter Reset Circuit
NOTE :
1. Overflows or underflows.
TCK1 to TCK0,
TMOD1 to TMOD0 : bits in the TBiMR register
TBiS
: bits in the TABSR register or TBSR register
TCS0 to TCS7
: bits in registers TBCS0 to TBCS3
Figure 15.18 Timer B Block Diagram
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i = 0 to 5
j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit Name
Bit Symbol
TMOD0
Address
033Bh to 033Dh
031Bh to 031Dh
After Reset
00XX0000b
00XX0000b
Function
Operation mode select bit
RW
b1
b0
0
0
1
0 : Timer mode
1 : Event counter mode
0 : Pulse period measurement mode
Pulse width measurement mode
1 : Do not set
TMOD1
1
RW
RW
MR0
MR1
RW
Function varies with each operation mode
RW
—
(b4)
No register bit. If necessary, set to 0. Read as undefined value
—
MR3
Function varies with each operation mode
RO
TCK0
Count source select bit (1)
(Function varies with each operation mode)
RW
TCK1
RW
NOTE :
1. Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0, TCK1 enabled).
Timer Bi Register (i = 0 to 5) (1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
TB0
TB1
TB2
TB3
TB4
TB5
0331h to 0330h
0333h to 0332h
0335h to 0334h
0311h to 0310h
0313h to 0312h
0315h to 0314h
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Mode
Function
Setting Range
RW
Timer mode
Divide the count source by n + 1 where
n = set value
0000h to FFFFh
RW
Event counter mode
Divide the count source by n + 1 where
n = set value (2)
0000h to FFFFh
RW
Pulse period
measurement mode
Pulse width
measurement mode
Measures a pulse period or width
0000h to FFFFh (3)
RW (4)
NOTES :
1. Access to the register in 16-bit units.
2. The timer counts pulses from an external device or overflows or underflows of other timers.
3. Set it when the TBiS bit in the TABSR or TBSR register is set to 0 (count stops).
4. Read only (RO) when the TBiS bit in the TABSR or TBSR register is set to 1 (count starts).
Figure 15.19 Register TB0MR to TB5MR and TB0 to TB5
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TABSR
0320h
00h
Bit Name
Bit Symbol
Function
RW
0 : Stop counting
1 : Start counting
TA0S
Timer A0 count start flag
RW
TA1S
Timer A1 count start flag
RW
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
Timer B3, B4, B5 Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TBSR
0300h
000XXXXXb
Bit Name
Bit Symbol
—
POFS0
(b4-b0)
Function
RW
No register bits. If necessary, set to 0. Read as undefined value
0 : Stop counting
1 : Start counting
—
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
RW
TB5S
Timer B5 count start flag
RW
RW
Clock Prescaler Reset Flag
Symbol
CPSRF
b7 b6 b5 b4 b3 b2 b1 b0
Address
0015h
Bit Name
Bit Symbol
Function
—
(b6-b0)
No register bits. If necessary, set to 0. Read as undefined value
CPSR
Clock prescaler reset flag
Figure 15.20 Register TABSR, TBSR, and CPSRF
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After Reset
0XXXXXXXb
Oct 12, 2007
Initializing the clock prescaler.
(Read as 0)
RW
—
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer B Count Source Select Register 0, Timer B Count Source Select Register 2
Symbol
TBCS0
TBCS2
b7 b6 b5 b4 b3 b2 b1 b0
Address
01C8h
01E8h
Bit Name
Bit Symbol
TCS0
Function
TBi count source select bit
TCS1
TCS2
TCS3
TCS4
TBi count source option
specified bit
TBj count source select bit
TCS6
TBj count source option
specified bit
TBCS0 register: i = 0, j = 1
b2
b1
RW
b0
0 0 0 : f1TIMAB or f2TIMAB (1)
0 0 1 : f8TIMAB
0 1 0 : f32TIMAB
0 1 1 : f64TIMAB
1 0 0 : Do not set
1 0 1 : fOCO-S
1 1 0 : f C32
1 1 1 : Do not set
1 : TCK0, TCK1 enabled, TCS0 to TCS2
disabled
0 : TCK0, TCK1 disabled, TCS0 to TCS2
enabled
b6
b5
b4
0 0 0 : f1TIMAB or f2TIMAB (1)
0 0 1 : f8TIMAB
0 1 0 : f32TIMAB
0 1 1 : f64TIMAB
1 0 0 : Do not set
1 0 1 : fOCO-S
1 1 0 : f C32
1 1 1 : Do not set
1 : TCK0, TCK1 enabled, TCS4 to TCS6
disabled
0 : TCK0, TCK1 disabled, TCS4 to TCS6
enabled
TCS5
TCS7
After Reset
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
TBCS2 register: i = 3, j = 4
NOTE :
1. Set this value at the PCLK0 bit in the PCLKR register.
Timer B Count Source Select Register 1, Timer B Count Source Select Register 3
Symbol
TBCS1
TBCS3
b7 b6 b5 b4 b3 b2 b1 b0
TBi count source select bit
TCS1
TCS2
TCS3
—
(b7-b4)
TBCS1 register: i = 2
After Reset
X0h
X0h
Bit Name
Bit Symbol
TCS0
Address
01C9h
01E9h
TBi count source option
specified bit
Function
b2
b1
No register bits. If necessary, set to 0. Read as undefined value
NOTE :
1. Set this value at the PCLK0 bit in the PCLKR register.
Figure 15.21 Registers TBCS0, TBCS1, TBCS2, and TBCS3
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b0
0 0 0 : f1TIMAB or f2TIMAB (1)
0 0 1 : f8TIMAB
0 1 0 : f32TIMAB
0 1 1 : f64TIMAB
1 0 0 : Do not set
1 0 1 : fOCO-S
1 1 0 : fC32
1 1 1 : Do not set
1 : TCK0, TCK1 enabled, TCS0 to TCS2
disabled
0 : TCK0, TCK1 disabled, TCS0 to TCS2
enabled
TBCS3 register: i = 5
Oct 12, 2007
RW
RW
RW
RW
RW
—
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.2.1
15. Timers
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 15.6). Figure 15.22
shows the TBiMR Register in Timer Mode.
Table 15.6
Specifications in Timer Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
Specification
f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32
• Decrement
• When the timer underflows, it reloads the reload register contents and continues
counting
1 / (n + 1)
n: set value of the TBi register
0000h to FFFFh
Set the TBiS bit (1) to 1 (start counting)
Set the TBiS bit to 0 (stop counting)
Timer underflow
I/O port
Count value can be read by reading the TBi register
• When not counting
Value written to the TBi register is written to both reload register and counter
• When counting
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 5
NOTE:
1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
assigned to bits 5 to 7 in the TBSR register.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Bi Mode Register (i = 0 to 5)
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Bit Symbol
Address
033Bh to 033Dh
031Bh to 031Dh
Bit Name
After Reset
00XX0000b
00XX0000b
Function
TMOD0
Operation mode select bit
TMOD1
b1 b0
0
0 : Timer mode
MR0
RW
RW
RW
RW
Set to 0 in timer mode
MR1
—
MR3
RW
No register bit. If necessary, set to 0. Read as undefined value
—
Write 0 in timer mode.
Read as undefined value in timer mode
RO
b7
TCK0
Count source select bit
TCK1
(2)
0
0
1
1
b6
0 : f1TIMAB or f2TIMAB (1)
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
NOTES :
1. Selected by the PCLK0 bit in the PCLKR register.
2. Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS2 is set to 0 (TCK0, TCK1 enabled).
Figure 15.22 TBiMR Register in Timer Mode
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RW
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.2.2
15. Timers
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 15.7). Figure 15.23 shows the TBiMR Register in Event Counter Mode.
Table 15.7
Specifications in Event Counter Mode
Item
Count Source
Count Operation
Divide Ratio
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
Specification
• External signals input to TBiIN pin (effective edge rising edge, falling edge,
or both rising and falling edges) can be selected in a program)
• Timer Bj overflow or underflow (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3)
• Decrement
• When the timer underflows, it reloads the reload register contents and continues counting.
1 / (n + 1)
n: set value of the TBi register
0000h to FFFFh
Set the TBiS bit (1) to 1 (start counting)
Set the TBiS bit to 0 (stop counting)
Timer underflow
Count source input
Count value can be read by reading the TBi register.
• When not counting
Value written to the TBi register is written to both reload register and counter
• When counting
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 5
NOTE:
1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
assigned to bits 5 to 7 in the TBSR register.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Bi Mode Register (i = 0 to 5)
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Bit Symbol
Address
033Bh to 033Dh
031Bh to 031Dh
Bit Name
After Reset
00XX0000b
00XX0000b
Function
TMOD0
b1 b0
Operation mode select bit 0
RW
RW
1 : Event counter mode
TMOD1
RW
b3 b2
0
MR0
Count polarity select bit
(1)
MR1
0
1
1
—
0 : Counts falling edges of external
signal
1 : Counts rising edges of external signal
0 : Counts falling and rising edges
external signal
1 : Do not set to this value
RW
RW
No register bit. If necessary, set to 0. Read as undefined value
—
MR3
Write 0 in event counter mode.
Read as undefined value in event counter mode
RO
TCK0
Invalid in event counter mode.
Set 0 or 1
RW
TCK1
Event clock select
0 : Input from TBiIN pin (2)
1 : TBj overflow or underflow
(j = i – 1; however, j = 2 if i = 0, j = 5 if i = 3)
RW
NOTES :
1. Valid when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits
can be set to 0 or 1.
2. Set the port direction bit for the TBiIN pin to 0 (input mode).
Figure 15.23 TBiMR Register in Event Counter Mode
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15.2.3
15. Timers
Pulse Period and Pulse Width Measurement Modes
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of
an external signal (see Table 15.8). Figure 15.24 shows the TBiMR Register in Pulse Period and Pulse
Width Measurement Mode. Figure 15.25 shows the Operation Timing when Measuring a Pulse Period.
Figure 15.26 shows the Operation Timing when Measuring a Pulse Width.
Table 15.8
Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count Source
Count Operation
Count Start Condition
Count Stop Condition
Interrupt Request
Generation Timing
TBiIN Pin Function
Read from Timer
Write to Timer
Specification
f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S, fC32
• Increment
• Counter value is transferred to reload register at an effective edge of
measurement pulse. The counter value is set to 0000h to continue counting.
Set the TBiS bit (3) to 1 (start counting)
Set the TBiS bit to 0 (stop counting)
• When an effective edge of measurement pulse is input (1)
Timer overflow. When an overflow occurs, the MR3 bit in the TBiMR register is
set to 1 (overflowed) simultaneously.
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading the
TBi register (2)
Value written to the TBi register is written to neither reload register nor counter
i = 0 to 5
NOTES:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from the TBi register is indeterminate until the second valid edge is input after the timer
starts counting.
3. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
assigned to bits 5 to 7 in the TBSR register.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Timer Bi Mode Register (i = 0 to 5)
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
b7 b6 b5 b4 b3 b2 b1 b0
1 0
Bit Symbol
Address
033Bh to 033Dh
031Bh to 031Dh
Bit Name
After Reset
00XX0000b
00XX0000b
Function
TMOD0
b1
Operation mode select bit 1
TMOD1
b0
0 : Pulse period, pulse width
measurement mode
RW
RW
RW
b3 b2
0
MR0
0
Measurement mode
select bit
1
MR1
1
—
MR3
0 : Pulse period measurement
(Measurement between a falling edge and
the next falling edge of measured pulse)
1 : Pulse period measurement
(Measurement between a rising edge and
the next rising edge of measured pulse)
0 : Pulse width measurement
(Measurement between a falling edge and
the next rising edge of measured pulse
and between a rising edge and the next
falling edge)
1 : Do not set to this value
No register bit. If necessary, set to 0. Read as undefined value
Timer Bi overflow flag (1)
0 : No overflow
1 : Overflow
b7
TCK0
Count source select bit
TCK1
(3)
0
0
1
1
b6
0 : f1TIMAB or f2TIMAB (2)
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
RW
RW
—
RO
RW
RW
NOTES :
1. This flag is indeterminate after reset. When the TBiS bit in the TABSR register or TBSR register is set to 1
(start counting), the MR3 bit is cleared to 0 (no overflow) by writing to the TBiMR register. The MR3 bit cannot
be set to 1 in a program.
2. Selected by the PCLK0 bit in the PCLKR register.
3. Valid when the TCS3 bit or TCS7 bit in registers TACS0 to TACS3 is set to 0 (TCK0, TCK1 enabled).
Figure 15.24 TBiMR Register in Pulse Period and Pulse Width Measurement Mode
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
15. Timers
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(NOTE 1)
(NOTE 2)
(NOTE 1)
Timing at which counter
reaches 0000h
“1”
TBiS bit
“0”
IR bit in TBiIC register
“1”
“0”
Set to 0 upon accepting an interrupt request or by writing in program
MR3 bit in TBiMR register
“1”
“0”
Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are assigned to bits 5
to 7 in the TABSR register.
i = 0 to 5
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where bits MR1 and MR0 in the TBiMR register are 00b (measure the interval from
falling edge to falling edge of the measurement pulse).
Figure 15.25 Operation Timing when Measuring a Pulse Period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate
value)
counter
(NOTE 1)
Transfer
(measured
value)
(NOTE 1)
Transfer
(measured
value)
(NOTE 1)
Transfer
(measured
value)
(NOTE 1)
(NOTE 2)
Timing at which counter
reaches 0000h
“1”
TBiS bit
“0”
IR bit in TBiIC register
“1”
“0”
MR3 bit in TBiMR register
“1”
Set to 0 upon accepting an interrupt request or by writing in program
“0”
Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are assigned to bits 5
to 7 in the TABSR register.
i = 0 to 5
NOTES :
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where bits MR1 and MR0 in the TBiMR register are 10b (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 15.26 Operation Timing when Measuring a Pulse Width
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
16. Three-Phase Motor Control Timer Function
Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 16.1 lists the
Three-phase Motor Control Timer Functions Specifications. Figure 16.1 shows the Three-phase Motor Control Timer Functions Block Diagram. Also, the related registers are shown on Figures 16.2 to 16.7.
Table 16.1
Three-phase Motor Control Timer Functions Specifications
Item
Three-Phase Waveform
Output Pin
Forced Cutoff Input (1)
Used Timers
Specification
Six pins (U, U, V, V, W, W)
Input “L” to the SD pin
Timer A4, A1, A2 (used in one-shot timer mode)
Timer A4: U- and U-phase waveform control
Timer A1: V- and V-phase waveform control
Timer A2: W- and W-phase waveform control
Timer B2 (used in timer mode)
Carrier wave cycle control
Dead time timer (3 eight-bit timers and shared reload register)
Dead time control
Output Waveform
Triangular wave modulation, sawtooth wave modulation
• Enable to output “H” or “L” for one cycle
• Enable to set positive-phase level and negative-phase level independently
Triangular wave modulation : count source x (m + 1) x 2
Carrier Wave Cycle
Sawtooth wave modulation : count source x (m + 1)
m: setting value of the TB2 register, 0000h to FFFFh
Count source: f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S,
fC32
Three-Phase PWM Output Triangular wave modulation: count source x n x 2
Width
Sawtooth wave modulation: count source x n
n: setting value of registers TA4, TA1, and TA2 (of registers TA4, TA41, TA1,
TA11, TA2, and TA21 when setting the INV11 bit to 1), 0001h to FFFFh
Count source: f1TIMAB, f2TIMAB, f8TIMAB, f32TIMAB, f64TIMAB, fOCO-S,
fC32
Dead Time
Count source x p, or no dead time
p: setting value of the DTT register, 01h to FFh
Count source: f1TIMAB, f2TIMAB, f1TIMAB divided by 2, f2TIMAB divided by
2
Active Level
Enable to select “H” or “L”
Positive and NegativePositive-and negative-phases concurrent active disable function
Phase Concurrent Active
Positive-and negative-phases concurrent active detect function
Disable Function
Interrupt Frequency
Timer B2 interrupt is generated every q times
q: carrier wave cycle-to-cycle basis, 1 to 15
NOTES:
1. Forced cutoff with SD input is effective when the IVPCR1 bit in the TB2SC register is set to 1 (threephase output forcible cutoff by SD input enabled). If an “L” signal is applied to the SD pin when the
IVPCR1 bit is 1, the related pins go to a high-impedance state regardless of which functions of those
pins are being used.
2. Related pins: P7_2/CLK2/TA1OUT/V, P7_3/CTS2/RTS2/TA1IN/V, P7_4/TA2OUT/W,
P7_5/TA2IN/W, P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
INV00 to INV07 : bits in the INVC0 register
INV10 to INV15 : bits in the INVC1 register
DUi, DUBi
: bits in the IDBi register (i = 0,1)
TA1S to TA4S : bits in the TABSR register
PWCOM
: bits in the TB2SC register
ICTB2 register
1
ICTB2 counter
n = 1 to 15
0
PWCON
Timer B2 underflow
f1 or f2
1/2
Timer B2
INV07
(Timer mode)
Start trigger signal for Timers A1, A2, and A4
Reload
Reload
Trigger
Timer A4 counter
Timer A4
one-shot
pulse
(One-shot timer mode)
TQ
INV11
When setting the TA4S bit to 0,
signal is set to 0.
TA1 register
TA11 register
Reload
Trigger
Dead time timer
n = 1 to 255
INV11
DU1
bit
DU0
bit
DQ
T
DQ
T
DUB1
bit
DUB0
bit
DQ
T
DQ
T
U-phase
output signal
U-phase
output signal
V-phase
output signall
V-phase output
control circuit
V-phase
output signal
When setting the TA1S bit to 0, signal is set to 0.
TA2 register
TA21 register
Reload
Trigger
Timer A2 oneshot pulse
Timer A2 counter
TQ
Trigger
Timer A2
one-shot
pulse
(One-shot timer mode)
INV11
DQ
T
Inverse
control
U
Inverse
control
U
Inverse
control
V
Inverse
control
V
Inverse
control
W
Inverse
control
W
When setting the TA2S bit to 0,
signal is set to 0.
Three-phase
output
shift register
(U phase)
DQ
T
DQ
T
DQ
T
Trigger
INV06
Reload
Selector
INV14
Dead Time Timer
n = 1 to 255
Trigger
Timer A1
one-shot
pulse
(One-shot timer mode)
INV02
Trigger
INV06
Timer A4
control signal
Timer A1 counter
TQ
INV13
Reload
Selector
R
U-phase output
control circuit
Timer A4
control signal
Selector
RESET
Timer B2
NMI
Interrupt
INV05
request bit
T
Trigger
INV06
Trigger
TA41 register
Write signal to INV03 bit
Reload register
n = 1 to 255
Transfer trigger (1)
TA4 register
INV03
DQ
INV04
0
1
INV12
Write signal to
Timer B2
INV10
INV03 bit
Circuit to set interrupt
generation frequency
INV01
INV11
INV00
Reload control signal for Timer A1
Value to be written to
n = 1 to 15
W-phase output
control circuit
Dead Time Timer
n = 1 to 255
W-phase
output signal
W-phase
output signal
DQ
T
DQ
T
Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram.
NOTE:
1. Transfer trigger is generated only when registers IDB0 and IDB1 are set and the first timer B2 underflows, if the INV06
bit is set to 0 (triangular wave modulation).
Figure 16.1
Three-phase Motor Control Timer Functions Block Diagram
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 0 (1)
Symbol
INVC0
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Bit Symbol
Function
INV00
Interrupt enable output
polarity select bit
INV01
Interrupt enable output
specification bit (2)
INV02
Mode select bit
INV03
Output control bit (6)
INV04
INV05
After Reset
00h
Address
0308h
(4)
Positive-and negativephases concurrent active
disable function bit
Positive-and negativephases concurrent active
output detect flag
RW
0 : The ICTB2 counter is decremented by one on the
rising edge of Timer A1 reload control signal
1 : The ICTB2 counter is decremented by one on the
falling edge of Timer A1 reload control signal (3)
0 : ICTB2 counter is decremented by one when
Timer B2 underflows
1 : Selected by the INV00 bit (3)
RW
RW
0 : No three-phase control timer functions
1 : Three-phase control timer function (5)
RW
0 : Disables three-phase control timer output (5)
1 : Enables three-phase control timer output
RW
0 : Enables concurrent active output
1 : Disables concurrent active output
RW
0 : Not detected
1 : Detected (7)
RW
INV06
Modulation mode
select bit (8)
0 : Triangular wave modulation mode
1 : Sawtooth wave modulation mode (9)
RW
INV07
Software trigger select bit
Transfer trigger is generated when the INV07 bit
is set to 1. Trigger to the dead time timer is also
generated when setting the INV06 bit to 1. Read
as 0.
RW
NOTES :
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enabled). Rewrite bits INV00
to INV02 and INV06 when Timers A1, A2, A4 and B2 stop.
2. Set the INV01 bit to 1 after setting the ICTB2 register
3. Bits INV00 and INV01 are enabled only when the INV11 bit is set to 1 (three-phase mode 1). The ICTB2
counter is decremented by one every time Timer B2 underflows, regardless of INV00 and INV01 bit settings,
when the INV11 bit is set to 0 (three-phase mode). When setting the INV01 bit to 1, set Timer A1 count start
flag to 1 before the first Timer B2 underflow. When the INV00 bit is set to 1, the first interrupt is generated
when Timer B2 underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are
generated every n times Timer B2 underflows.
4. Set the INV02 bit to 1 to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2
counter.
5. When the INVC03 bit is set to 1, the pins applied to U/V/W output three-phase PWM. Pins U, U, V, V, W and
W, including pins shared with other output functions, are all placed in high-impedance states when the
following conditions are all met.
• The INV02 bit is set to 1 (three-phase motor control timer function)
• The INV03 bit is set to 0 (three-phase motor control timer output disabled)
• Direction registers of each port are set to 0 (input mode)
6. The INV03 bit is set to 0 when the followings conditions are all met.
• Reset
• A concurrent active state occurs while the INV04 bit is set to 1
• The INV03 bit is set to 0 by program
• A signal applied to the SD pin changes “H” to “L”
When both bits INVC04 and INVC05 are set to 1, the INVC03 bit is set to 0.
7. The INV05 bit can not be set to 1 by program. Set the INV04 bit to 0 as well when setting the INV05 bit to 0.
8. The following table describes how the INV06 bit works.
Item
Mode
INV06 = 0
Triangular wave modulation mode
INV06 = 1
Sawtooth wave modulation mode
Timing to transfer from registers Transferred once by generating a
Transferred every time a transfer
IDB0 and IDB1 to three-phase transfer trigger after setting registers trigger is generated
output shift register
IDB0 and IDB1
Timing to trigger the dead time
timer when the INV16 bit = 0
On the falling edge of a one-shot
pulse of the timer A1, A2, or A4
On the falling edge of a one-shot pulse of the
timer A1, A2, or A4, and transfer a trigger
INV13 bit
Enabled when the INV11 bit = 1 and
Disabled
the INV06 bit = 0
Transfer trigger : Timer B2 underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
9. When the INV06 bit is set to 1, set the INV11 bit to 0 (three-phase mode 0) and the PWCON bit in the TB2SC
register to 0 (reload Timer B2 with Timer B2 underflow).
Figure 16.2
INVC0 Register
REJ09B0392-0064 Rev.0.64
Page 167 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 1 (1)
Symbol
INVC1
b7 b6 b5 b4 b3 b2 b1 b0
0
After Reset
00h
Address
0309h
Bit Name
Bit Symbol
Function
RW
INV10
Timer A1, A2, and A4 start
trigger select bit
0 : Timer B2 underflow
1 : Timer B2 underflow and write to Timer
B2
RW
INV11
Timer A1-1, A2-1 and A4-1
control bit (2)
0 : Three-phase mode 0 (3)
1 : Three-phase mode 1
RW
INV12
Dead time timer count
source select bit
0 : f1TIMAB or f2TIMAB
1 : f1TIMAB divided by 2
or f2TIMAB divided by 2
RW
INV13
Carrier wave detect bit (4)
0 : Timer A1 reload control signal is 0
1 : Timer A1 reload control signal is 1
RO
INV14
Output polarity control bit
0 : Active “L” of an output waveform
1 : Active “H” of an output waveform
RW
INV15
Dead time disable bit
0 : Dead time enabled
1 : Dead time disabled
RW
INV16
Dead time timer trigger
select bit (5)
0 : Falling edge of a one-shot pulse of Timer A1,
A2, and A4
1 : Rising edge of the three-phase output shift
register (U-, V-, W-phase)
RW
Reserved bit
Set to 0
RW
—
(b7)
NOTES :
1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enabled). Rewrite while
the timers A1, A2, A4, and B2 stop.
2. The following table lists how the INV11 bit works.
Item
INV11 = 0
INV11 = 1
Mode
Three-phase mode 0
Three-phase mode 1
Registers TA11, TA21, and TA41
Not used
Used
Bits INV00 and INV01 in the INVC0 Disabled.
register
The ICTB2 counter is decremented
whenever Timer B2 underflows
Enabled
INV13 bit
Enabled when INV11 = 1 and INV06 = 0
Disabled
3. When the INV06 bit is set to 1 (sawtooth wave modulation mode), set the INV11 bit to 0 (three-phase mode 0).
Also, when the INV11 bit is set to 0, set the PWCON bit in the TB2SC register to 0 (timer B2 is reloaded when
Timer B2 underflows).
4. The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11
bit to 1 (three-phase mode 1).
5. If the following conditions are all met, set the INV16 bit to 1 (rising edge of the three-phase output shift register).
• The INV15 bit is set to 0 (dead time timer enabled)
• The Dij bit and DiBj bit always have different values when the INV03 bit is set to 1 (the positive-phase and
negative-phase always output opposite level signals) (i = U, V or W, j = 0, 1).
If above conditions are not met, set the INV16 bit to 0 (dead time timer is triggered on the falling edge of a oneshot pulse of timers).
Figure 16.3
INVC1 Register
REJ09B0392-0064 Rev.0.64
Page 168 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Three-Phase Output Buffer Register i (1) (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0
IDB1
Address
030Ah
030Bh
After Reset
XX111111b
XX111111b
Bit Name
Bit Symbol
Function
RW
Write output level
0 : Active level
1 : Inactive level
DUi
U-phase output buffer i
DUBi
U-phase output buffer i
DVi
V-phase output buffer i
RW
DVBi
V-phase output buffer i
RW
DWi
W-phase output buffer i
RW
DWBi
W-phase output buffer i
RW
—
(b7-b6)
RW
When read, the value of the three-phase
shift register is read.
RW
No register bits. If necessary, set to 0. Read as undefined value
—
NOTE :
1. Values of registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer trigger.
After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal
first. Then the value written in the IDB1 register on the falling edge of Timers A1, A2, and A4 one-shot pulse
determines each phase output signal.
Dead Time Timer (1, 2)
b7
b0
Symbol
DTT
Address
030Ch
After Reset
Indeterminate
Function
If setting value is n, the timer stops when counting n times
a count source selected by the INV12 after start trigger
occurs. Positive or negative phase, which changes from
inactive level to active level, shifts when the dead time
timer stops.
Setting Range
RW
1 to 255
WO
NOTES :
1. Use the MOV instruction to set the DTT register.
2. The DTT register is enabled when the INV15 bit in the INVC1 register is set to 0 (dead time enabled). No
dead time can be set when the INV15 bit is set to 1 (dead time disabled). The INV06 bit in the INVC0 register
determines start trigger of the DTT register.
Timer B2 Interrupt Generation Frequency Set Counter
b7
b0
Symbol
Address
ICTB2
030Dh
(1, 2, 3)
After Reset
Indeterminate
Function
Setting Range
RW
When the INV01 bit is set to 0 (the ICTB2 counter increments
whenever Timer B2 underflows) and the setting value is n,
Timer B2 interrupt is generated every nth time Timer B2
underflow occurs.
When the INV01 bit is set to 1 (the INV00 bit selects count
timing of the ICTB2 counter) and setting value is n, Timer B2
interrupt is generated every nth time Timer B2 underflow
meeting the condition selected in the INV00 bit occurs.
1 to 15
WO
No register bits. If necessary, set to 0
—
NOTES :
1. Use the MOV instruction to set the ICTB2 register.
2. If the INV01 bit in the INVCO register is set to 1, set the ICTB2 register when the TB2S bit in the TABSR
register is set to 0 (Timer B2 counter stopped).
If the INV01 bit is set to 0 and the TB2S bit to 1 (Timer B2 counter start), do not set the ICTB2 register when
Timer B2 underflows.
3. If the INV00 bit is set to 1, the first interrupt is generated when Timer B2 underflows n-1 times, n being the
value set in the ICTB2 counter. Subsequent interrupts are generated every n times Timer B2 underflows.
Figure 16.4
Registers IDB0, IDB1, DTT, and ICTB2
REJ09B0392-0064 Rev.0.64
Page 169 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i = 1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 1 0
Symbol
TA1MR
TA2MR
TA4MR
Address
0337h
0338h
033Ah
After Reset
00h
00h
00h
Bit Name
Bit symbol
Function
RW
TMOD0
RW
Operation mode select bit
Set to 10b (one-shot timer mode) with the
three-phase motor control timer function
TMOD1
RW
MR0
Pulse output function select
bit
Set to 0 with the three-phase motor control
timer function
RW
MR1
External trigger select bit
Set to 0 with the three-phase motor control
timer function
RW
MR2
Trigger select bit
Set to 1 (selected by the TRGSR register)
with the three-phase motor control timer
function
RW
MR3
Set to 0 with the three-phase motor control timer function
b7
TCK0
Count source select bit (2)
TCK1
0
0
1
1
RW
b6
0 : f1TIMAB or f2TIMAB
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
RW
(1)
RW
NOTES :
1. Selected by the PCLK0 bit in the PCLKR register.
2. Valid when bits TCS3 and TCS7 in registers TACS0 to TACS2 are set to 0. Selected by bits TCS2 to TCS0 or
TCS6 to TCS4 in registers TACS0 to TACS2 when bits TCS3 and TCS7 are set to 1. (Refer to Figure 15.8
Registers TACS0 and TACS and Figure 15.9 TACS2 Register ).
Timer B2 Special Mode Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TB2SC
033Eh
XXXXXX00b
Bit Name
Bit Symbol
Function
RW
PWCON
Timer B2 reload timing
switch bit
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
occurrences (2)
RW
IVPCR1
Three-phase output port SD
control bit 1 (4)
0 : Three-phase output forcible cutoff by
SD input (high-impedance) disabled
1 : Three-phase output forcible cutoff by
SD input (high-impedance) enabled (3)
RW
—
(b7-b2)
No register bits. If necessary, set to 0. Read as 0
—
NOTES :
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).
2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (sawtooth wave modulation mode), set the
PWCON bit to 0 (Timer B2 underflow).
3. Make sure to set the PD8_5 bit to 0 (input) when setting the IVPCR1 bit to 1 (three-phase output forcible cutoff
by SD input enabled ).
4. Related pins are U(P8_0), U(P8_1), V(P7_2), V(P7_3), W(P7_4), and W(P7_5). If a low-level signal is applied to
the P8_5/NMI/SD pin, three-phase motor control timer output is disabled (INV03 = 0). Then, the target pins go
to a high-impedance state regardless of which functions of those pins are being used. After forced interrupt
(cutoff), input “H” to the P8_5/NMI/SD pin and set the IVPCR1 bit to 0 to cancel the forced cutoff.
Figure 16.5
Registers TA1, TA2, TA4, TA11, TA21, TA41, and TB2SC
REJ09B0392-0064 Rev.0.64
Page 170 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Timer B2 Register (1)
(b15)
b7
(b8)
b0 b7
Symbol
TB2
b0
Address
0335h to 0334h
Function
If setting value is n, count source is divided by n+1.
Timers A1, A2 and A4 start every time an underflow occurs.
After Reset
Indeterminate
Setting Range
RW
0000h to FFFFh
RW
NOTE :
1. Read and write in 16-bit units.
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
0323h
Bit Name
Bit Symbol
TA1TGL
A1TGH
TA2TGL
TA2TGH
Function
Set to 01b (TB2 underflow) before using
a V-phase output control circuit
Timer A2 event / trigger
select bit
Set to 01b (TB2 underflow) before using
a W-phase output control circuit
b5
0
0
1
1
Timer A3 event / trigger
select bit
TA3TGH
TA4TGH
RW
Timer A1 event / trigger
select bit
TA3TGL
TA4TGL
After Reset
00h
Timer A4 event / trigger
select bit
RW
RW
RW
RW
b4
0 : Input on TA3IN is selected
1 : TB2 is selected (2)
0 : TA2 is selected (2)
1 : TA4 is selected (2)
(1)
RW
RW
RW
Set to 01b (TB2 underflow) before using
a U-phase output control circuit
RW
NOTES :
1. Set the corresponding port direction bit to 0 (input mode).
2. Overflow or underflow
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TABSR
0320h
00h
Bit Name
Bit Symbol
Figure 16.6
0 : Stop counting
1 : Start counting
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
RW
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
Registers TB2, TRGSR, and TABSR
REJ09B0392-0064 Rev.0.64
Page 171 of 373
Function
Oct 12, 2007
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i = 1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 1 0
After Reset
00h
00h
00h
Address
0337h
0338h
033Ah
Symbol
TA1MR
TA2MR
TA4MR
Bit Name
Bit symbol
Function
RW
TMOD0
RW
Operation mode select bit
Set to 10b (one-shot timer mode) with the
three-phase motor control timer function
TMOD1
RW
MR0
Pulse output function select
bit
Set to 0 with the three-phase motor control
timer function
RW
MR1
External trigger select bit
Set to 0 with the three-phase motor control
timer function
RW
MR2
Trigger select bit
Set to 1 (selected by the TRGSR register)
with the three-phase motor control timer
function
RW
MR3
Set to 0 with the three-phase motor control timer function
b7
TCK0
Count source select bit
(2)
TCK1
0
0
1
1
RW
b6
0 : f1TIMAB or f2TIMAB
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
RW
(1)
RW
NOTES :
1. Selected by the PCLK0 bit in the PCLKR register.
2. Valid when bits TCS3 and TCS7 in registers TACS0 to TACS2 are set to 0. Selected by bits TCS2 to TCS0 or
TCS6 to TCS4 in registers TACS0 to TACS2 when bits TCS3 and TCS7 are set to 1. (Refer to Figure 15.8
Registers TACS0 and TACS and Figure 15.9 TACS2 Register ).
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
033Dh
TB2MR
Bit Name
Bit Symbol
Function
TMOD0
Operation mode select bit
TMOD1
MR0
MR1
After Reset
00XX0000b
Set to 00b (timer mode) when using the
three-phase motor control timer function
Disabled when using the three-phase motor control timer function.
If necessary, set to 0.
Read as undefined value
RW
RW
RW
No register bit. If necessary, set to 0. Read as undefined value
—
MR3
When write in three-phase motor control timer function, set to 0.
Read as undefined value in three-phase motor control timer function
RO
b7
Count source select bit
TCK1
(2)
0
0
1
1
b6
0 : f1TIMAB or f2TIMAB (1)
1 : f8TIMAB
0 : f32TIMAB
1 : fC32
NOTES :
1. Selected by the PCLK0 bit in the PCLKR register.
2. Valid when the TCS3 bit in the TBCS1 register is set to 0. Selected by bits TCS2 to TCS0 in the TBCS1
register when the TCS3 bit in the TBCS1 register is set to 1 (Refer to Figure 15.21 TBCS1 Register).
Registers TA1MR, TA2MR, TA4MR, and TB2MR
REJ09B0392-0064 Rev.0.64
Page 172 of 373
RW
—
(b4)
TCK0
Figure 16.7
RW
Oct 12, 2007
RW
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1.
When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1, and A2 are used to
control three-phase PWM outputs (U, U, V, V, W, and W). The dead time is controlled by a dedicated dead
time timer. Figure 16.8 shows an Example of Triangular Wave Modulation Operation and Figure 16.9 shows
an Example of Sawtooth Wave Modulation Operation.
Triangular Waveform as a Carrier Wave
Carrier wave
Signal wave
TB2S bit
in TABSR register
Timer B2
Timer A1
reload control signal (1)
Timer A4
start trigger signal (1)
TA4 register (2)
m
n
p
q
r
TA4-1 register (2)
m
n
p
q
r
Reload register (2)
m
m
m
Timer A4
one-shot pulse (1)
n
m
n
n
n
p
p
p
n
q
q
p
q
q
Rewrite registers IDB0 and IDB1
U-phase output signal (1)
U-phase output signal
INV14 = 0
(“L” active)
Rewritten value is
reflected here
(1)
U-phase
U-phase
Dead time
INV14 = 1
(“H” active)
U-phase
Dead time
U-phase
INV00,INV01 : bits in the INVC0 register
INV11, INV14: bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 16.1 Three-phase Motor Control Timer Functions Block Diagram.
2. Applies only when the INV11 bit is set to 1 (three-phase mode).
The above applies when INVC0 = 00XX11XXb (X varies depending on each system) and INVC1 = 010XXXXb.
The followings are examples of PWM output change.
(a) When INV11 = 1 (three-phase mode 1)
- INV01 = 0 and ICTB2 = 2h (Timer B2 interrupt is
generated with every second Timer B2 underflow) or
INV01 = 1, INV00 = 1, and ICTB2 = 1h (Timer B2 interrupt
is generated on the falling edge of Timer A reload control
signal)
- Default value of the timer: TA41 = m, TA4 = m
Registers TA4 and TA41 are changed whenever
Timer B2 interrupt is generated.
First time: TA41 = n, TA4 = n.
Second time: TA41 = p, TA4 = p.
- Default value of registers IDB0 and IDB1
DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1,
DUB1 = 0 by the third Timer B2 interrupt.
Figure 16.8
(b) When INV11 = 0 (three-phase mode 0)
- INV01 = 0, ICTB2 = 1h (Timer B2 interrupt is generated
whenever Timer B2 underflows)
- Default value of the timer: TA4 = m
The TA4 register is changed whenever Timer B2
interrupt is generated.
First time: TA4 = m Second time: TA4 = n.
Third time: TA4 = n Fourth time: TA = p.
Fifth time: TA4=p.
- Default value of registers IDB0 and IDB1:
DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1,
DUB1 = 0 by the sixth Timer B2 interrupt.
Example of Triangular Wave Modulation Operation
REJ09B0392-0064 Rev.0.64
Page 173 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
16. Three-Phase Motor Control Timer Function
Sawtooth Waveform as a Carrier Wave
Carrier Wave
Signal Wave
Timer B2
Timer A4 start trigger signal
(1)
Timer A4 one-shot pulse
(1)
Rewrite registers
IDB0 and IDB1
Rewritten value is reflected here
U-phase output signal
(1)
U-phase output signal
(1)
INV14 = 0
(“L” active)
U-phase
Dead time
U-phase
INV14 = 1
(“H” active)
U-phase
Dead time
U-phase
INV14: bit in the INVC1 register
NOTE:
1. See Figure 16.1 Three-Phase Motor Control Timer Functions Block Diagram.
The above applies when INVC0 = 01XX110Xb (X varies depending on each system) and INVC1 = 010XXX00b
The following is an example of PWM output change.
- Default value of registers IDB0 and IDB1: DU0 = 0, DUB0 = 1, DU1 = 1, DUB1 = 1
They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 1 by the timer B2 interrupt.
Figure 16.9
Example of Sawtooth Wave Modulation Operation
REJ09B0392-0064 Rev.0.64
Page 174 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
17. Serial Interface
Serial interfaces consist of eight channels: UART0 to UART2, UART5 to UART7, SI/O3, and SI/O4.
17.1
UARTi (i = 0 to 2, 5 to 7)
Each UARTi has an exclusive timer to generate a transfer clock, so it operates independently of each
other.
Figures 17.1 to 17.3 show the block diagrams of UARTi. Figure 17.4 shows the UARTi Transmit / Receive
Unit.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode)
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode)
• Special mode 4 (SIM mode) : UART2
Figures 17.5 to 17.11 show the UARTi-related registers.
Refer to tables for each mode for register setting.
UART6 and UART7 cannot be used in memory expansion mode or microprocessor mode.
REJ09B0392-0064 Rev.0.64
Page 175 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
1/2
f1
f2SIO
0
f1SIO
1
PCLK1
f1SIO or f2SIO
1/8
f8SIO
1/4
RXD polarity
switching circuit
RXD0
1/16
Clock source selection
CLK1 to CLK0 CKDIR
f1SIO or
00
Internal
f2SIO
01
0
f8SIO
10
f32SIO
1
001
1 / (n + 1)
Transmission
control circuit
010, 100, 101, 110
Clock sync type
Receive
clock
TXD0
TXD
polarity
switching
circuit
TXD1
Transmit/
receive
unit
Transmit
clock
001
Clock synchronous type
(when internal clock is selected)
0
CTS / RTS disabled
CTS / RTS selected
RTS0
1
CRS 0
0
RCSP
CTS / RTS disabled
0
1
CTS0 from UART1
CTS0
1 CRD
VSS
n: values set to the U0BRG register
PCLK1
: bit in the PCLKR register
SMD2 to SMD0, CKDIR
: bits in the U0MR register
CLK1 to CLK0, CKPOL, CRD, CRS : bits in the U0C0 register
RCSP
: bit in the UCON register
UART0 Block Diagram
1/2
f1
f2SIO
0
f1SIO
1
PCLK1
f1SIO or f2SIO
1/8
f8SIO
1/4
RXD polarity
switching circuit
RXD1
1/16
Clock source selection
CLK1 to CLK0 CKDIR
f1SIO or
00
Internal
f2SIO
01
0
f8SIO
10
f32SIO
1
U1BRG
register
1/16
UART transmission
010, 100, 101, 110
External
CLK1
CLKMD0
Receive
clock
Transmit
clock
Clock synchronous type
(when internal clock is selected)
0
Clock synchronous type
(when external clock is selected)
0
Transmission
control circuit
Clock sync type
001
CKPOL
CLK
polarity
reversing
circuit
Reception
control circuit
Clock sync type
001
1 / (n + 1)
f32SIO
UART reception SMD2 to SMD0
010, 100, 101, 110
1/2
Clock synchronous type
(when internal clock is selected)
1
CKDIR
1
CTS1 / RTS1/
CTS0 / CLKS1
Clock output
pin select
1
CTS / RTS selected
CTS / RTS disabled
CRS 1
CLKMD1
RTS1
0
0
0
CTS / RTS disabled
0
1
VSS
n: Values set to the U1BRG register
Figure 17.2
TXD
polarity
switching
circuit
1
Clock synchronous type
(when external clock is selected) CKDIR
Clock synchronous type
(when internal clock is selected)
CKPOL
Figure 17.1
UART transmission
1/16
External
CLK
polarity
reversing
circuit
CTS0 /
RTS0
Reception
control
circuit
Clock sync type
U0BRG
register
1/2
CLK0
UART reception SMD2 to SMD0
010, 100, 101, 110
f32SIO
1 CRD
to CTS0 in UART0
RCSP
PCLK1
: bit in the PCLKR register
SMD2 to SMD0, CKDIR
: bits in the U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS : bits in the U1C0 register
CLKMD0, CLKMD1, RCSP
: bits in the UCON register
UART1 Block Diagram
REJ09B0392-0064 Rev.0.64
Page 176 of 373
CTS1
Oct 12, 2007
Transmit/
receive
unit
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
1/2
f1
f2SIO
0
f1SIO
1
PCLK1
f1SIO or f2SIO
1/8
f8SIO
1/4
RXD polarity
switching circuit
RXDi
1/16
Clock source selection
CLK1 to CLK0
CKDIR
f1SIO or
00
Internal
f2SIO
01
0
f8SIO
10
f32SIO
1
001
1 / (n + 1)
1/16
External
Reception
control circuit
UART transmission
010, 100, 101, 110
Clock sync type
001
Transmission
control circuit
CLK
polarity
reversing
circuit
CTS / RTS selected
Transmit
clock
Clock synchronous type
(when internal clock is selected)
0
CTS / RTS disabled
RTSi
1
CRS 0
CTS / RTS disabled
0
CTSi
1
VSS
n: values set to the UiBRG register
i = 2, 5 to 7
CRD
PCLK1
: bit in the PCLKR register
SMD2 to SMD0, CKDIR
: bits in the U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS : bits in the U2C0 register
NOTE :
1. UART2 is an N-channel open-drain output. CMOS output cannot be set.
Figure 17.3
Receive
clock
1
Clock synchronous type
CKDIR
Clock synchronous type (when external clock is selected)
(when internal clock is selected)
CKPOL
CTSi /
RTSi
Clock sync type
UiBRG
register
1/2
CLKi
UART reception SMD2 to SMD0
010, 100, 101, 110
f32SIO
UART2, and UART5 to UART7 Block Diagram
REJ09B0392-0064 Rev.0.64
Page 177 of 373
Oct 12, 2007
Transmit/
receive
unit
TXD
polarity
switching
circuit (1)
TXDi
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
IOPOL
RXDi
0
RXD data
reverse circuit
1
No reverse
Reverse
PRYE
STPS
1SP
0
PAR
disabled
I2C
Clock sync
type
0
SP
SP
Clock sync type
UART
(7 bits)
UART
(8 bits)
UARTi receive register
PAR
1
1
1
2SP
1
I2C
PAR enabled UART
SMD2 to SMD0
0
UART (7 bits)
0
0
0
0
0
0
0
0
UART
(9 bits)
0
I2C
1
clock sync type
UART
(8 bits)
UART
(9 bits)
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB
register
Logic reverse circuit + MSB / LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB / LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiTB
register
UART
(8 bits)
UART
(9 bits)
I2C
PRYE
STPS
2SP
1
SP
PAR enabled
1
0
1SP
0
UART
UART
(9 bits)
1
PAR
SP
SMD2 to SMD0
PAR
disabled
0
I2C
clock sync
type
SP : stop bit
PAR: parity bit
I2C
clock sync type
1
1
0
0
UART
(7 bits)
UART
(8 bits)
Clock sync type
UART (7 bits)
UARTi transmit register
Error signal output disabled
0
UiERE 1
i = 0 to 2, 5 to 7
Error signal output enabled
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : bits in the UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS
: bits in the UiC0 register
UiERE
: bit in the UiC1 register
Figure 17.4
UARTi Transmit / Receive Unit
REJ09B0392-0064 Rev.0.64
Page 178 of 373
Error signal
output
circuit
Oct 12, 2007
IOPOL
0
1
No reverse
Reverse
TXD data
reverse
circuit
TXDi
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
UARTi Transmit Buffer Register (i = 0 to 2, 5 to 7)
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
U2TB
U5TB
U6TB
U7TB
b0
(1)
Address
024Bh to 024Ah
025Bh to 025Ah
026Bh to 026Ah
028Bh to 028Ah
029Bh to 029Ah
02ABh to 02AAh
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
RW
Transmit data
WO
No register bits. If necessary, set to 0. Read as undefined value
—
NOTE :
1. Use MOV instruction to write to this register.
UARTi Receive Buffer Register (i = 0 to 2, 5 to 7)
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
U2RB
U5RB
U6RB
U7RB
b0
Address
024Fh to 024Eh
025Fh to 025Eh
026Fh to 026Eh
028Fh to 028Eh
029Fh to 029Eh
02AFh to 02AEh
Bit Name
Bit Symbol
—
(b7-b0)
—
(b8)
—
(b10-b9)
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
RW
Receive data (D7 to D0)
RO
Receive data (D8)
RO
No register bits. If necessary, set to 0. Read as undefined value
—
ABT
Arbitration lost detect flag (2)
0 : Not detected
1 : Detected
RW
OER
Overrun error flag (1)
0 : No overrun error
1 : Overrun error found
RO
FER
Framing error flag (1, 3)
0 : No framing error
1 : Framing error found
RO
PER
Parity error flag (1,3)
0 : No parity error
1 : Parity error found
RO
SUM
Error sum flag (1, 3)
0 : No error
1 : Error found
RO
NOTES :
1. When bits SMD2 to SMD0 in the UiMR register = 000b (serial interface disabled) or the RE bit in the UiC1 register
= 0 (reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The SUM bit is set to 0 (no
error) when all of bits PER, FER, and OER = 0 (no error). Bits PER and FER are set to 0 by reading the lower
byte of the UiRB register.
2. The ABT bit is set to 0 by writing 0 in a program. (Writing a 1 has no effect.)
3. These error flags are disabled when bits SMD2 to SMD0 are set to 001b (clock synchronous serial I/O mode) or
to 010b (I2C mode). Read as undefined values.
Figure 17.5
Registers U0TB to U2TB, U5TB to U7TB, U0RB to U2RB, and U5RB to U7RB
REJ09B0392-0064 Rev.0.64
Page 179 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
UARTi Bit Rate Register (i = 0 to 2, 5 to 7)
b0
b7
(1, 2, 3)
After Reset
Indeterminate
Indeterminate
Address
Symbol
U0BRG, U1BRG, U2BRG
U5BRG, U6BRG, U7BRG
0249h, 0259h, 0269h
0289h, 0299h, 02A9h
Function
Setting Range
RW
00h to FFh
WO
If set value = n, UiBRG divides the count source by n + 1
NOTES :
1. Write to this register while serial interface is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
3. Write to this register after setting bits CLK1 to CLK0 in the UiC0 register.
UARTi Transmit / Receive Mode Register (i = 0 to 2, 5 to 7)
Symbol
U0MR, U1MR, U2MR
U5MR, U6MR, U7MR
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
SMD0
SMD1
SMD2
Address
0248h, 0258h, 0268h
0288h, 0298h, 02A8h
Bit Name
After Reset
00h
00h
Function
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C mode (3)
Serial I/O mode select bit 1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set except above
RW
RW
RW
RW
CKDIR
Internal / external clock
select bit
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
RW
PRY
Odd / even parity select
bit
Valid when PRYE = 1
0 : Odd parity
1 : Even parity
RW
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
IOPOL
TXD, RXD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
RW
(1)
RW
NOTE :
1. Set the corresponding port direction bit for each CLKi pin to 0 (input mode).
2. To receive data, set the corresponding port direction bit for each RXDi pin to 0 (input mode).
3. Set the corresponding port direction bit for pins SCL and SDA to 0 (input mode).
Figure 17.6
Registers U0BRG to U2BRG, U5BRG to U7BRG, U0MR to U2MR, and U5MR to U7MR
REJ09B0392-0064 Rev.0.64
Page 180 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
UARTi Transmit / Receive Control Register 0 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C0, U1C0, U2C0
U5C0, U6C0, U7C0
Address
024Ch, 025Ch, 026Ch
028Ch, 029Ch, 02ACh
Bit Name
Bit Symbol
b1
UiBRG count source select
bit (6)
CLK1
TXEPT
CRD
NCH
RW
Function
CLK0
CRS
After Reset
00001000b
00001000b
0
0
1
1
b0
0 : f1SIO or f2SIO is selected
1 : f8SIO is selected
0 : f32SIO is selected
1 : Do not set to this value
(5)
RW
RW
Valid when CRD = 0
0 : CTS function selected (1)
1 : RTS function selected
RW
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
RO
CTS / RTS disable bit
0 : CTS / RTS function enabled
1 : CTS / RTS function disabled
(P6_0, P6_4, P7_3, P8_1, P1_0, and
P4_4 can be used as I/O ports)
RW
0 : Pins TXDi / SDAi and SCLi are CMOS
output
1 : Pins TXDi / SDAi and SCLi are Nchannel open-drain output
RW
RW
RW
CTS / RTS function select bit
(4)
Data output select bit
(2)
CKPOL
CLK polarity select bit
0 : Transmit data is output at the falling
edge of transfer clock and receive data
is input at the rising edge
1 : Transmit data is output at the rising
edge of transfer clock and receive data
is input at the falling edge
UFORM
Transfer format select bit (3)
0 : LSB first
1 : MSB first
NOTES :
1. Set the corresponding port direction bit for each CTSi pin to 0 (input mode).
2. TXD2 / SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. No NCH bit in
the U2C0 register is assigned. If necessary, set to 0.
3. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous
serial I/O mode), or 101b (UART mode, 8-bit transfer data).
Set this bit to 1 when bits SMD2 to SMD0 are set to 010b (I 2C mode), and to 0 when bits SMD2 to SMD0 are
set to 100b (UART mode, 7-bit transfer data) or 110b (UART mode, 9-bit transfer data).
4. CTS1 / RTS1 can be used when the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the RCSP
bit in the UCON register = 0 (CTS0 / RTS0 not separated).
5. Selected by the PCLK1 bit in the PCLKR register.
6. When changing bits CLK1 and CLK0, set the UiBRG register.
Figure 17.7
Registers U0C0 to U2C0 and U5C0 to U7C0
REJ09B0392-0064 Rev.0.64
Page 181 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
UARTi Transmit / Receive Control Register 1 (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0C1, U1C1
024Dh, 025Dh
After Reset
00XX0010b
Bit Name
Function
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : Data present in UiRB register
1 : No data present in UiRB register
RO
Bit Symbol
—
(b5-b4)
No register bits. If necessary, set to 0. Read as undefined value
UiLCH
Data logic select bit (1)
0 : No reverse
1 : Reverse
RW
UiERE
Error signal output enable bit
0 : Output disabled
1 : Output enabled
RW
—
NOTE :
1. The UiLCH bit enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock sychronous serial I/
O mode), 100b (UART mode, 7-bit transfer data), or 101b (UART mode, 8-bit transfer data). Set this bit to 0
when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit transfer data).
UARTi Transmit / Receive Control Register 1 (i = 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
U2C1
U5C1, U6C1, U7C1
026Dh
028Dh, 029Dh, 02ADh
00000010b
00000010b
Bit Name
Function
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in UiRB register
1 : Data present in UiRB register
RO
UARTi transmit interrupt
source select bit
0 : UiTB register empty (TI = 1)
1 : Transmit completed (TXEPT = 1)
RW
UiRRM
UARTi continuous receive
mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
UiLCH
Data logic select bit (1)
0 : No reverse
1 : Reverse
RW
UiERE
Error signal output enable bit
0 : Output disabled
1 : Output enabled
RW
Bit symbol
UilRS
NOTE :
1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous
serial I/O mode), 100b (UART mode, 7-bit transfer data), or 101b (UART mode, 8-bit transfer data).
Set this bit to 0 when bits SMD2 to SMD0 are set to 010b (I 2C mode) or 110b (UART mode, 9-bit transfer data).
Figure 17.8
Registers U0C1 to U2C1 and U5C1 to U7C1
REJ09B0392-0064 Rev.0.64
Page 182 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
UART Transmit / Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
0250h
Bit Name
Bit symbol
After Reset
X0000000b
RW
Function
U0IRS
UART0 transmit interrupt
source select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U1IRS
UART1 transmit interrupt
source select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U0RRM
UART0 continuous receive
mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U1RRM
UART1 continuous receive
mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
CLKMD0
UART1CLK, CLKS select bit 0
CLKMD1
RCSP
—
(b7)
UART1CLK, CLKS select bit 1
(1)
Separate UART0
CTS / RTS bit
Valid when CLKMD1 = 1
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only from CLK1
1 : Transfer clock output from multiple-pin
output function selected
0 : CTS / RTS shared pin
1 : CTS / RTS separated (CTS0 supplied
from the P6_4 pin)
No register bit. If necessary, set to 0. Read as undefined value
RW
RW
RW
—
NOTE :
1. When using multiple transfer clock output pins, make sure the following conditions are met:
the CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0SMR, U1SMR, U2SMR
U5SMR, U6SMR, U7SMR
Address
0247h, 0257h, 0267h
0287h, 0297h, 02A7h
Bit Name
Bit Symbol
After Reset
X0000000b
X0000000b
Function
RW
IICM
I2C mode select bit
0 : Other than I2C mode
1 : I2C mode
RW
ABC
Arbitration lost detect flag
control bit
0 : Update per bit
1 : Update per byte
RW
BBS
Bus busy flag (1)
0 : Stop-condition detected
1 : Start-condition detected (busy)
RW
—
(b3)
Reserved bit
Set to 0
RW
Bus collision detect sampling 0 : Rising edge of transfer clock
clock select bit
1 : Underflow signal of Timer Aj (2)
RW
Auto clear function select bit 0 : No auto clear function
of transmit enable bit
1 : Auto clear at occurrence of bus collision
RW
SSS
Transmit start condition
select bit
RW
—
(b7)
No register bit. If necessary, set to 0. Read as undefined value
ABSCS
ACSE
0 : Not synchronized to RXDi
1 : Synchronized to RXDi (3)
—
NOTES :
1. The BBS bit is set to 0 by writing a 0 in a program (Writing a 1 has no effect).
2. Underflow signal of Timer A3 in UART0 and UART6, underflow signal of Timer A4 in UART1 and UART7,
and underflow signal of Timer A0 in UART2 and UART5
3. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXDi).
Figure 17.9
Registers UCON, U0SMR to U2SMR, and U5SMR to U7SMR
REJ09B0392-0064 Rev.0.64
Page 183 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
UARTi Special Mode Register 2 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR2, U1SMR2, U2SMR2
U5SMR2, U6SMR2, U7SMR2
Bit Name
Bit Symbol
After Reset
X0000000b
X0000000b
Address
0246h, 0256h, 0266h
0286h,0296h,02A6h
RW
Function
IICM2
I2C mode select bit 2
See Table 17.13 I2C Mode Functions
RW
CSC
Clock synchronization bit
0 : Disabled
1 : Enabled
RW
SWC
SCL wait output bit
0 : Disabled
1 : Enabled
RW
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
RW
STAC
UARTi initialization bit
0 : Disabled
1 : Enabled
RW
SWC2
SCL wait output bit 2
0: Transfer clock
1: “L” output
RW
SDHI
SDA output disable bit
0: Enabled
1: Disabled (high-impedance)
RW
—
(b7)
No register bit. If necessary, set to 0. Read as undefined value
—
UARTi Special Mode Register 3 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3, U1SMR3, U2SMR3
U5SMR3, U6SMR3, U7SMR3
Bit Name
Bit Symbol
—
(b0)
CKPH
—
(b2)
NODC
—
(b4)
After Reset
000X0X0Xb
000X0X0Xb
Function
No register bit. If necessary, set to 0. Read as undefined value
Clock phase set bit
0 : Without clock delay
1 : With clock delay
No register bit. If necessary, set to 0. Read as undefined value
Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
No register bit. If necessary, set to 0. Read as undefined value
DL0
DL1
Address
0245h, 0255h, 0265h
0285h, 0295h, 02A5h
SDAi digital delay
setup bit (1, 2)
DL2
b7 b6 b5
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
RW
—
RW
—
RW
—
RW
RW
RW
NOTES :
1. Bits DL2 to DL0 are used to generate a delay in SDAi output by digital means during I2C mode. In other
than I2C mode, set these bits to 000b (no delay).
2. The amount of delay varies with the load on pins SCLi and SDAi. Also, when using an external clock, the
amount of delay increases by about 100 ns.
Figure 17.10 Registers U0SMR2 to U2SMR2, U5SMR2 to U7SMR2, U0SMR3 to U2SMR3, and
U5SMR3 to U7SMR3
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M16C/64 Group
17. Serial Interface
UARTi Special Mode Register 4 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR4, U1SMR4, U2SMR4
U5SMR4, U6SMR4, U7SMR4
Bit Name
Bit Symbol
STAREQ
RSTAREQ
STPREQ
Address
0244h, 0254h, 0264h
0284h, 0294h, 02A4h
Start condition generate bit
Function
RW
(1)
0 : Clear
1 : Start
RW
Restart condition generate
bit (1)
0 : Clear
1 : Start
RW
Stop condition generate bit
0 : Clear
1 : Start
RW
0 : Start and stop conditions not output
1 : Start and stop conditions output
RW
(1)
STSPSEL SCL, SDA output select bit
ACKD
ACK data bit
0 : ACK
1 : NACK
RW
ACKC
ACK data output enable bit
0 : Serial interface data output
1 : ACK data output
RW
SCLHI
SCL output stop enable bit
0 : Disabled
1 : Enabled
RW
SWC9
SCL wait bit 3
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
RW
NOTE :
1. Set to 0 when each condition is generated.
Figure 17.11 Registers U0SMR4 to U2SMR4 and U5SMR4 to U7SMR4
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After Reset
00h
00h
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.1
17. Serial Interface
Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 17.1 lists
the Clock Synchronous Serial I/O Mode Specifications. Table 17.2 lists Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode.
Table 17.1
Clock Synchronous Serial I/O Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission, Reception
Control
Transmission Start Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
Transfer data length: 8 bits
• CKDIR bit in the UiMR register = 0 (internal clock): fj / (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of UiBRG register
• CKDIR bit = 1 (external clock) : input from CLKi pin
00h to FFh
Selectable from CTS function, RTS function or CTS / RTS function disable
Before transmission starts, satisfy the following requirements (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = “L”
Before reception starts, satisfy the following requirements (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present and dummy written in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit (3) = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending
data from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at completion of reception)
Overrun error (2)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input / output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending / receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit / receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
• Separate CTS / RTS pins (UART0)
CTS0 and RTS0 are input / output from separate pins
i = 0 to 2, 5 to 7
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge
of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1
(transmit data output at the rising edge and the receive data taken in at the falling edge of the
transfer clock), the external clock is in the low state.
2. If an overrun error occurs, the receive data of the UiRB register will be indeterminate. The IR bit in
the SiRIC register does not change to 1 (interrupt requested).
3. Bits U0IRS and U1IRS correspond to bits 0 and 1 in the UCON register respectively. Bits U2IRS,
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
U5IRS, U6IRS, and U7IRS are in registers U2C1, U5C1, U6C1, and U7C1 respectively.
Table 17.2
Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
UiTB
(3)
UiRB (3)
UiBRG
UiMR (3)
UiC0
UiC1
Bit
Function
0 to 7
Set transmission data
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
Reception data can be read
Overrun error flag
Set a bit rate
Set to 001b
Select the internal clock or external clock
Set to 0
Select the count source for the UiBRG register
Select either CTS or RTS to use functions
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TXDi pin output mode (2)
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to 1 to enable transmission / reception
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the source of UARTi transmit interrupt
CKPOL
UFORM
TE
TI
RE
RI
UiIRS (1)
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
UiRRM (1)
UiLCH
UiERE
0 to 7
0 to 7
0 to 2
NODC
4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
7
Set this bit to 1 to use continuous reception mode
Set this bit to 1 to use inverted data logic
Set to 0
Set to 0
Set to 0
Set to 0
Select clock output mode
Set to 0
Set to 0
Select the source of UART0 / UART1 transmit interrupt
Set this bit to 1 to use continuous reception mode
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to 1 to output UART1 transfer clock from two pins
Set this bit to 1 to accept as input the CTS0 signal of UART0 from the
P6_4 pin
Set to 0
i = 0 to 2, 5 to 7
NOTES:
1. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in
the UCON register.
2. The TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to 0.
3. Set bits not listed above to 0 when writing to the registers in clock synchronous serial I/O mode.
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M16C/64 Group
17. Serial Interface
Table 17.3 lists the functions of the input / output pins during clock synchronous serial I/O mode. Table
17.3 shows pin functions for the case where the multiple transfer clock output pin select function is not
selected. Table 17.4 lists the P6_4 Pin Functions during clock synchronous serial I/O mode.
Note that for a period from when UARTi operating mode is selected to when transfer starts, the TXDi pin
outputs “H” (If the N-channel open-drain output is selected, this pin is in high-impedance state).
Table 17.3
Pin Functions during Clock Synchronous Serial I/O Mode (Multiple Transfer Clock
Output Pin Function Not Selected)
Pin Name
Function
Method of Selection
TXDi
Serial data output
(Outputs dummy data when performing reception only)
RXDi
Serial data input
Set the port direction bit corresponding to the RXDi pin = 0
(can be used as an input port when performing transmission
only)
CLKi
Transfer clock output
The CKDIR bit in the UiMR register = 0
Transfer clock input
The CKDIR bit in the UiMR register = 1
Set the port direction bit corresponding to the CLKi pin = 0
CTS input
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 0
Set the port direction bit corresponding to the CTSi pin = 0
RTS output
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 1
I/O port
The CRD bit in the UiC0 register = 1
CTSi / RTSi
i = 0 to 2, 5 to 7
Table 17.4
P6_4 Pin Functions during Clock Synchronous Serial I/O Mode
Bit Set Value
Pin Function
U1C0 Register
CRD
UCON Register
CRS
RCSP
CLKMD1
PD6 Register
CLKMD0
PD6_4
P6_4
1
-
0
0
-
Input: 0, Output: 1
CTS1
0
0
0
0
-
0
RTS1
0
1
0
0
-
-
CTS0 (1)
0
0
1
0
-
0
CLKS1
-
-
-
1 (2)
1
-
- indicates either 0 or 1
NOTES:
1. In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0 / RTS0 enabled) and the CRS bit
in the U0C0 register to 1 (RTS0 selected).
2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the CLKPOL bit in the U1C0 register = 0
• Low if the CLKPOL bit in the U1C0 register = 1
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17. Serial Interface
(1) Example of Transmit Timing (when internal clock is selected)
Tc
Transfer clock
“1”
TE bit in
UiC1 register
“0”
Data is set in the UiTB register
“1”
TI bit in
UiC1 register
“0”
Data is transferred from the UiTB register to
the UARTi transmit register
“H”
CTSi
TCLK
“L”
Pulse stops because an "H”
signal is applied to CTSi
Pulse stops because the TE bit is set to 0
CLKi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXDi
TXEPT flag in
UiC0 register
“1”
“0”
IR bit in
SiTIC register
“1”
“0”
i = 0 to 2, 5 to 7
D0 D1 D2 D3 D4 D5 D6 D7
Set to 0 by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
· The CKDIR bit in the UiMR register = 0 (internal clock)
· The CRD bit in the UiC0 register
= 0 (CTS / RTS enabled), the CRS bit = 0 (CTS selected)
· The CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
· The UiIRS bit in the UiC1 register
= 0 (an interrupt request occurs when the UiTB register
becomes empty)
TC = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to the UiBRG register
(2) Example of Receive Timing (when external clock is selected)
RE bit in
UiC1 register
“1”
TE bit in
UiC1 register
“1”
TI bit in
UiC1 register
“1”
RTSi
“0”
“0”
Dummy data is set in the UiTB register
“0”
Data is transferred from the UiTB register to the UARTi transmit register
“H”
“L”
1 / fEXT
An "L” signal is applied when the UiRB register is read
CLKi
Received data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
RXDi
RI bit in
UiC1 register
“1”
“0”
IR bit in
SiRIC register
“1”
“0”
Data is transferred from the UARTi
receive register to the UiRB register
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5 D6
Read by the UiRB register
Set to 0 by an interrupt request acknowledgement or by program
OER flag in
UiRB register
“1”
“0”
i = 0 to 2, 5 to 7
The above timing diagram applies to the case where the register bits are set as follows:
· The CKDIR bit in the UiMR register = 1 (external clock)
· The CRD bit in the UiC0 register = 0 (CTS / RTS enabled), the CRS bit = 1 (RTS selected)
· The CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
Make sure the following conditions are met when input to
the CLKi pin before receiving data is high:
· The TE bit in the UiC0 register = 1 (transmit enabled)
· The RE bit in the UiC1 register = 1 (receive enabled)
· Write dummy data to the UiTB register
fEXT: frequency of the external clock
Figure 17.12 Transmit and Receive Operation during Clock Synchronous Serial I/O Mode
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Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.1.1
17. Serial Interface
Counter Measure for Communication Error
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
• Resetting the UiRB register (i = 0 to 2, 5 to 7)
(1) Set the RE bit in the UiC1 register to 0 (reception disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)
(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to 1 (reception enabled)
• Resetting the UiTB register (i = 0 to 2, 5 to 7)
(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)
(2) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode)
(3) A 1 is written to the RE bit in the UiC1 register (transmission enabled), regardless of the value of
the TE bit in the UiCi register
17.1.1.2
CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the transfer clock polarity. Figure
17.13 shows the Transfer Clock Polarity.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
“H” is output from the CLKi pin
during no transmission.
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the
receive data taken in at the falling edge of the transfer clock) “L” is output from the CLKi pin
during no transmission.
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
The above applies to the case where
the UFORM bit in the UiC0 register = 0 (LSB first) and
the UiLCH bit in the UiC1 register = 0 (no reverse).
i = 0 to 2, 5 to 7
Figure 17.13 Transfer Clock Polarity
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M16C/64 Group
17.1.1.3
17. Serial Interface
LSB First / MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2, 5 to 7) to select the transfer format. Figure 17.14
shows the Transfer Format.
(1) When the UFORM Bit in the UiC0 Register = 0 (LSB First)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UFORM Bit in the UiC0 Register = 1 (MSB First)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
The above applies to the case where
the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge
and the receive data taken in at the rising edge of the transfer clock), and
the UiLCH bit in the UiC1 register = 0 (no reverse).
i = 0 to 2, 5 to 7
Figure 17.14 Transfer Format
17.1.1.4
Continuous Reception Mode
In continuous reception mode, receive operation becomes enabled when the receive buffer register
is read. It is not necessary to write dummy data into the transmit buffer register to enable receive
operation in this mode. However, a dummy read of the receive buffer register is required when starting the operating mode.
When the UiRRM bit (i = 0 to 2, 5 to 7) = 1 (continuous reception mode), the TI bit in the UiC1 register
is set to 0 (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM
bit = 1, do not write dummy data to the UiTB register in a program. Bits U0RRM and U1RRM correspond to bits 2 and 3 in the UCON register, respectively. Bits U2RRM, U5RRM, U6RRM, and
U7RRM are in registers U2C1, U5C1, U6C1, and U7C1.
REJ09B0392-0064 Rev.0.64
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M16C/64 Group
17.1.1.5
17. Serial Interface
Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2, 5 to 7) = 1 (reverse), the data written to the UiTB
register has its logic reversed before being transmitted. Similarly, the received data has its logic
reversed when read from the UiRB register. Figure 17.15 shows Serial Data Logic Switching.
(1) When the UiLCH Bit in the UiC1 Register = 0 (No Reverse)
Transfer Clock
TXDi
(No Reverse)
“H”
“L”
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH Bit in the UiC1 Register = 1 (Reverse)
Transfer Clock
TXDi
(Reverse)
“H”
“L”
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
This applies to the case where
the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge of the transfer clock), and
the UFORM bit in the UiC0 register = 0 (LSB first)
i = 0 to 2, 5 to 7
Figure 17.15 Serial Data Logic Switching
17.1.1.6
Transfer Clock Output from Multiple Pins (UART1)
Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transfer clock output
pins (see Figure 17.16). This function can be used when the selected transfer clock for UART1 is an
internal clock.
Microcomputer
TXD1 (P6_7)
CLKS1 (P6_4)
CLK1 (P6_5)
IN
IN
CLK
CLK
Transfer enabled when the CLKMD0
bit in the UCON register = 0
Transfer enabled when the CLKMD0
bit in the UCON register = 1
The above applies to the case where
the CKDIR bit in the U1MR register = 0 (internal clock) and
the CLKMD1 bit in the UCON register = 1 (transfer clock output from multiple pins).
Figure 17.16 Transfer Clock Output from Multiple Pins
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M16C/64 Group
17.1.1.7
17. Serial Interface
CTS / RTS Function
The CTS function is used to start transmit and receive operation when “L” is applied to the CTSi /
RTSi (i = 0 to 2, 5 to 7) pin. Transmit and receive operation begins when the CTSi / RTSi pin is held
“L”. If the “L” signal is switched to “H” during a transmit or receive operation, the operation stops
before the next data.
For the RTS function, the CTSi / RTSi pin outputs “L” when the microcomputer is ready to receive.
The output level becomes “H” on the first falling edge of the CLKi pin.
• The CRD bit in the UiC0 register = 1 (disable CTS / RTS function)
CTSi / RTSi pin is programmable I/O function
• The CRD bit = 0, CRS bit = 0 (CTS function selected) CTSi / RTSi pin is CTS function
• The CRD bit = 0, CRS bit = 1 (RTS function selected) CTSi / RTSi pin is RTS function
17.1.1.8
CTS / RTS Separate Function (UART0)
This function separates CTS0 / RTS0, outputs RTS0 from the P6_0 pin, and inputs CTS0 from the
P6_4 pin. To use this function, set the register bits as shown below.
• The CRD bit in the U0C0 register
= 0 (enable CTS / RTS of UART0)
• The CRS bit in the U0C0 register
= 1 (output RTS of UART0)
• The CRD bit in the U1C0 register
= 0 (enable CTS / RTS of UART1)
• The CRS bit in the U1C0 register
= 0 (input CTS of UART1)
• The RCSP bit in the UCON register
= 1 (inputs CTS0 from the P6_4 pin)
• The CLKMD1 bit in the UCON register
= 0 (CLKS1 not used)
Note that when using the CTS / RTS separate function, CTS / RTS of UART1 function cannot be
used.
Microcomputer
IN
RXD0 (P6_2)
OUT
CLK0 (P6_1)
CLK
RTS0 (P6_0)
CTS
CTS0 (P6_4)
RTS
Figure 17.17 CTS / RTS Separate Function
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IC
TXD0 (P6_3)
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.2
17. Serial Interface
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer
data format. Table 17.5 lists the UART Mode Specifications.
Table 17.5
UART Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission, Reception Control
Transmission Start Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
Specification
• Character bit (transfer data): selectable from 7, 8, or 9 bits
• Start bit
: 1 bit
• Parity bit
: selectable from odd, even, or none
• Stop bit
: selectable from 1 bit or 2 bits
• The CKDIR bit in the UiMR register = 0 (internal clock): fj / (16(n + 1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: setting value of UiBRG register 00h to FFh
• CKDIR bit = 1 (external clock): fEXT / (16(n + 1))
fEXT: input from CLKi pin n: setting value of UiBRG register 00h to FFh
Selectable from CTS function, RTS function or CTS / RTS function disabled
Before transmission starts, satisfy the following requirements
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
• If CTS function is selected, input on the CTSi pin = “L”
Before reception starts, satisfy the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
For transmission, one of the following conditions can be selected
• The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial interface completes sending
data from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at completion of reception)
• Overrun error (1)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the bit one before the last stop bit of the next data
• Framing error (3)
This error occurs when the number of stop bits set is not detected
• Parity error (3)
This error occurs when if parity is enabled, the number of 1 in parity and character
bits does not match the number of 1 set
• Error sum flag
This flag is set to 1 when any of the overrun, framing, or parity errors occur
• LSB first, MSB first selection
Whether to start sending / receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit / receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data are reversed.
• Separate CTS / RTS pins (UART0)
CTS0 and RTS0 are input / output from separate pins.
i = 0 to 2, 5 to 7
NOTES:
1. If an overrun error occurs, the receive data of the UiRB register will be indeterminate. The IR bit in the SiRIC register does not change.
2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register. Bits U2IRS, U5IRS, U6IRS, and U7IRS are in registers U2C1, U5C1, U6C1, and U7C1.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UARTi receive register to the UiRB register.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.6
17. Serial Interface
Registers to Be Used and Settings in UART Mode
Register
UiTB
0 to 8
Bit
UiRB
0 to 8
UiBRG
UiMR
OER, FER, PER,
SUM
0 to 7
SMD2 to SMD0
UiC0
CKDIR
STPS
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
UiIRS (2)
UiRRM (2)
UiLCH
UiERE
UiSMR 0 to 7
UiSMR2 0 to 7
UiSMR3 0 to 7
UiSMR4 0 to 7
UCON U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
7
Function
Set transmission data
(1)
Reception data can be read (1)
Error flag
Set a bit rate
Set these bits to 100b when transfer data is 7 bits long
Set these bits to 101b when transfer data is 8 bits long
Set these bits to 110b when transfer data is 9 bits long
Select the internal clock or external clock
Select the stop bit
Select whether parity is included and whether odd or even
Select the TXD / RXD input / output polarity
Select the count source for the UiBRG register
Select CTS or RTS to use functions
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TXDi pin output mode (3)
Set to 0
LSB first or MSB first can be selected when transfer data is 8 bits long.
Set this bit to 0 when transfer data is 7 or 9 bits long.
Set this bit to 1 to enable transmission
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the source of UARTi transmit interrupt
Set to 0
Set this bit to 1 to use reversed data logic
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
Select the source of UART0 / UART1 transmit interrupt
Set to 0
Invalid because CLKMD1 = 0
Set to 0
Set this bit to 1 to accept as input CTS0 signal of UART0 from the P6_4
pin
Set to 0
i = 0 to 2, 5 to 7
NOTES:
1. The bits used for transmit / receive data are as follows: bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
2. Set the bit 4 and bit 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM
are included in the UCON register.
3. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to 0.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
Table 17.7 lists the functions of the input / output pins during UART mode. Table 17.8 lists the P6_4 Pin
Functions in UART Mode. Note that for a period from when the UARTi operating mode is selected to
when transfer starts, the TXDi pin outputs “H” (If the N-channel open-drain output is selected, this pin is
in high-impedance state).
Table 17.7
I/O Pin Functions in UART Mode
Pin Name
Function
Method of Selection
TXDi
Serial data output
(“H” output when performing reception only)
RXDi
Serial data input
Set the port direction bit corresponding to the RXDi pin to 0
(can be used as an input port when performing transmission
only)
CLKi
Input / output port
The CKDIR bit in the UiMR register = 0
Transfer clock input
The CKDIR bit in the UiMR register = 1
Set the port direction bit corresponding to the CLKi pin to 0
CTS input
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 0
Set the port direction bit corresponding to the CTSi pin to 0
RTS input
The CRD bit in the UiC0 register = 0
The CRS bit in the UiC0 register = 1
Input / output port
The CRD bit in the UiC0 register = 1
CTSi / RTSi
i = 0 to 2 , 5 to 7
Table 17.8
P6_4 Pin Functions in UART Mode
Bit Set Value
Pin Function
U1C0 Register
CRD
UCON Register
CRS
RCSP
PD6 Register
CLKMD1
PD6_4
P6_4
1
-
0
0
Input: 0, Output: 1
CTS1
0
0
0
0
0
0
1
0
0
-
0
0
1
0
0
RTS1
CTS0
(1)
− indicates either 0 or1.
NOTE:
1. In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0 / RTS0 enabled) and the CRS bit
in the U0C0 register to 1 (RTS0 selected).
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
(1) 8-bit Data Transmit Timing (with a Parity and 1 Stop Bit)
The transfer clock stops once because an “H” signal is applied to the CTS pin when
the stop bit is verified.
The transfer clock resumes running as soon as an “L” signal is applied to the CTS pin.
Tc
Transfer clock
TE bit in
UiC1 register
“1”
TI bit in
UiC1 register
“1”
“0”
Data is set in the UiTB register
“0”
Data is transferred from the UiTB register
to the UARTi transmit register
“H”
CTSi
“L”
Parity
bit
Start bit
TXDi
ST
TXEPT bit in
UiC0 register
“1”
IR bit in
SiTIC register
“1”
D0
D1
D2
D3
D4
D5
D6
D7
P
Pulse stops because the TE
bit is set to 0
Stop
bit
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
“0”
“0”
Set to 0 by an interrupt request acknowledgement or by program
i = 0 to 2, 5 to 7
The above timing diagram applies to the case where the register bits are set as follows:
· The PRYE bit in the UiMR register
= 1 (parity enabled)
· The STPS bit in the UiMR register
= 0 (1 stop bit)
· The CRD bit in the UiC0 register
= 0 (CTS / RTS enabled) and
the CRS bit
= 0 (CTS selected)
· The UiIRS bit in the UiC1 register
= 1 (an interrupt request occurs when transmit completed)
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj
: frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n
: value set to UiBRG
(2) 9-bit Data Transmit Timing (with No Parity and 2 Stop Bits)
Tc
Transfer clock
TE bit in
UiC1 register
“1”
TI bit in
UiC1 register
“1”
“0”
Data is set in the UiTB register
“0”
Data is transferred from the UiTB register
to the UARTi transmit register
Stop
bit
Start bit
TXDi
ST
TXEPT bit in
UiC0 register
“1”
IR bit in
SiTIC register
“1”
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
Stop
bit
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
“0”
“0”
Set to 0 by an interrupt request acknowledgement or by program
i = 0 to 2, 5 to 7
The above timing diagram applies to the case where the register bits are set as follows:
· The PRYE bit in the UiMR register = 0 (parity disabled)
· The STPS bit in the UiMR register = 1 (2 stop bits)
· The CRD bit in the UiC0 register
= 1 (CTS / RTS disabled)
· The UiIRS bit in the UiC1 register = 0 (an interrupt request occurs when transmit
buffer becomes empty)
Figure 17.18 Transmit Timing in UART Mode
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TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj
: frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of UiBRG count source (external clock)
n
: value set to UiBRG
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
Example of Receive Timing When Transfer Data is 8 Bits Long
(Parity Disabled, One Stop Bit)
UiBRG count
source
RE bit in
UiC1 register
“1”
“0”
Stop bit
Start bit
RXDi
D0
Sampled “L”
D1
D7
Receive data taken in
Transfer clock
RI bit in
UiC1 register
“1”
Reception triggered when transfer clock
is generated by falling edge of start bit
Transferred from UARTi receive register
to UiRB register
“0”
“H”
RTSi
“L”
IR bit in
SiRIC register
“1”
“0”
Set to 0 by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
· The PRYE bit in the UiMR register = 0 (parity disabled)
· The STPS bit in the UiMR register
= 0 (1 stop bit)
· The CRD bit in the UiC0 register
= 0 (CTSi / RTSi enabled) and
the CRS bit
= 1 (RTSi selected)
i = 0 to 2, 5 to 7
Figure 17.19 Receive Timing in UART Mod
17.1.2.1
Bit Rate
In UART mode, the frequency set by the UiBRG register (i = 0 to 2, 5 to 7) divided by 16 become bit
rates. Table 17.9 lists an Example of Bit Rates and Settings.
Table 17.9
Example of Bit Rates and Settings
Bit Rate
(bps)
Count Source
of UiBRG
1200
2400
4800
9600
14400
19200
28800
31250
38400
51200
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f8SIO
f8SIO
f8SIO
f1SIO
f1SIO
f1SIO
f1SIO
f1SIO
f1SIO
f1SIO
Peripheral Function Clock: 16
Peripheral Function Clock: 24
MHz
MHz
Set Value of
Bit Rate (bps)
Set value of
Bit Rate (bps)
UiBRG: n
UiBRG: n
103 (67h)
1202
155 (9Bh)
1202
51 (33h)
2404
77 (4Dh)
2404
25 (19h)
4808
38 (26h)
4808
103 (67h)
9615
155 (9Bh)
9615
68 (44h)
14493
103 (67h)
14423
51 (33h)
19231
77 (4Dh)
19231
34 (22h)
28571
51 (33h)
28846
31 (1Fh)
31250
47 (2Fh)
31250
25 (19h)
38462
38 (26h)
38462
19 (13h)
50000
28 (1Ch)
51724
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.2.2
17. Serial Interface
Counter Measure for Communication Error
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures
below.
• Resetting the UiRB register (i = 0 to 2, 5 to 7)
(1) Set the RE bit in the UiC1 register to 0 (reception disabled)
(2) Set the RE bit in the UiC1 register to 1 (reception enabled)
• Resetting the UiTB register
(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)
(2) Reset bits SMD2 to SMD0 in the UiMR register to 001b, 101b, and 110b.
(3) 1 is written to the RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in
the UiC1 register
17.1.2.3
LSB First / MSB First Select Function
As shown in Figure 17.20, use the UFORM bit in the UiC0 register to select the transfer format. This
function is valid when transfer data is 8 bits long.
(1) When the UFORM Bit in the UiC0 Register = 0 (LSB First)
CLKi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UFORM Bit in the UiC0 Register = 1 (MSB First)
CLKi
TXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
ST : start bit
P : parity bit
SP : stop bit
i = 0 to 2, 5 to 7
The above applies to the case where
the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock),
the UiLCH bit in the UiC1 register = 0 (no reverse),
the STPS bit in the UiMR register = 0 (1 stop bit), and
the PRYE bit in the UiMR register = 1 (parity enabled).
Figure 17.20 Transfer Format
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.2.4
17. Serial Interface
Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 17.21 shows Serial
Data Logic Switching.
(1) When the UiLCH bit in the UiC1 Register = 0 (No Reverse)
“H”
Transfer
“L”
Clock
“H”
TXDi
(No Reverse) “L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
P
SP
(2) When the UiLCH Bit in the UiC1 Register = 1 (Reverse)
Transfer
Clock
TXDi
(Reverse)
“H”
“L”
“H”
ST
“L”
D0
D1
D2
D3
D4
D5
D6
D7
ST : start bit
P : parity bit
SP : stop bit
i = 0 to 2, 5 to 7
The above applies to the case where
the CKPOL bit in the UiC0 register
the UFORM bit in the UiC0 register
the STPS bit in the UiMR register
the PRYE bit in the UiMR register
= 0 (transmit data output at the falling edge of the transfer clock),
= 0 (LSB first),
= 0 (1 stop bit), and
= 1 (parity enabled).
Figure 17.21 Serial Data Logic Switching
17.1.2.5
TXD and RXD I/O Polarity Reverse Function
This function reverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all
input / output data (including bits for start, stop, and parity) are reversed. Figure 17.22 shows the
TXD and RXD I/O Polarity Reverse.
(1) When the IOPOL Bit in the UiMR Register = 0 (No Reverse)
“H”
Transfer
“L”
Clock
“H”
TXDi
(No Reverse) “L”
“H”
RXDi
(No Reverse) “L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL Bit in the UiMR Register = 1 (Reverse)
Transfer
Clock
TXDi
(Reverse)
RXDi
(Reverse)
“H”
“L”
“H”
“L”
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST: start bit
P : parity bit
SP: stop bit
i = 0 to 2, 5 to 7
The above applies to the case where the UFORM bit in the UiC0 register = 0 (LSB first), the
STPS bit in the UiMR register = 0 (1 stop bit), and the PRYE bit in the UiMR register = 1
(parity enabled).
Figure 17.22 TXD and RXD I/O Polarity Reverse
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.2.6
17. Serial Interface
CTS / RTS Function
The CTS function is used to start transmit operation when “L” is applied to the CTSi / RTSi (i = 0 to 2,
5 to 7) pin. Transmit operation begins when the CTSi / RTSi pin is held “L”. If the “L” signal is
switched to “H” during a transmit operation, the operation stops after the ongoing transmit / receive
operation is completed.
When the RTS function is used, the CTSi / RTSi pin outputs “L” when the microcomputer is ready to
receive. The output level becomes “H” on the first falling edge of the CLKi pin.
• CRD bit in the UiC0 register = 1 (disable CTS / RTS function)
CTSi / RTSi pin is programmable I/O function
• The CRD bit = 0, the CRS bit = 0 (CTS function is selected) CTSi / RTSi pin is CTS function
• The CRD bit = 0, the CRS bit = 1 (RTS function is selected) CTSi / RTSi pin is RTS function
17.1.2.7
CTS / RTS Separate Function (UART0)
This function separates CTS0 / RTS0, outputs RTS0 from the P6_0 pin, and inputs CTS0 from the
P6_4 pin. To use this function, set the register bits as shown below.
• The CRD bit in the U0C0 register
= 0 (enable CTS / RTS of UART0)
• The CRS bit in the U0C0 register
= 1 (output RTS of UART0)
• The CRD bit in the U1C0 register
= 0 (enable CTS / RTS of UART1)
• The CRS bit in the U1C0 register
= 0 (input CTS of UART1)
• The RCSP bit in the UCON register
= 1 (inputs CTS0 from the P6_4 pin)
• The CLKMD1 bit in the UCON register
= 0 (CLKS1 not used)
Note that when using the CTS / RTS separate function, CTS / RTS of UART1 function cannot be
used.
microcomputer
IN
RXD0 (P6_2)
OUT
RTS0 (P6_0)
CTS
CTS0 (P6_4)
RTS
Figure 17.23 CTS / RTS Separate Function
REJ09B0392-0064 Rev.0.64
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IC
TXD0 (P6_3)
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.3
17. Serial Interface
Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 17.10 lists the specifications of I2C mode. Tables 17.11 and 17.12 list the registers used in I2C mode and the register values set. Table 17.13 lists the I2C Mode Functions. Figure 17.24 shows the block diagram for I2C mode.
Figure 17.25 shows Transfer to UiRB Register and Interrupt Timing.
As shown in Table 17.13, the microcomputer is placed in I2C mode by setting bits SMD2 to SMD0 to
010b and the IICM bit to 1. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
Table 17.10
I2C Mode Specifications
Item
Transfer Data Format
Transfer Clock
Specification
Transfer data length: 8 bits
• During master
CKDIR bit in the UiMR register = 0 (internal clock): fj / (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of the UiBRG register
00h to FFh
• During slave
CKDIR bit = 1 (external clock): input from the SCLi pin
Transmission Start Condition
Before transmission starts, satisfy the following requirements (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
Reception Start Condition
Before reception starts, satisfy the following requirements (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, or
acknowledge detected
Interrupt Request
Generation Timing
Error Detection
Select Function
Overrun error (2)
This error occurs if the serial interface started receiving the next data
before reading the UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles
selectable
• Clock phase setting
With or without clock delay selectable
i = 0 to 2, 5 to 7
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in high
state.
2. If an overrun error occurs, the received data of the UiRB register will be indeterminate. The IR bit in
the SiRIC register does not change.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
SDAi
Delay
circuit
ACKC = 1
Start and stop condition generation block
STSPSEL = 1
DMA0 to DMA3 request
SDA (STSP)
SCL (STSP)
STSPSEL = 0
IICM2 = 1
Transmission
register
ACKC = 0
UARTi transmit, NACK
interrupt request
IICM = 1 and
IICM2 = 0
UARTi
SDHI
ACKD bit
D Q
T
Noise
filter
ALS
DMA0, DMA2 request
Arbitration
IICM2 = 1
Reception
register
UARTi
Start condition
detection
S
R
Q
IICM = 1 and
IICM2 = 0
Bus
busy
Stop condition
detection
NACK
D Q
T
Falling edge
detection
SCLi
IICM = 0
R
I/O port
D Q
T
Port register (1)
UARTi
STSPSEL
IICM = 1
=1
ACK
9th bit
Q
STSPSEL=0
Noise
filter
UARTi receive,
ACK interrupt request,
DMA1, DMA3 request
Internal clock
SWC2
External
clock
R
S
Start / stop condition detection
interrupt request
CLK
control
UARTi
9th bit falling edge
SWC
This diagram applies to the case where bits SMD2 to SMD0 in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
IICM
: bit in the UiSMR register
IICM2, SWC, ALS, SWC2, SDHI : bits in the UiSMR2 register
STSPSEL, ACKD, ACKC
: bits in the UiSMR4 register
i = 0 to 2, 5 to 7
If the IICM bit = 1, the pin can be read even when the port direction bit corresponding to the SCLi pin = 1 (output mode).
Figure 17.24 I2C Mode Block Diagram
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.11
17. Serial Interface
Registers to Be Used and Settings in I2C Mode (1)
Register
UiTB
UiRB (3)
UiBRG
UiMR (3)
UiC0
Bit
0 to 7
0 to 7
8
ABT
OER
0 to 7
SMD2 to
SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
UiC1
CRD (4)
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS (1)
UiSMR
UiSMR2
UiRRM (1),
UiLCH,
UiERE
IICM
ABC
BBS
3 to 7
IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
Function
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a bit rate
Set to 010b
Slave
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to 010b
Set to 0
Set to 0
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to 1
Set to 1
Set to 0
Invalid
Invalid because CRD = 1
Transmit register empty flag
Set to 1
Set to 1 (2)
Set to 0
Set to 1
Set this bit to 1 to enable transmission
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Invalid
Set to 0
Set to 1 (2)
Set to 0
Set to 1
Set this bit to 1 to enable transmission
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Invalid
Set to 0
Set to 1
Select the timing at which arbitration lost is
detected
Bus busy flag
Set to 0
Set to 1
Invalid
See Table 17.13 I2C Mode Functions
Set this bit to 1 to enable clock synchronization
Set this bit to 1 to have SCLi output fixed to
“L” at the falling edge of the 9th bit of clock
Set this bit to 1 to have SDAi output stopped
when arbitration lost is detected
Set to 0
Set this bit to 1 to have SCLi output forcibly
pulled low
Set this bit to 1 to disable SDAi output
Set to 0
Bus busy flag
Set to 0
See Table 17.13 I2C Mode Functions
Set to 0
Set this bit to 1 to have SCLi output fixed to
“L” at the falling edge of the 9th bit of clock
Set to 0
Set this bit to 1 to initialize UARTi at start
condition detection
Set this bit to 1 to have SCLi output forcibly
pulled low
Set this bit to 1 to disable SDAi output
Set to 0
i = 0 to 2, 5 to 7
NOTES:
1. Set the bit 4 and bit 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the
UCON register.
2. The TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to 0.
3. Set the bits not listed above to 0 when writing to the registers in I2C mode.
4. When using UART1 in I2C mode and enabling the CTS / RTS separate function of UART0, set the CRD bit in the
U1C0 register to 0 (CTS / RTS enabled) and the CRS bit to 0 (CTS input).
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.12
17. Serial Interface
Registers to Be Used and Settings in I2C Mode (2)
Register
Function
Bit
UiSMR3 0, 2, 4, and
NODC
CKPH
DL2 to DL0
UiSMR4 STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR2A IFSR26,
ISFR27
UCON
U0IRS,
U1IRS
2 to 7
Master
Slave
Set to 0
Set to 0
See Table 17.13 “I2C Mode Functions”
Set the amount of SDAi digital delay
Set this bit to 1 to generate start condition
Set this bit to 1 to generate restart condition
Set this bit to 1 to generate stop condition
Set this bit to 1 to output each condition
Select ACK or NACK
Set this bit to 1 to output ACK data
Set this bit to 1 to have SCLi output
stopped when stop condition is
detected
Set to 0
See Table 17.13 “I2C Mode Functions”
Set the amount of SDAi digital delay
Set to 0
Set to 0
Set to 0
Set to 0
Select ACK or NACK
Set this bit to 1 to output ACK data
Set to 0
Set to 1
Set this bit to 1 to set the SCLi to “L”
hold at the falling edge of the 9th bit of
clock
Set to 1
Invalid
Invalid
Set to 0
Set to 0
i = 0 to 2, 5 to 7
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.13
17. Serial Interface
I2C Mode Functions
Function
Clock Synchronous Serial
I/O Mode (SMD2 to SMD0
= 001b, IICM = 0)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0
(NACK/ACK interrupt)
CKPH = 0
(No clock delay)
IICM2 = 1
(UART transmit / receive interrupt)
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
Factor of Interrupt Number
5, 6, 7, 10, 27, and 28 (1, 5,
7))
-
Start condition detection or stop condition detection
(See Table 17.14 “STSPSEL Bit Functions”)
Factor of Interrupt Number
15, 17, 19, 21, 23, and 24 (1,
UARTi transmission
Transmission started or
completed (selected by
UiIRS)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
6)
UARTi transmission
Rising edge of SCLi
9th bit
CKPH = 1
(Clock delay)
UARTi transmission
Falling edge of SCLi
next to the 9th bit
UARTi reception
Acknowledgment detection (ACK)
When 8th bit received
Rising edge of SCLi 9th bit
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
UARTi reception
Falling edge of SCLi 9th bit
Timing for Transferring Data
from the UART Reception
Shift Register to the UiRB
Register
CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit
CKPOL = 1 (falling edge)
Falling edge of SCLi
9th bit
UARTi Transmission Output Delay
Not delayed
Functions of TXDi / SDAi
TXDi output
SDAi input / output
Functions of RXDi / SCLi
RXDi input
SCLi input / output
Functions of CLKi
CLKi input or output port
selected
− (Cannot be used in I2C mode)
Noise Filter Width
15ns
200ns
Read RXDi and SCLi Pin
Levels
Possible when the corresponding port direction
bit = 0
Always possible no matter how the corresponding port direction bit is set
Initial Value of TXDi and
SDAi Outputs
CKPOL = 0 (“H”)
CKPOL = 1 (“L”)
The value set in the port register before setting I2C mode (2)
Initial and End Values of
SCLi
-
“H”
DMA1 Factor (6)
UARTi reception
Acknowledgment detection (ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store Received Data
1st to 8th bits of the
received data are stored
into bits 0 to 7 in the
UiRB register
1st to 8th bits of the received data are
stored into bits 7 to 0 in the UiRB register
1st to 7th bits of the received data are stored
into bits 6 to 0 in the UiRB register. 8th bit is
stored into bit 8 in the UiRB register
Factor of Interrupt Number
16, 18, 20, 22, 25, and 26 (1,
6)
Read Received Data
Falling and rising
edges of SCLi 9th bit
Delayed
The UiRB register status is read
“L”
“H”
“L”
1st to 8th bits are
stored into bits 7 to 0
in the UiRB register (3)
Bits 6 to 0 in the UiRB
register are read as
bits 7 to 1. Bit 8 in the
UiRB register is read
as bit 0 (4)
i = 0 to 2, 5 to 7
NOTES:
1. If the source or factor of any interrupt is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to 1 (interrupt requested). (Refer to 24.7 “Interrupt”)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore,
always be sure to clear the IR bit to 0 (interrupt not requested) after changing those bits.
Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register, the IICM2 bit in the UiSMR
register, and the CKPH bit in the UiSMR3 register
2. Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register = 000b (serial interface
disabled).
3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)
4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)
5. See Figure 17.27 “STSPSEL Bit Functions”.
6. See Figure 17.25 “Transfer to UiRB Register and Interrupt Timing”.
7. When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to 1 (factor of interrupt: UART0 bus
collision).
When using UART1, be sure to set the IFSR27 bit in the IFSR2A register to 1 (factor of interrupt: UART1 bus
collision).
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Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1, DMA3 request),
NACK interrupt
Transfer to UiRB register
b15
b9
...
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
UiRB register
(2) IICM2 = 0, CKPH = 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1, DMA3 request),
NACK interrupt
Transfer to UiRB register
b15
b9
...
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
UiRB register
(3) IICM2 = 1 (UART transmit / receive interrupt), CKPH = 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt Transmit
(DMA1, DMA3
interrupt
request)
Transfer to UiRB register
b15
b9
...
b8
b7
b0
D0
D7
D6
D5
D4
UiRB register
(4) IICM2 = 1, CKPH = 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1, DMA3
request)
Transfer to UiRB register
b15
b9
...
b8
D0
b7
b0
D7
D6
D5
D4
D3
D2
D1
Transmit interrupt
Transfer to UiRB register
b15
b9
...
UiRB register
i = 0 to 2, 5 to 7
This diagram applies to the case where the following condition is met.
· The CKDIR bit in the UiMR register = 0 (slave selected)
Figure 17.25 Transfer to UiRB Register and Interrupt Timing
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b8
b7
D8
D7
b0
D6
D5
D4
D3
UiRB register
D2
D1
D0
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.3.1
17. Serial Interface
Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition detect interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition detect interrupt request is generated when
the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition detect interrupts share the interrupt control register and vector,
check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up
3 to 6 cycles < duration for holding (1)
(1)
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
i = 0 to 2, 5 to 7
When the PCLK1 bit in the PCLKR register = 1, this is the cycle number of
f1SIO, and the PCLK1 bit = 0, the cycle number of f2SIO.
Figure 17.26 Detection of Start and Stop Condition
17.1.3.2
Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2, 5 to 7) to
1 (start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to 1 (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the UiSMR4 register to 1 (output).
The function of the STSPSEL bit is shown in Tables 17.14 and 17.27.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.14
17. Serial Interface
STSPSEL Bit Functions
Function
Output of Pins SCLi and
SDAi
STSPSEL = 0
Output of transfer clock and data
Output of start / stop condition is
accomplished by a program using
ports (not automatically generated in
hardware)
Detect start / stop condition
Start / Stop Condition
Interrupt Request Generation Timing
STSPSEL = 1
Output of a start / stop condition
according to bits STAREQ,
RSTAREQ, and STPREQ
Complete generating start / stop condition
(1) When Slave
CKDIR = 1 (external clock)
STSPSEL bit
0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When Master
CKDIR = 0 (internal clock), CKPH = 1 (clock delayed)
STSPSEL bit
Set to 1 in
a program
Set to 0 in
a program
Set to 1 in
a program
Set to 0 in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Set STAREQ = 1
(start)
i = 0 to 2, 5 to 7
Start condition detection
interrupt
Set STPREQ=1
Stop condition detection
(start)
interrupt
Figure 17.27 STSPSEL Bit Functions
17.1.3.3
Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising
edge of SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the
UiRB register is updated. If the ABC bit = 0 (update per bit), the ABT bit is set to 1 at the same time
unmatching is detected during check, and is cleared to 0 when not detected. In cases when the ABC
bit is set to 1, if unmatching is ever detected, the ABT bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated per byte, clear the ABT bit to
0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte.
Setting the ALS bit in the UiSMR2 register to 1 (SDA output stop enabled) factors arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit
is set to 1 (unmatching detected).
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.3.4
17. Serial Interface
Transfer Clock
The transfer clock is used to transmit and receive data as is shown in Figure 17.25 Transfer to UiRB
Register and Interrupt Timing.
The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal
SCLi) and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to 1 (clock
synchronization enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high,
the internal SCLi goes low, at which time the value of the UiBRG register is reloaded with and starts
counting in the low-level interval. If the internal SCLi changes state from low to high while the SCLi
pin is low, counting stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is equivalent to AND of the internal SCLi and the clock signal
applied to the SCLi pin. The transfer clock works between a half cycle before the falling edge of the
internal SCLi 1st bit and the rising edge of the 9th bit. To use this function, select an internal clock for
the transfer clock.
The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to be or freed from lowlevel output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the UiSMR4 register is set to 1 (enabled), SCLi output is turned off (placed in the
high-impedance state) when a stop condition is detected.
Setting the SWC2 bit in the UiSMR2 register = 1 (0 output) makes it possible to forcibly output a lowlevel signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to 0
(transfer clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal.
If the SWC9 bit in the UiSMR4 register is set to 1 (SCL hold low enabled) when the CKPH bit in the
UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse
next to the 9th. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level
output.
17.1.3.5
SDA Output
The data written to bits 7 to 0 (D7 to D0) in the UiTB register is output in descending order from D7.
The 9th bit (D8) is ACK or NACK.
Set the initial value of SDAi transmit output when IICM = 1 (I2C mode) and bits SMD2 to SMD0 in the
UiMR register = 000b (serial interface disabled).
Bits DL2 to DL0 in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count
source clock cycles to SDAi output.
Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in
the high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi transfer clock.
This is because the ABT bit may inadvertently be set to 1 (detected).
17.1.3.6
SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits 7 to 0 in the
UiRB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits 6 to 0 in the
UiRB register and the 8th bit (D0) is stored in bit 8 in the UiRB register. Even when the IICM2 bit = 1,
providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read. To read the data,
read the UiRB register after the rising edge of 9th bit of the corresponding clock pulse.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.3.7
17. Serial Interface
ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to 0 (start and stop conditions not generated) and
the ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the
UiSMR4 register is output from the SDAi pin.
If the IICM2 bit = 0, the NACK interrupt request is generated if the SDAi pin remains high at the rising
edge of the 9th bit of transmit clock pulse. The ACK interrupt request is generated if the SDAi pin is
low at the rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected to generate a DMA1 or DMA3 request source, a DMA transfer can be activated by
detection of an acknowledge.
17.1.3.8
Initialization of Transmission / Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface operates as described below.
• The transmit shift register is initialized, and the content of the UiTB register is transferred to the
transmit shift register. In this way, the serial interface starts sending data synchronously with the
next clock pulse applied. However, the UARTi output value does not change state and remains the
same as when a start condition was detected until the first bit of data is output synchronously with
the input clock.
• The receive shift register is initialized, and the serial interface starts receiving data synchronously
with the next clock pulse applied.
• The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the 9th clock pulse.
Note that when UARTi transmission / reception is started using this function, the TI bit does not
change state. Select the external clock as the transfer clock to start UARTi transmission / reception
with this setting.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.4
17. Serial Interface
Special Mode 2
In special mode 2, serial communication between one or multiple masters and multiple slaves is available. Transfer clock polarity and phase are selectable. Table 17.15 lists the Special Mode 2 Specifications. Table 17.16 lists the Registers to Be Used and Settings in Special Mode 2. Figure 17.28 shows
Special Mode 2 Communication Control Example (UART2).
Table 17.15
Special Mode 2 Specifications
Item
Transfer Data Format
Transfer Clock
Transmit / Receive Control
Transmission Start Condition
Reception Start Condition
Specification
Transfer data length: 8 bits
• Master mode
The CKDIR bit in the UiMR register = 0 (internal clock): fj / (2(n + 1))
fj = f1SIO, f2SIO, f8SIO, f32SIO n: setting value of UiBRG register 00h to FFh
• Slave mode
• The CKDIR bit = 1 (external clock selected): input from the CLKi pin
Controlled by input / output ports
Before transmission starts, satisfy the following requirements (1)
• The TE bit in the UiC1 register
= 1 (transmission enabled)
• The TI bit in the UiC1 register
= 0 (data present in UiTB register)
Before reception starts, satisfy the following requirements (1)
• The RE bit in the UiC1 register
• The TE bit
• The TI bit
= 1 (reception enabled)
= 1 (transmission enabled)
= 0 (data present in the UiTB register)
Interrupt Request Generation
Timing
While transmitting, one of the following conditions can be selected
• The UiIRS bit in the UiC1 register= 0 (transmit buffer empty): when transferring
data from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit
=1 (transfer completed):
when the serial interface completed sending data from the UARTi transmit register
While receiving
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error Detection
Overrun error (2)
Select Function
This error occurs if the serial interface starts receiving the next data before reading
the UiRB register and receives the 7th bit of the next data
Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
i = 0 to 2, 5 to 7
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in high state; if the CKPOL bit = 1 (transmit data output at the rising edge and the receive data
taken in at the falling edge of the transfer clock), the external clock is in low state.
2. If an overrun error occurs, the received data of the UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
P1_3
P1_2
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
Microcomputer
(master)
P9_3
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
Microcomputer
(slave)
P9_3
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
Microcomputer
(slave)
Figure 17.28 Special Mode 2 Communication Control Example (UART2)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.16
17. Serial Interface
Registers to Be Used and Settings in Special Mode 2
Register
Bit
Function
UiTB
(3)
0 to 7
Set transmission data
UiRB
(3)
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
Reception data can be read
Overrun error flag
Set a bit rate
Set to 001b
Set to 0 in master mode or 1 in slave mode
Set to 0
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to 1
UiBRG
UiMR (3)
UiC0
Select TXDi pin output format (2)
Clock phases can be set in combination with the CKPH bit in the
UiSMR3 register
Set to 0
Set to 1 to enable transmission / reception
Transmit buffer empty flag
Set to 1 to enable reception
Reception complete flag
Select UART2 transmit interrupt source
CKPOL
UiC1
UFORM
TE
TI
RE
RI
UiIRS (1)
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
UiRRM (1),UiLCH,
UiERE
0 to 7
0 to 7
CKPH
NODC
0, 2, 4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Set to 0
Set to 0
Set to 0
Clock phases can be set in combination with the CKPOL bit in the UiC0
register
Set to 0
Set to 0
Set to 0
Select UART0 and UART1 transmit interrupt source
Set to 0
Invalid because CLKMD1 = 0
Set to 0
i = 0 to 2, 5 to 7
NOTES:
1. Set bits 4 and 5 in registers U0C0 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in
the UCON register.
2. The TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When
write, set to 0.
3. Set the bits not listed above to 0 when writing to the registers in special mode 2.
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.4.1
17. Serial Interface
Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit
in the UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 17.29 shows the Transmission and Reception Timing in Master Mode (Internal Clock).
Figure 17.30 shows the Transmission and Reception Timing (CKPH = 0) in Slave Mode (External
Clock) while Figure 17.31 shows the Transmission and Reception Timing (CKPH = 1) in Slave Mode
(External Clock).
“H”
Clock output
(CKPOL = 0, CKPH = 0) “L”
Clock output
“H”
(CKPOL = 1, CKPH = 0) “L”
“H”
Clock output
(CKPOL = 0, CKPH = 1) “L”
“H”
Clock output
(CKPOL = 1, CKPH = 1) “L”
Data output timing
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
Data input timing
Figure 17.29 Transmission and Reception Timing in Master Mode (Internal Clock)
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D7
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
“H”
Slave control input
“L”
“H”
Clock input
(CKPOL = 0, CKPH = 0) “L”
“H”
Clock input
(CKPOL = 1, CKPH = 0) “L”
Data output timing
“H”
(1)
“L”
undefined
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Note:
1. UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 17.30 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock)
“H”
Slave control input
“L”
Clock input
(CKPOL=0, CKPH=1)
“H”
Clock input
(CKPOL=1, CKPH=1)
“H”
Data output timing
“L”
“L”
“H”
(1)
“L”
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Note:
1. UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 17.31 Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock)
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.5
17. Serial Interface
Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 17.17 lists the Registers to Be Used and Settings in IE Mode. Figure 17.32 shows the Bus Collision Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2, 5 to 7) output level and RXDi pin input level do not match, a UARTi bus collision detect interrupt request is generated.
Use bits IFSR26 and IFSR27 in the IFSR2A register to enable the UART0 / UART1 bus collision detect
function.
Table 17.17
Register
UiTB
UiRB (3)
UiBRG
UiMR
UiC0
UiC1
Registers to Be Used and Settings in IE Mode
Bit
0 to 8
0 to 8
OER, FER, PER, SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS (1)
UiSMR
UiSMR2
UiSMR3
UiSMR4
IFSR2A
UCON
UiRRM (1), UiLCH, UiERE
0 to 3, 7
ABSCS
ACSE
SSS
0 to 7
0 to 7
0 to 7
IFSR26, IFSR27
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Function
Set transmission data
Reception data can be read
Error flag
Set a bit rate
Set to 110b
Select the internal clock or external clock
Set to 0
Invalid because PRYE = 0
Set to 0
Select the TXD and RXD input / output polarity
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to 1
Select TXDi pin output format (2)
Set to 0
Set to 0
Set to 1 to enable transmission
Transmit buffer empty flag
Set to 1 to enable reception
Reception complete flag
Select the source of UARTi transmit interrupt
Set to 0
Set to 0
Select the sampling timing at which to detect a bus collision
Set this bit to 1 to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to 0
Set to 0
Set to 0
Set to 1
Select the source of UART0 / UART1 transmit interrupt
Set to 0
Invalid because CLKMD1 = 0
Set to 0
i = 0 to 2, 5 to 7
NOTES:
1. Set bits 4 and 5 in registers U0C0 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the UCON
register.
2. The TXD2 pin is N channel open-drain output. No NCH bit in the U2C0 register is assigned. When write, set to
0.
3. Set the bits not listed above to 0 when writing to the registers in IE mode.
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Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
(1) The ABSCS Bit in the UiSMR Register (Bus collision detect sampling clock select)
(i = 0 to 2, 5 to 7)
If ABSCS = 0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TXDi
RXDi
Trigger signal is applied to the TAjIN pin
Timer Aj
If ABSCS = 1, bus collision is determined when timer Aj (one-shot timer mode) underflows.
Timer Aj: Timer A3 in UART0; Timer A4 in UART1; Timer A0 in UART2
Timer A0 in UART5; Timer A3 in UART6; Timer A4 in UART7
(2) The ACSE Bit in the UiSMR Register (Auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TXDi
RXDi
IR bit in UiBCNIC and
BCNIC register
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to 0
(transmission disabled) when the
IR bit in the UiBCNIC register =
1 (unmatching detected).
TE bit in UiC1 register
(3) The SSS Bit in the UiSMR Register (Transmit start condition select)
If SSS bit = 0, the serial interface starts sending data one transfer
clock cycle after the transmission enable condition is met.
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D7
D8
SP
TXDi
Transmit enable conditions are met
If SSS bit = 1, the serial interface starts sending data at the rising edge of RXDi
(1)
CLKi
ST
TXDi
D0
D1
D2
D3
D4
D5
D6
(2)
RXDi
NOTES :
1. The falling edge of RXDi when IOPOL = 0; the rising edge of RXDi when IOPOL = 1.
2. The transmit condition must be met before the falling edge of RXD (1).
The above diagram applies to the case where IOPOL = 1 (reversed).
i = 0 to 2, 5 to 7
Figure 17.32 Bus Collision Detect Function-Related Bits
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.6
17. Serial Interface
Special Mode 4 (SIM Mode) (UART2)
SIM interface devices can communicate in UART mode. Both direct and inverse formats are available. The TXD2 pin outputs a low-level signal when a parity error is detected.
Table 17.18 lists the SIM Mode Specifications. Table 17.19 lists the Registers to Be Used and Settings in SIM Mode.
Table 17.18
SIM Mode Specifications
Item
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing (2)
Error Detection
Specification
• Direct format
• Inverse format
• The CKDIR bit in the U2MR register = 0 (internal clock): fi / (16(n + 1))
fi = f1SIO, f2SIO, f8SIO, f32SIO
n = setting value of the U2BRG register 00h to FFh
• The CKDIR bit = 1 (external clock): fEXT / (16(n + 1))
fEXT = input from the CLK2 pin
n = setting value of the U2BRG register 00h to FFh
Before transmission starts, satisfy the following requirements
• The TE bit in the U2C1 register
= 1 (transmission enabled)
• The TI bit in the U2C1 register
= 0 (data present in the U2TB register)
Before reception starts, satisfy the following requirements
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• While transmitting
When the serial interface completed sending data from the UART2 transmit
register (the U2IRS bit =1)
• While receiving
When transferring data from the UART2 receive register to the U2RB register
(at completion of reception)
• Overrun error (1)
This error occurs if the serial interface started receiving the next data before
reading the U2RB register and received the bit one before the last stop bit of
the next data
• Framing error (3)
This error occurs when the number of stop bits set is not detected
• Parity error (3)
During reception, if a parity error is detected, parity error signal is output from
the TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2
pin when a transmission interrupt occurs
• Error sum flag
This flag is set to 1 when one of the overrun, framing, and parity errors occurs
NOTES:
1. If an overrun error occurs, the received data of the U2RB register will be indeterminate. The IR bit in
the S2RIC register does not change.
2. A transmit interrupt request is generated by setting the U2IRS bit to 1 (transmission completed) and
the U2ERE bit to 1 (error signal output) in the U2C1 register after reset is canceled. Therefore, when
using SIM mode, set the IR bit to 0 (interrupt not requested) after setting the bits.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is
transferred from the UART2 receive register to the U2RB register.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.19
17. Serial Interface
Registers to Be Used and Settings in SIM Mode
Register
U2TB
(1)
U2RB (1)
U2BRG
U2MR
U2C0
U2C1
U2SMR (1)
U2SMR2
U2SMR3
U2SMR4
Bit
Function
0 to 7
Set transmission data
0 to 7
OER,FER,PER,SUM
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
CLK0,CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
U2LCH
U2ERE
0 to 3
Reception data can be read
Error flag
Set a bit rate
Set to 101b
Select the internal clock or external clock
Set to 0
Set to 1 in direct format or 0 in inverse format
Set to 1
Set to 0
Select the count source for the U2BRG register
Invalid because CRD = 1
Transmit register empty flag
Set to 1
Set to 0
Set to 0
Set to 0 in direct format or 1 in inverse format
Set to 1 to enable transmission
Transmit buffer empty flag
Set to 1 to enable reception
Reception complete flag
Set to 1
Set to 0
Set to 0 in direct format or 1 in inverse format
Set to 1
Set to 0
0 to 7
0 to 7
0 to 7
Set to 0
Set to 0
Set to 0
NOTE:
1. Set the bits not listed above to 0 when writing to the registers in SIM mode.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
Tc
(1) Transmit Timing
Transfer clock
TE bit in
U2C1 register
“1”
TI bit in
U2C1 register
“1”
“0”
(Note 1)
Data is written to the U2TB register
“0”
Parity
bit
Start
bit
TXD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
Stop
bit
Data is transferred from the U2TB
register to the UART2 transmit register
ST
SP
Parity error signal
returned from
receiving end
RXD2 pin level
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
An “L” signal is applied from the
SIM card due to a parity error
(2)
ST
TXEPT bit in
U2C0 register
“1”
IR bit in
S2TIC register
“1”
D0
D1
D2
D3
D4
D5
D6
D7
P
ST
SP
D0
D1
D2
D3
D4
An interrupt
routine
detects “H” or “L”
“0”
D5
D6
D7
SP
P
An interrupt routine detects
“H” or “L”
“0”
Set to 0 by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where data is
transmitted in the direct format.
• The STPS bit in the U2MR register = 0 (1 stop bit)
• The PRY bit in the U2MR register
= 1 (even parity)
• The UFORM bit in the U2C0 register = 0 (LSB first)
• The U2LCH bit in the U2C1 register = 0 (no reverse)
• The U2IRS bit in the U2C1 register = 1 (transmit completed)
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi
: frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n
: value set to U2BRG
Tc
(2) Receive Timing
Transfer clock
RE bit in
U2C1 register
“1”
“0”
Parity
bit
Start
bit
Transmit waveform
from
transmitting end
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
Stop
bit
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TXD2
TXD2 provides “L” output
due to a parity error
RXD2 pin level (3)
ST
RI bit in
U2C1 register
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“1”
“0”
IR bit in
S2RIC register
Read the U2RB register
“1”
“0”
Set to 0 by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where data is
received in the direct format.
• The STPS bit in the U2MR register = 0 (1 stop bit)
• The PRY bit in the U2MR register
= 1 (even parity)
• The UFORM bit in the U2C0 register = 0 (LSB first)
• The U2LCH bit in the U2C1 register = 0 (no reverse)
• The U2IRS bit in the U2C1 register = 1 (transmit completed)
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi
: frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n
: value set to U2BRG
NOTES:
1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit.
2. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the
TXD2 pin and parity error signal from the receiving end, is generated.
3. Because pins TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the
transmitting end and parity error signal from the TXD2 pin, is generated.
Figure 17.33 Transmit and Receive Timing in SIM Mode
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
Figure 17.34 shows an Example of SIM Interface Connection. Connect TXD2 and RXD2, and then
place a pull-up resistance.
Microcomputer
SIM card
TXD2
RXD2
Figure 17.34 Example of SIM Interface Connection
17.1.6.1
Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (error signal output).
The parity error signal is output when a parity error is detected while receiving data. A low-level signal
is output from the TXD2 pin in the timing shown in Figure 17.35. If the U2RB register is read while
outputting a parity error signal, the PER bit is cleared to 0 (no parity error) and at the same time the
TXD2 output is returned high.
When transmitting, a transmission complete interrupt request is generated at the falling edge of the
transfer clock pulse that immediately follows the stop bit. Therefore, whether a parity error signal has
been returned can be determined by reading the port that shares the RXD2 pin in a transmission
complete interrupt routine.
Transfer clock
RXD2
TXD2
RI bit in
U2C1 register
“H”
“L”
“H”
“L”
ST
D0
D1
“H”
D2
D3
D4
D5
D6
D7
SP
(NOTE 1)
“L”
“1”
“0”
This timing diagram applies to the case where the direct format is implemented.
Note:
1. The output of microcomputer is in the high-impedance state (pulled up externally).
Figure 17.35 Parity Error Signal Output Timing
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P
Oct 12, 2007
ST : Start bit
P : Even Parity
SP : Stop bit
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.1.6.2
17. Serial Interface
Format
Two formats are available: direct format and inverse format.
In direct format, set the PRYE bit in the U2MR register to 1 (parity enabled), the PRY bit to 1(even
parity), the UFORM bit in the U2C0 register to 0 (LSB first) and the U2LCH bit in the U2C1 register to
0 (not inverted). When data are transmitted, data set in the U2TB register are transmitted with the
even-numbered parity, starting from D0. When data are received, received data are stored in the
U2RB register, starting from D0. The even-numbered parity determines whether a parity error occurs.
In inverse format, set the PRYE bit to 1, the PRY bit to 0 (odd parity), the UFORM bit to 1 (MSB first),
and the U2LCH bit to 1 (inverted). When data are transmitted, values set in the U2TB register are
logically inversed and are transmitted with the odd-numbered parity, starting from D7. When data are
received, received data are logically inversed to be stored in the U2RB register, starting from D7. The
odd-numbered parity determines whether a parity error occurs.
(1) Direct format
Transfer clock
TXD2
“H”
“L”
“H”
D0
“L”
D1
D2
D3
D4
D5
D6
D7
P
P : Even parity
(2) Inverse format
Transfer clock
TXD2
“H”
“L”
“H”
D7
“L”
D6
D5
D4
D3
D2
D1
D0
P
P : Odd parity
Figure 17.36 SIM Interface Format
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.2
17. Serial Interface
SI/O3 and SI/O4
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 17.37 shows the SI/O3 and SI/O4 Block Diagram, and Figure 17.38 shows the Registers S3C,
S4C, S3BRG, S4BRG, S3TRR, and S4TRR.
Table 17.20 shows the SI/O3 and SI/O4 Specifications.
Main clock,
PLL clock, or
on-chip oscillator clock
1/2
Clock source select
SMi1 to SMi0
= 00b
f2SIO PCLK1 = 0
f1SIO
1/8
PCLK1 = 1 f8SIO
f32SIO
1/4
SMi6 = 0
= 01b
= 10b
SMi6
= 1 Synchronous
circuit
SMi4
CLKi
SMi3
SMi6
Data bus
1/2
1 / (n + 1)
SiBRG register
SMi6
CLK polarity
reversing
circuit
S I/O counter i
SMi2
SMi3
SMi5 LSB
SOUTi
SINi
MSB
SiTRR register
8
NOTE :
i = 3, 4
n: velue set in the SiBRG register
Figure 17.37 SI/O3 and SI/O4 Block Diagram
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S I / Oi
interrupt request
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
SI/Oi Control Register (i = 3, 4)
(1)
Symbol
S3C
S4C
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name
Bit symbol
SMi0
SMi1
SMi2
Address
0272h
0276h
After Reset
01000000b
01000000b
Function
RW
b1 b0
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Do not set
Internal synchronous
clock select bit (6)
SOUTi output disable bit
(4)
(5)
RW
0 : SOUTi output enabled
1 : SOUTi output disabled (high-Impedance)
RW
SMi3
SI/Oi port select bit
0 : Input / output port
serial interface disabled
1 : SOUTi output, CLKi function
serial interface enabled
RW
SMi4
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
RW
SMi5
Transfer direction select
bit
0 : LSB first
1 : MSB first
RW
SMi6
Synchronous clock
select bit
0 : External clock (2)
1 : Internal clock (3)
RW
SMi7
Valid when SMi6 = 0 (7)
SOUTi initial value set bit 0 : “L” output
1 : “H” output
RW
NOTES :
1. Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register
to 1 (write enabled).
2. Set the SMi3 bit to 1 and the corresponding port direction bit to 0 (input mode).
3. Set the SMi3 bit to 1 (SOUTi output, CLKi function).
4. When the SMi2 bit is set to 1, the target pin goes to high-impedance state regardless of which function of
the pin is being used.
5. Selected by the PCLK1 bit in the PCLKR register.
6. When the values of bits SMi1 and SMi0 are changed, set the SiBRG register.
7. Set the value when SMi3 bit is set to 0 (I/O port). When the SMi3 bit is set to 1 (SOUTi output)
subsequently, the selected level signal by the SMi7 bit is output from the SOUTi pin.
SI/Oi Bit Rate Register (i = 3, 4) (1, 2, 3)
b7
b0
Symbol
Address
S3BRG
S4BRG
After Reset
Indeterminate
Indeterminate
0273h
0277h
Function
Setting Range
RW
BRGi divides the count source by n + 1 where n = set value
00h to FFh
WO
NOTES :
1. Write to this register while serial interface is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
3. Write to this register after setting bits SMi1 and SMi0 in the SiC register.
SI/Oi Transmit / Receive Register (i = 3, 4) (1, 2)
b7
b0
Symbol
Address
After Reset
S3TRR
S4TRR
0270h
0274h
Indeterminate
Indeterminate
Function
Setting Range
Transmission / reception starts by writing transmit data to this register. After
transmission / reception completes, reception data can be read by reading this register.
NOTES :
1. Write to this register while serial interface is neither transmitting nor receiving.
2. To receive data, set the corresponding port direction bit for SINi to 0 (input mode).
Figure 17.38 Registers S3C, S4C, S3BRG, S4BRG, S3TRR, and S4TRR
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RW
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17. Serial Interface
SI/O 34 Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
S34C2
0
Address
0278h
Bit Name
Bit Symbol
After Reset
00XXX0X0b
Function
—
(b0)
Reserved bit
—
(b1)
No register bit. If necessary, set to 0. Read as undefined value
—
(b2)
Reserved bit
—
(b5-b3)
Set to 0
Set to 0
No register bits. If necessary, set to 0. Read as undefined value
RW
—
RW
—
SM26
SOUT3 output control bit (1)
SOUT3 status after transmission
0 : High-impedance
1 : Last bit level retained
RW
SM27
SOUT4 output control bit (1)
SOUT4 status after transmission
0 : High-impedance
1 : Last bit level retained
RW
NOTE :
1. Bits SM26 and SM27 are valid when the SMi3 bit in registers S3C and S4C are set to 1 (SOUT, CLK)
Figure 17.39 S34C2 Register
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RW
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 17.20
17. Serial Interface
SI/O3 and SI/O4 Specifications
Item
Transfer Data Format
Transfer Clock
Transmission / Reception
Start Condition
Interrupt Request Generation Timing
CLKi Pin Function
SOUTi Pin Function
SINi Pin Function
Select Function
Specification
Transfer data length: 8 bits
• The SMi6 bit in the SiC (i = 3, 4) register = 1 (internal clock): fj / (2(n + 1))
fj = f1SIO, f8SIO, f32SIO
n = setting value of the SiBRG register 00h to FFh
• The SMi6 bit = 0 (external clock): input from the CLKi pin (1)
Before transmission / reception starts, satisfy the following requirements
Write transmit data to the SiTRR register (2, 3)
• When the SMi4 bit in the SiC register = 0
The rising edge of the last transfer clock pulse (4)
• When the SMi4 bit = 1
The falling edge of the last transfer clock pulse (4)
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
Whether to start sending / receiving data beginning with bit 0 or beginning
with bit 7 can be selected
• CLK polarity selection
Whether transmit data is output / input at the rising edge or falling edge of
transfer clock can be selected.
• Function for setting an SOUTi initial value set function
When the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin
output level while not transmitting can be selected.
• SOUTi state selection after transmission
Whether to set to high-impedance or retain the last bit level can be
selected.
NOTES:
1. To set the SMi6 bit in the SiC register to 0 (external clock), follow the procedure described below.
• If the SMi4 bit in the SiC register = 0, write transmit data to the SiTRR register while input on the
CLKi pin is high. The same applies when rewriting the SMi7 bit in the SiC register.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The
same applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop
the transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock
automatically stops.
2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer.
Therefore, do not write the next transmit data to the SiTRR register during transmission.
3. When the SMi6 bit = 1 (internal clock) and bits SM26 (SOUT3) and SM27 (SOUT4) in the S34C2 register = 0 (high-impedance after transmission), SOUTi retains the last data for a 1/2 transfer clock
period after completion of transfer and, thereafter, goes to high-impedance state. However, if transmit data is written to the SiTRR register during this period, SOUTi immediately goes to high-impedance state, with the data hold time thereby reduced.
4. When the SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit = 0, or
stops in the low state if the SMi4 bit = 1.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.2.1
17. Serial Interface
SI/Oi Operation Timing
Figure 17.40 shows the SI/Oi Operation Timing
.
0.5 to 1.0 cycle (max.) (2)
SI/Oi internal clock “H”
“L”
“H”
“L”
CLKi output
Signal written to
SiTRR register
SOUTi output
“H”
“L”
SINi input
“H”
“L”
IR bit in
SiIC register
“1”
“0”
D0
D1
D2
D3
D4
D5
D6
D7
i = 3, 4
NOTES :
1. This diagram applies to the case where the SiC register bits are set as follows:
SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data output at the falling edge and receive
data input at the rising edge of the transfer clock), SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock)
Bits SM26 (SOUT3) and SM27 (SOUT4) in the S34C2 register are 0 (high-impedance after transmission).
2. If the SMi6 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 0.5 to 1.0 transfer clock cycles after
writing to the SiTRR register.
Figure 17.40 SI/Oi Operation Timing
17.2.2
CLK Polarity Selection
The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 17.41 shows
the Polarity of Transfer Clock
(1) When the SMi4 bit in the SiC register = 0
CLKi
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
SINi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the SMi4 bit = 1
CLKi
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
SINi
D0
D1
D2
D3
D4
D5
D6
D7
i = 3, 4
NOTES:
This diagram applies to the case where the SiC register bits are set as follows:
1. When the SMi5 = 0 (LSB first) and the SMi6 = 1 (internal clock)
2. When the SMi6 bit =1 (internal clock), high level is output from the CLKi pin if not transferring data.
3. When the SMi6 bit =1
Figure 17.41 Polarity of Transfer Clock
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.2.3
17. Serial Interface
Functions for Setting an SOUTi Initial Value
If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low
when not transferring. However, the last bit value of the former data is retained between data and data
when transmitting data consecutively. Figure 17.42 shows the timing chart for setting an SOUTi initial
value and how to set it.
(Example) When “H” Selected for SOUTi Initial Value (1)
Signal written to
SiTRR register
Initial value setting of SOUTi output
and
starting of transmission / reception
SMi7 bit
Set the SMi3 bit to 0
(SOUTi pin functions as an I/O port)
SMi3 bit
SOUTi (internal)
SOUTi pin output
(i = 3, 4)
Port output
D0
Set the SMi7 bit to 1
(SOUTi initial value = “H”)
D0
Set the SMi3 bit to 1
(SOUTi pin functions as SOUTi output)
Initial value = “H” (3)
Setting the SOUTi
initial value to “H” (2)
Port selection switching
(I/O port → SOUTi)
NOTES:
This diagram applies to the case where the bits in the SiC register are set as follows:
1. SMi2 = 0 (SOUTi output), SMi5 = 0 (LSB first) and SMi6 = 0 (external clock)
2. SOUTi can only be initialized when input on the CLKi pin is in the high state if the
SMi4 bit in the SiC register = 0 (transmit data output at the falling edge of the transfer clock)
or in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
3. If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.
Figure 17.42 SOUTi Initial Value Setting
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Oct 12, 2007
“H” level is output from the SOUTi pin
Write to the SiTRR register
Serial transmit / reception starts
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
17.2.4
17. Serial Interface
Functions for Selecting SOUTi State after Transmission
If bits SM26 and SM27 in the S34C2 register = 1 (last bit level retained), output from the SOUTi pin
retains the last bit level after transmission. Figure 17.43 shows the Level of SOUT3 Pin after Transmission.
SI/O internal clock
“H”
“L”
“H”
CLK3 output
SOUT3
output
“L”
When SM26 = 0
(high-impedance)
D6
D7
When SM26 = 1
(last bit level retained)
D6
D7
The above SOUT3 example applies to the case where
The SM32 bit in the S3C register = 0 (SOUT3 output),
The SM33 bit in the S3C register = 1 (SOUT3 output, CLK3 selected),
The SM34 bit in the S3C register = 0 (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock),
The SM35 bit in the S3C register = 0 (LSB first), and
The SM36 bit in the S3C register = 1 (internal clock)
Figure 17.43 Level of SOUT3 Pin after Transmission
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
18. A/D Converter
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method.
The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6, P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using these inputs, make sure the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the ADSTBY bit to 0 (A/D operation stop: standby), so that no current
will flow for the A/D converter, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register for pins ANi, AN0_i, and AN2_i (i = 0 to 7).
Table 18.1 shows the A/D Converter Specifications. Figure 18.1 shows the A/D Converter Block Diagram,
and Figures 18.2 and 18.3 show the A/D converter-related registers.
Table 18.1
A/D Converter Specifications
Item
A/D Conversion
Method
Analog Input Voltage
Performance
Successive approximation
0V to AVCC (VCC1)
(1)
Operating clock φAD
fAD, divide-by-2 of fAD, divide-by-3 of fAD, divide-by-4 of fAD, divide-by-6 of fAD,
divide-by-12 of fAD
Resolution
10-bit
Integral Nonlinearity
When AVCC = VREF = 5V
Error
AN0 to AN7 input, AN0_0 to AN0_7 input or AN2_0 to AN2_7 input: ±3LSB
ANEX0 or ANEX1 input: ±3LSB
When AVCC = VREF = 3.0V
AN0 to AN7 input, AN0_0 to AN0_7 input or AN2_0 to AN2_7 input: ±3LSB
ANEX0 or ANEX1 input: ±3LSB
Operating Modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
Analog Input Pins
+ 8 pins (AN2_0 to AN2_7)
A/D Conversion Start • Software trigger
Condition
The ADST bit in the ADCON0 register is set to 1 (A/D conversion start)
• External trigger (retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is set
to 1
(A/D conversion start)
Conversion Speed per 43 φAD cycles minimum
Pin
(1)
NOTES:
1. Set φAD frequency as follows:
When VCC1 = 4.0 to 5.5 V, 2 MHz ≤ φAD ≤ 25 MHz
When VCC1 = 3.2 to 4.0 V, 2 MHz ≤ φAD ≤ 16 MHz
When VCC1 = 3.0 to 3.2 V, 2 MHz ≤ φAD ≤ 10 MHz
REJ09B0392-0064 Rev.0.64
Page 230 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
0
f1
A/D conversion rate selection
CKS2
1/2
fAD
fAD
1/3
1
1
0
0
1/2
CKS1
φAD
CKS0
1
0
Software trigger
Trigger
1
ADTRG
TRG
0
VREF
AVSS
Analog circuit
1
ADSTBY
Successive conversion register
ADCON1 register
ADCON0 register
AD0 register (16 bits)
AD1 register (16 bits)
AD2 register (16 bits)
AD3 register (16 bits)
AD4 register (16 bits)
AD5 register (16 bits)
AD6 register (16 bits)
AD7 register (16 bits)
Decoder
for register
Data bus (high-order)
ADCON2 register
Data bus (low-order)
PM00
PM01
Vref
(1)
Decoder
for channel
selection
Port P10 group
Port P0 group
PM01 and PM00 = 00b (1)
ADGSEL1.0 ANEX1.0
= 00b
= 10b
= 10b
= 00b
= 00b
= 10b
= 10b
= 00b
= 10b
= 00b
= 10b
= 00b
= 10b
= 00b
= 10b
= 00b
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
CH2 to CH0
= 000b
= 001b
= 010b
= 011b
= 100b
= 101b
= 110b
= 111b
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
VIN
ADGSEL1.0 ANEX1.0
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
CH2 to CH0
= 000b
= 001b
= 010b
= 011b
= 100b
= 101b
= 110b
= 111b
Port P2 group
PM01 and PM00 = 00b
ADGSEL1.0
= 11b
AN2_0
= 11b
AN2_1
= 11b
AN2_2
= 11b
AN2_3
= 11b
AN2_4
= 11b
AN2_5
= 11b
AN2_6
= 11b
AN2_7
ANEX1.0
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
= 00b
CH2 to CH0
= 000b
= 001b
= 010b
= 011b
= 100b
= 101b
= 110b
= 111b
ADEX1 to ADEX0 = 01b
ANEX0
ADEX1 to ADEX0 = 10b
ANEX1
NOTE :
1. Port P0 group (AN0_0 to AN0_7) can be used as analog input pins even when bits PM01 and PM00 are set to 01b
(memory expansion mode) and bits PM05 and PM04 are set to 11b (multiplex bus allocated to the entire CS space).
Figure 18.1
A/D Converter Block Diagram
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Oct 12, 2007
Comparator
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Bit Name
Bit Symbol
CH0
Address
03D6h
After Reset
00000XXXb
Function
RW
Analog input pin select bit Function varies with each operation mode
CH1
RW
CH2
MD0
RW
RW
A/D operation mode select
bit 0
MD1
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or
repeat sweep mode 1
RW
RW
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion stop
1 : A/D conversion start
RW
CKS0
Frequency select bit 0
Refer to NOTE 3 of the ADCON2 Register
RW
NOTE :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Bit Name
Bit Symbol
SCAN0
Address
03D7h
A/D sweep pin select bit
After Reset
0000X000b
Function
Function varies with each operation mode
SCAN1
MD2
—
(b3)
No register bit. If necessary, set to 0. Read as undefined value
Frequency select bit 1
ADSTBY A/D standby bit (2)
ADEX0
RW
RW
0 : Any mode other than repeat sweep mode
A/D operation mode select
1
bit 1
1 : Repeat sweep mode 1
CKS1
RW
Extended pin select bit
ADEX1
RW
—
Refer to NOTE 3 of the ADCON2 Register
RW
0 : A/D operation stopped (standby)
1 : A/D operation enabled
RW
Function varies with each operation mode
RW
RW
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the ADSTBY bit is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1 φAD
cycle or more before starting A/D conversion.
Figure 18.2
Registers ADCON0 and ADCON1
REJ09B0392-0064 Rev.0.64
Page 232 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
0 0 0
After Reset
0000X00Xb
Bit Name
Bit Symbol
—
(b0)
Address
03D4h
Function
RW
No register bit. If necessary, set to 0. Read as undefined value
ADGSEL0
A/D input group select bit
ADGSEL1
—
(b3)
b2 b1
0 0 : Select port P10 group
0 1 : Do not set
1 0 : Select port P0 group
1 1 : Select port P2 group
No register bit. If necessary, set to 0. Read as undefined value
CKS2
—
(b7-b5)
—
RW
RW
—
Frequency select bit 2 (2)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
RW
Reserved bits
Set to 0
RW
NOTES :
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. φAD frequency is selected by a combination of the CKS0 bit in the ADCON0 register, the CKS1 bit in
the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
CKS1
CKS0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
1
A/D Register (i = 0 to 7)
(b8)
b0 b7
(b15)
b7
0
b0
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
φAD
fAD divided by 4
fAD divided by 2
fAD
fAD divided by 12
fAD divided by 6
fAD divided by 3
Address
03C1h to 03C0h
03C3h to 03C2h
03C5h to 03C4h
03C7h to 03C6h
03C9h to 03C8h
03CBh to 03CAh
03CDh to 03CCh
03CFh to 03CEh
After Reset
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
000000XXb, XXXXXXXXb
Function
Eight low-order bits of A/D conversion result
RO
Two high-order bits of A/D conversion result
RO
No register bits. If necessary, set to 0. Read as undefined value
—
Reserved bit
RO
NOTE :
1. Use the MOV instruction to write to this register.
Figure 18.3
Registers ADCON2 and AD0 to AD7
REJ09B0392-0064 Rev.0.64
Page 233 of 373
RW
Oct 12, 2007
Set to 0
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.1
18. A/D Converter
Mode Description
18.1.1
One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table
18.2 shows the One-Shot Mode Specifications. Figure 18.4 shows the Registers ADCON0 and
ADCON1 (One-shot Mode).
Table 18.2
One-Shot Mode Specifications
Item
Function
A/D Conversion Start Condition
A/D Conversion Stop Condition
Interrupt Request Generation Timing
Analog Input Pin
Reading of Result of A/D
Converter
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Specification
Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 and
ADGSEL0 in the ADCON2 register, or bits ADEX1 and ADEX0 in the
ADCON1 register select a pin. Analog voltage applied to the pin is converted to a digital code once.
• When the TRG bit in the ADCON0 register is 0 (software trigger)
the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)
• When the TRG bit is 1 (ADTRG trigger)
input on the ADTRG pin changes state from high to low after the ADST bit
is set to 1 (A/D conversion start)
• Completion of A/D conversion (The ADST bit is cleared to 0 (A/D conversion stop))
• Set the ADST bit to 0
Completion of A/D conversion
Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
ANEX0, and ANEX1
Read one of the registers AD0 to AD7 that corresponds to the selected pin
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
ADCON0
Address
03D6h
Bit Name
Bit Symbol
Function
b2
CH0
CH1
Analog input pin select bit (2)
CH2
MD0
MD1
After Reset
00000XXXb
0
0
0
0
1
1
1
1
b4
A/D operation mode select
bit 0
0
b1
0
0
1
1
0
0
1
1
RW
b0
RW
0 : Select AN0
1 : Select AN1
0 : Select AN2
1 : Select AN3
0 : Select AN4
1 : Select AN5
0 : Select AN6
1 : Select AN7
RW
RW
b3
RW
0 : One-shot mode
RW
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion stop
1 : A/D conversion start
RW
CKS0
Frequency select bit 0
Refer to NOTE 3 of the ADCON2
Register
RW
NOTES :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits ADGSEL1
and ADGSEL0 in the ADCON2 register to select the desired pin.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Bit Name
Bit Symbol
SCAN0
Address
03D7h
A/D sweep pin select bit
After Reset
0000X000b
Function
Invalid in one-shot mode
SCAN1
RW
RW
MD2
A/D operation mode select Set to 0 when one-shot mode is selected
bit 1
—
(b3)
No register bit. If necessary, set to 0. Read as undefined value
CKS1
RW
Frequency select bit 1
ADSTBY A/D standby bit (2)
ADEX0
Extended pin select bit
ADEX1
RW
—
Refer to NOTE 3 of the ADCON2 Register
RW
Set to 1 (A/D operation enabled)
RW
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : Do not set
RW
RW
NOTES :
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the ADSTBY bit is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1
φAD cycle or more before starting A/D conversion.
Figure 18.4
Registers ADCON0 and ADCON1 (One-shot Mode)
REJ09B0392-0064 Rev.0.64
Page 235 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.1.2
18. A/D Converter
Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table
18.3 shows the Repeat Mode Specifications. Figure 18.5 shows the Registers ADCON0 and ADCON1
(Repeat Mode).
Table 18.3
Repeat Mode Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pin
Reading of Result of A/D
Converter
REJ09B0392-0064 Rev.0.64
Page 236 of 373
Specification
Bits CH2 to CH0 in the ADCON0 register and bits ADGSEL1 and
ADGSEL0 in the ADCON2 register, or bits ADEX1 and ADEX0 in the
ADCON1 register select a pin. Analog voltage applied to this pin is repeatedly converted to a digital code.
• When the TRG bit in the ADCON0 register is 0 (software trigger)
the ADST bit in the ADCON0 register is set to 1 (A/D conversion start)
• When the TRG bit is 1 (ADTRG trigger)
input on the ADTRG pin changes state from high to low after the ADST bit
is set to 1 (A/D conversion start)
Set the ADST bit to 0 (A/D conversion stop)
No interrupt requests generated
Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
ANEX0, and ANEX1
Read one of the registers AD0 to AD7 that corresponds to the selected pin
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Symbol
ADCON0
Address
03D6h
Bit Name
Bit Symbol
Function
CH0
CH1
Analog input pin select bit (2)
CH2
MD0
MD1
After Reset
00000XXXb
A/D operation mode select
bit 0
RW
b2 b1 b0
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN7
RW
RW
RW
b4 b3
0 1 : Repeat mode
RW
RW
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion stop
1 : A/D conversion start
RW
CKS0
Frequency select bit 0
Refer to NOTE 3 of the ADCON2 Register RW
NOTES :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits
ADGSEL1 and ADGSEL0 in the ADCON2 register to select the desired pin.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
Bit Name
Bit Symbol
SCAN0
Address
03D7h
A/D sweep pin select bit
After Reset
0000X000b
Function
Invalid in repeat mode
SCAN1
RW
RW
MD2
A/D operation mode select Set to 0 when repeat mode is selected
bit 1
—
(b3)
No register bit. If necessary, set to 0. Read as undefined value
CKS1
RW
Frequency select bit 1
ADSTBY A/D standby bit (2)
ADEX0
Extended pin select bit
ADEX1
RW
—
Refer to NOTE 3 of the ADCON2 Register
RW
Set to 1 (A/D operation enabled)
RW
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : Do not set
RW
RW
NOTES :
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. When the ADSTBY bit is reset from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1
φAD cycle or more before starting A/D conversion.
Figure 18.5
Registers ADCON0 and ADCON1 (Repeat Mode)
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.1.3
18. A/D Converter
Single Sweep Mode
In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 18.4 shows the Single Sweep Mode Specifications. Figure 18.6 shows Registers
ADCON0 and ADCON1 (Single Sweep Mode).
Table 18.4
Single Sweep Mode Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pin
Reading of Result of A/D
Converter
Specification
Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and
ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to
the pins is converted one-by-one to a digital code.
• When the TRG bit in the ADCON0 register is 0 (software trigger)
the ADST bit in the ADCON0 register is set to 1 (A/D conversion start)
• When the TRG bit is 1 (ADTRG trigger)
input on the ADTRG pin changes state from high to low after the ADST bit
is set to 1 (A/D conversion start)
• Completion of A/D conversion (The ADST bit is cleared to 0 (A/D conversion stop))
• Set the ADST bit to 0
Completion of A/D conversion
Select from AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6
pins), and AN0 to AN7 (8 pin) (1)
Read one of the registers AD0 to AD7 that corresponds to the selected pin
NOTE:
1. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Symbol
ADCON0
Address
03D6h
Bit Name
Bit Symbol
Function
CH0
CH1
Analog input pin select bit (2)
CH2
MD0
MD1
After Reset
00000XXXb
RW
b2 b1 b0
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN7
RW
RW
RW
b4 b3
0 1 : Repeat mode
A/D operation mode select
bit 0
RW
RW
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion stop
1 : A/D conversion start
RW
CKS0
Frequency select bit 0
Refer to NOTE 3 of the ADCON2 Register RW
NOTES :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits
ADGSEL1 and ADGSEL0 in the ADCON2 register to select the desired pin.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
ADCON1
Address
03D7h
After Reset
0000X000b
Bit Name
Bit Symbol
Function
When repeat sweep mode 1 is selected
SCAN0
b1
A/D sweep pin select bit (2)
SCAN1
0
0
1
1
b0
0 : AN0 (1 pin)
1 : AN1 (2 pins)
0 : AN2 (3 pins)
1 : AN3 (4 pins)
MD2
A/D operation mode select
1 : Repeat sweep mode 1
bit 1
—
(b3)
No register bit. If necessary, set to 0. Read as undefined value
CKS1
Frequency select bit 1
ADSTBY A/D standby bit (3)
Extended pin select bit
ADEX1
RW
RW
RW
—
Refer to NOTE 3 of the ADCON2 Register
RW
Set to 1 (A/D operation enabled)
RW
b7
ADEX0
RW
0
0
1
1
b6
0 : ANEX0 and ANEX1 are not used
1 : Do not set
0 : Do not set
1 : Do not set
RW
RW
NOTES :
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits
ADGSEL1 and ADGSEL0 in the ADCON2 register to select the desired pin.
3. If the ADSTBY bit is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1
φAD cycle or more before starting A/D conversion.
Figure 18.6
Registers ADCON0 and ADCON1 (Single Sweep Mode)
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.1.4
18. A/D Converter
Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital
code.
Table 18.5 shows the Repeat Sweep Mode 0 Specifications. Figure 18.7 shows Registers ADCON0
and ADCON1 (Repeat Sweep Mode 0).
Table 18.5
Repeat Sweep Mode 0 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pin
Reading of Result of A/D
Converter
Specification
Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and
ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to
the pins is repeatedly converted to a digital code.
• When the TRG bit in the ADCON0 register is 0 (software trigger)
the ADST bit in the ADCON0 register is set to 1 (A/D conversion start)
• When the TRG bit is 1 (ADTRG trigger)
input on the ADTRG pin changes state from high to low after the ADST bit
is set to 1 (A/D conversion start)
Set the ADST bit to 0 (A/D conversion stop)
No interrupt requests generated
Select from AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6
pins), and AN0 to AN7 (8 pin) (1)
Read one of the registers AD0 to AD7 that corresponds to the selected pin
NOTE:
1. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
Bit Name
Bit Symbol
Function
RW
CH0
CH1
RW
Analog input pin select bit Invalid in repeat sweep mode 0
CH2
MD0
MD1
RW
RW
A/D operation mode select
bit 0
b4
1
RW
b3
1 : Repeat sweep mode 0 or
repeat sweep mode 1
RW
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion stop
1 : A/D conversion start
RW
CKS0
Frequency select bit 0
Refer to NOTE 3 of the ADCON2 Register
RW
NOTE :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
ADCON1
SCAN1
After Reset
0000X000b
Bit Name
Bit Symbol
SCAN0
Address
03D7h
Function
When repeat sweep mode 0 is selected
b1
0
A/D sweep pin select bit (2) 0
1
1
b0
0 : AN0 to AN1 (2 pins)
1 : AN0 to AN3 (4 pins)
0 : AN0 to AN5 (6 pins)
1 : AN0 to AN7 (8 pins)
MD2
A/D operation mode select
bit 1
—
(b3)
No register bit. If necessary, set to 0. Read as undefined value
CKS1
Frequency select bit 1
ADSTBY A/D standby bit (3)
Set to 0 when repeat sweep mode 0 is
selected
Extension pin select bit
ADEX1
RW
RW
RW
—
Refer to NOTE 3 of the ADCON2 Register
RW
Set to 1 (A/D operation enabled)
RW
b7
ADEX0
RW
0
0
1
1
b6
0 : ANEX0 and ANEX1 are not used
1 : Do not set
0 : Do not set
1 : Do not set
RW
RW
NOTES :
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits
ADGSEL1 and ADGSEL0 in the ADCON2 register to select the desired pin.
3. If the ADSTBY bit is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1
φAD cycle or more before starting A/D conversion.
Figure 18.7
Registers ADCON0 and ADCON1 (Repeat Sweep Mode 0)
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.1.5
18. A/D Converter
Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code. Table 18.6 shows the Repeat Sweep Mode 1 Specifications. Figure 18.8 shows Registers
ADCON0 and ADCON1 (Repeat Sweep Mode 1).
Table 18.6
Repeat Sweep Mode 1 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation timing
Analog Input Pins to be
Given Priority When A/D
Converted
Reading of Result of A/D
Converter
Specification
The input voltages on all pins selected by bits ADGSEL1 and ADGSEL0 in
the ADCON2 register are A/D converted repeatedly, with priority given to
pins selected by bits SCAN1 and SCAN0 in the ADCON1 register and bits
ADGSEL1 and ADGSEL0.
Example:
If AN0 selected, input voltages are A/D converted in order of
AN0→AN1→AN0→AN2→AN0→AN3, and so on.
• When the TRG bit in the ADCON0 register is 0 (software trigger),
the ADST bit in the ADCON0 register is set to 1 (A/D conversion start)
• When the TRG bit is 1 (ADTRG trigger),
input on the ADTRG pin changes state from high to low after the ADST
bit is set to 1 (A/D conversion start)
Set the ADST bit to 0 (A/D conversion stop)
No interrupt requests generated
Select from AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins),
and AN0 to AN3 (4 pins) (1)
Read one of the registers AD0 to AD7 that corresponds to the selected pin
NOTES:
1. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
1 1
Address
After Reset
00000XXXb
03D6h
Bit Name
Bit Symbol
Function
RW
CH0
CH1
RW
Analog input pin select bit Invalid in repeat sweep mode 1
CH2
RW
RW
A/D operation mode select
bit 0
b4 b3
1 1 : Repeat sweep mode 0 or
repeat sweep mode 1
RW
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion stop
1 : A/D conversion start
RW
CKS0
Frequency select bit 0
Refer to NOTE 3 of the ADCON2 Register
RW
MD0
MD1
RW
NOTE :
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol
ADCON1
1
Address
03D7h
Bit Name
Bit Symbol
Function
When repeat sweep mode 1 is selected
SCAN0
SCAN1
After Reset
0000X000b
b1
0
A/D sweep pin select bit (2) 0
1
1
b0
0 : AN0 (1 pin)
1 : AN1 (2 pins)
0 : AN2 (3 pins)
1 : AN3 (4 pins)
MD2
A/D operation mode select
1 : Repeat sweep mode 1
bit 1
—
(b3)
No register bit. If necessary, set to 0. Read as undefined value
CKS1
Frequency select bit 1
ADSTBY A/D standby bit (3)
Extended pin select bit
ADEX1
RW
RW
RW
—
Refer to NOTE 3 of the ADCON2 Register
RW
Set to 1 (A/D operation enabled)
RW
b7
ADEX0
RW
0
0
1
1
b6
0 : ANEX0 and ANEX1 are not used
1 : Do not set
0 : Do not set
1 : Do not set
RW
RW
NOTES :
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN0_7 and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7. Use bits
ADGSEL1 and ADGSEL0 in the ADCON2 register to select the desired pin.
3. If the ADSTBY bit is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1
φAD cycle or more before starting A/D conversion.
Figure 18.8
Registers ADCON0 and ADCON1 (Repeat Sweep Mode 1)
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.2
18. A/D Converter
Conversion Rate
The conversion rate is defined as follows.
Start dummy time depends on which φAD is selected. Table 18.7 shows Start Dummy Time. When the
ADST bit in the ADCON0 register is set to 1 (A/D conversion start), A/D conversion starts after start
dummy time elapses. 0 (A/D conversion stop) is read if the ADST bit is read before A/D conversion starts.
For multiple pins or A/D conversion repeat mode, for each pin, between-execution dummy time is inserted
between A/D conversion execution time and the next A/D conversion execution time.
The ADST bit is set to 0 during the end dummy time, and the last A/D conversion result is set to the ADi
register in one-shot mode and single sweep mode.
While in one-shot mode:
Start dummy time + A/D conversion execution time + end dummy time
When two pins are selected while in single sweep mode:
Start dummy time + (A/D conversion execution time + between-execution dummy time + A/D conversion
execution time) + end dummy time
Start dummy time: See Table 18.7 “Start Dummy Time”
A/D conversion execution time: 40 φAD cycles per pin
Between-execution dummy time: 1 φAD cycle
End dummy time: 2 to 3 cycles of fAD
Table 18.7
Start Dummy Time
φAD Selection
fAD
fAD divided by 2
fAD divided by 3
fAD divided by 4
fAD divided by 6
fAD divided by 12
18.3
Start Dummy Time
1 to 2 cycles of fAD
2 to 3 cycles of fAD
3 to 4 cycles of fAD
3 to 4 cycles of fAD
4 to 5 cycles of fAD
7 to 8 cycles of fAD
Extended Analog Input Pins
In one-shot and repeat modes, pins ANEX0 and ANEX1 can be used as analog input pins. Use bits
ADEX1 and ADEX0 in the ADCON1 register to select whether or not to use ANEX0 and ANEX1.
The A/D conversion results of ANEX0 and ANEX1 inputs are stored in registers AD0 and AD1, respectively.
18.4
Current Consumption Reducing Function
When not using the A/D converter, power consumption can be reduced by setting the ADSTBY bit in the
ADCON1 register to 0 (A/D operation stopped: standby) to shut off any analog circuit current flow.
To use the A/D converter, set the ADSTBY bit to 1 (A/D operation enabled) after operating longer than
one cycle of a timer count source, and then set the ADST bit in the ADCON0 register to 1 (A/D conversion
start). Do not set bits ADST and ADSTBY to 1 at the same time.
Also, do not set the ADSTBY bit to 0 (A/D operation stopped: standby) during A/D conversion.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
18.5
18. A/D Converter
Output Impedance of Sensor under A/D Conversion
Microcomputer
Sensor equivalent
circuit
R0
R (10.0 kW)
VIN
C (10.0 pF)
VC
Figure 18.9
Sampling time
15
∅AD
Analog Input Pin and External Sensor Equivalent Circuit
REJ09B0392-0064 Rev.0.64
Page 245 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
19. D/A Converter
19. D/A Converter
19.1
Summary
The D/A converter consists of two independent 8-bit R-2R type D/A converters.
D/A conversion is performed by writing to the DAi register (i = 0 to 1). To output the result of conversion,
set the DAiE bit in the DACON register to 1 (output enabled). Before using D/A conversion, clear the corresponding port direction bit to 0 (input mode). When the DAiE bit is set to 1 (input enabled), pull-up of a
corresponding port is disabled.
Output analog voltage (V) is determined by a set value (n: decimal) in the DAi register.
n (n = 0 to 255)
V = VREF × --------256
VREF: reference voltage
Table 19.1 lists the D/A Converter Performance. Figure 19.1 shows the D/A Converter Block Diagram.
Figure 19.2 shows Registers DACON, DA0, and DA1. Figure 19.3 shows the D/A Converter Equivalent
Circuit.
Table 19.1
D/A Converter Performance
Item
D/A Conversion Method
Resolution
Analog Output Pin
Performance
R-2R
8 bits
2 channels (DA0 and DA1)
Low-Order Bits of Data Bus
DA0 register
0
DA0
R-2R resistor ladder
1
DA0E bit
DA1 register
0
R-2R resistor ladder
DA1
1
DA1E bit
Figure 19.1
D/A Converter Block Diagram
REJ09B0392-0064 Rev.0.64
Page 246 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
19. D/A Converter
D/A Control Register (1)
Address
03DCh
Symbol
DACON
b7 b6 b5 b4 b3 b2 b1 b0
After Reset
00h
Bit Name
Bit Symbol
Function
RW
DA0E
D/A 0 output enable bit
0 : Output disabled
1 : Output enabled
RW
DA1E
D/A 1 output enable bit
0 : Output disabled
1 : Output enabled
RW
—
(b7-b2)
No register bits. If necessary, set to 0. Read as 0
—
NOTE :
1. When not using the D/A converter, clear the DAiE bit (i = 0 to 1) to 0 (output disabled) to reduce the
unnecessary current consumption in the chip and set the DAi register to 00h to prevent current from flowing
into the R-2R resistor ladder.
D/Ai Register (i = 0 to 1) (1)
b0
b7
Symbol
Address
DA0
DA1
03D8h
03DAh
After Reset
00h
00h
Function
Output value of D/A conversion
Setting Range
RW
00h to FFh
RW
NOTE :
1. When not using the D/A converter, clear the DAiE bit (i = 0 to 1) to 0 (output disabled) to reduce the
unnecessary current consumption in the chip and set the DAi register to 00h to prevent current from flowing
into the R-2R resistor ladder.
Figure 19.2
Registers DACON, DA0, and DA1
DAiE bit
0
r
DAi
R
R
R
R
R
R
R
2R
1
2R
2R
2R
0
1
AVSS
VREF (2)
i = 0 to 1
NOTES:
1. The above diagram applies when the DAi register is set to 2Ah.
2. VREF is not related to ADSTBY bit in the AD0CON1 register.
Figure 19.3
2R
2R
2R
2R
LSB
MSB
DAi register
2R
D/A Converter Equivalent Circuit
REJ09B0392-0064 Rev.0.64
Page 247 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
20. CRC Operation
20. CRC Operation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a
generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit
units. After the initial value is set in the CRCD register, the CRC code is set in that register each time one
byte of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two
cycles.
Figure 20.1 shows the CRC Circuit Block Diagram. Figure 20.2 shows Registers CRCD and CRCIN.
Figure 20.3 shows an example using the CRC Operation.
Data bus (high-order)
Data bus (low-order)
Eight low-order bits
Eight high-order bits
CRCD register
CRC code generating circuit
X16 + X12 + X5 + 1
CRCIN register
Figure 20.1
CRC Circuit Block Diagram
CRC Data Register
(b15)
(b8)
b7
b0 b7
b0
Symbol
Address
After Reset
CRCD
03BDh to 03BCh
Indeterminate
Function
Setting Range
RW
When data is written to the CRCIN register after setting the
initial value in the CRCD register, the CRC code can be
read out from the CRCD register.
0000h to FFFFh
RW
CRC Input Register
b7
b0
Symbol
Address
After Reset
CRCIN
03BEh
Indeterminate
Function
Data input
Figure 20.2
Registers CRCD and CRCIN
REJ09B0392-0064 Rev.0.64
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Setting Range
RW
00h to FFh
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
20. CRC Operation
Setup procedure and CRC operation when generating CRC code “80C4h”
• CRC operation performed by the M16C
CRC code
: remainder of a division in which the value written to the CRCIN register with its bit positions reversed is divided
by the generator polynomial
Generator polynomial : X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b)
• Setting procedure
(1) Reverse the bit positions of the value “80C4h” by program in 1-byte units.
80h
01h, C4h
23h
b15
b0
(2) Write 0000h (initial value)
CRCD register
b7
b0
(3) Write 01h
b0
b15
CRCIN register
Two cycles later, the CRC code for 80h, i.e., 9188h, has its bit
positions reversed to become 1189h which is stored in the CRCD
register.
CRCD register
1189h
b7
b0
(4) Write 23h
b15
b0
CRCIN register
Two cycles later, the CRC code for 80C4h, i.e., 8250h, has its bit
positions reversed to become 0A41h which is stored in the CRCD
register.
CRCD register
0A41h
• Details of CRC operation
As shown in (3) above, bit position of 01h (00000001b) written to the CRCIN register is reversed and becomes 10000000b.
Add 1000 0000 0000 0000 0000 0000b, as 10000000b plus 16 digits, to 0000 0000 0000 0000 0000 0000b,
as 0000 0000 0000 0000b plus 8 digits as the default value of the CRCD register to perform the modulo-2 division.
1 0001 0000 0010 0001 1000 0000 0000 0000
1000 1000 0001 0000
1000 0001 0000
Generator polynomial
1000 1000 0001
1001 0001
1000
0000
1
1000
0000
1000
1000
0000
0
1
1000
Data
Modulo-2 operation is
operation that complies
with the law given below.
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
CRC code
0001 0001 1000 1001b (1189h), the remainder 1001 0001 1000 1000b (9188h) with inversed bit position, can
be read from the CRCD register.
When going on to (4) above, 23h (00100011b) written in the CRCIN register is reversed and becomes 11000100b.
Add 1100 0100 0000 0000 0000 0000b, as 11000100b plus 16 digits, to 1001 0001 1000 1000 0000 0000b, as 1001 0001 1000 1000b
plus 8 digits as a remainder of (3) left in the CRCD register to perform the modulo-2 division.
0000 1010 0100 0001b (0A41h), the remainder with reversed bit position, can be read from the CRCD register.
Figure 20.3
CRC Operation
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
21. Programmable I/O Ports
88 programmable input / output ports (I/O ports) are available. The direction registers determine individual
port status, input or output. The pull-up control registers determine whether the pots, divided into groups of
four ports, are pulled up or not. P8_5 is an input port and no pull-up is allowed. Port P8_5 shares the pin
with NMI, so that the NMI input level can be read from the P8_5 bit in the P8 register.
Figures 21.1 to 21.5 show the I/O ports. Figure 21.6 shows the I/O Pins.
Each pin functions as an I/O port, a peripheral function input / output, or a bus control pin.
To set peripheral functions, refer to the description for individual functions. If any pin is used as a peripheral
function input or D/A converter output pin, set the direction bit of the corresponding pin to 0 (input mode).
Any pin used as an output pin for peripheral functions other than the D/A converter is directed for output no
matter how the corresponding direction bit is set.
To use as bus control pins, refer to 8.2 “Bus Control”.
P0 to P5 are capable of VCC2-level input / output; P6 to P10 are capable of VCC1- level input / output.
21.1
Port Pi Direction Register (PDi Register, i = 0 to 10)
Figure 21.7 shows the Pi Direction Registers.
This register selects whether the I/O port is to be used for input or output. Each bit in the PDi register corresponds to one port.
During memory extension or microprocessor mode, the PDi registers for the pins functioning as bus control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL / WR, WRH / BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
21.2
Port Pi Register (Pi Register, i = 0 to 10)
Figure 21.8 shows the Pi Registers.
Data input / output to and from external devices are accomplished by reading and writing to the Pi register.
Each bit of the Pi register consists of a port latch to hold the output data and a circuit to read the pin status.
For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register. The data written to the port latch is output
from the pin. Each bit in the Pi register correspond to each port.
During memory extension or microprocessor mode, the Pi registers for the pins functioning as bus control
pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL / WR, WRH / BHE, ALE, RDY, HOLD, HLDA, and
BCLK) cannot be modified.
21.3
Pull-up Control Register 0 to Pull-up Control Register 2 (Registers PUR0 to
PUR2)
Figures 21.9 and 21.10 show the Registers PUR0 to PUR2.
Bits in registers PUR0 to PUR2 can be used to select whether or not to pull the corresponding port high in
4 pin units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit
is set for input mode.
However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory
extension or microprocessor mode. Although the register contents can be modified, no pull-up resistors
are connected.
21.4
Port Control Register (PCR Register)
Figure 21.11 shows the PCR Register.
When the P1 register is read after setting the PCR0 bit in the PCR register to 1, the corresponding port
latch can be read no matter how the PD1 register is set.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Pull-up selection
P0_0 to P0_7,
P2_0 to P2_3,
P2_6 to P2_7,
P10_0 to P10_3
P3_0 to P3_7,
P4_0 to P4_3,
P5_0 to P5_4, P5_6
Direction
register
(dotted section
included)
Data bus
Port latch
(NOTE 1)
(dotted section
not included)
Analog input
Pull-up selection
Direction
register
P1_0
1
Port P1 control register
output
Port latch
Data bus
(NOTE 1)
Pull-up selection
Direction
register
P1_1 to P1_3
1
Port P1 control register
output
Port latch
Data bus
(NOTE 1)
CMOS / Nch
Selection
NOTE:
1.
Figure 21.1
symbolizes a parasitic diode.
Make sure the input voltage on each port will never exceed VCC.
VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
I/O Ports (1)
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Pull-up selection
Direction
register
P1_4
(dotted section not included)
P1_5 to P1_7
(dotted section included)
Port P1 control register
Port latch
Data bus
(NOTE 1)
Input to respective
peripheral functions
Pull-up selection
Direction
register
P2_4, P2_5
P10_4 to P10_7
Data bus
Port latch
(NOTE 1)
Analog input
Input to respective peripheral functions
Port control register
Pull-up selection
Direction
register
P4_4, P5_7, P6_0,
P6_4, P7_3 to P7_5,
P8_1, P9_0, P9_2
1
output
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
NOTE:
1.
Figure 21.2
symbolizes a parasitic diode.
Make sure the input voltage on each port will never exceed VCC.
VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
I/O Ports (2)
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Pull-up selection
Direction
register
P4_5 to P4_7,
P6_1 to P6_3,
P6_5 to P6_7, P7_2,
P7_6 to P7_7, P8_0
1
output
Data bus
Port latch
(NOTE 1)
CMOS / Nch
selection
Input to respective peripheral functions
Pull-up selection
Direction
register
P5_5, P8_2 to P8_4,
P9_1, P9_7
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Direction
register
P7_0, P7_1
1
output
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
NOTE:
1.
Figure 21.3
symbolizes a parasitic diode.
Make sure the input voltage on each port will never exceed VCC.
VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
I/O Ports (3)
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Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
NMI enabled
Direction
register
P8_5
Data bus
Port latch
(NOTE 1)
NMI interrupt input
NMI enabled
SD input
Pull-up selection
D/A output enabled
Direction
register
P9_3, P9_4
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Analog output
D/A output enabled
Pull-up selection
Direction
register
P9_5
(Inside dotted-line included)
P9_6
1
(Inside dotted-line not included)
output
Data bus
Port latch
(NOTE 1)
Input to respective
peripheral functions
Analog input
NOTE:
1.
Figure 21.4
symbolizes a parasitic diode.
Make sure the input voltage on each port will never exceed VCC.
VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
I/O Ports (4)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Pull-up selection
Direction
register
P8_7
Data bus
Port latch
(NOTE 1)
fC
Rf
Pull-up selection
Direction
register
P8_6
Rd
1
output
Data bus
Port latch
(NOTE 1)
NOTE:
1.
Figure 21.5
symbolizes a parasitic diode.
Make sure the input voltage on each port will never exceed VCC.
VCC: VCC1 for ports P6 to P10, and VCC2 for ports P0 to P5.
I/O Ports (5)
BYTE
BYTE signal input
(NOTE 1)
CNVSS
CNVSS signal input
(NOTE 1)
RESET
RESET signal input
NOTE:
1.
Figure 21.6
symbolizes a parasitic diode.
Make sure the input voltage on each port will never exceed VCC1.
I/O Pins
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(NOTE 1)
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Port Pi Direction Register (i = 0 to 10) (1, 2)
Symbol
b7 b6 b5 b4 b3 b2 b1 b0
Address
PD0 to PD3
PD4 to PD7
PD8
PD9, PD10
Bit Name
Bit Symbol
After Reset
00h
00h
00h
00h
03E2h, 03E3h, 03E6h, 03E7h
03EAh, 03EBh, 03EEh, 03EFh
03F2h
03F3h, 03F6h
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
PDi_0
Port Pi_0 direction bit
PDi_1
Port Pi_1 direction bit
PDi_2
Port Pi_2 direction bit
PDi_3
Port Pi_3 direction bit
RW
PDi_4
Port Pi_4 direction bit
RW
PDi_5
Port Pi_5 direction bit
RW
PDi_6
Port Pi_6 direction bit
RW
PDi_7
Port Pi_7 direction bit
RW
RW
RW
RW
NOTES :
1. Make sure the PD9 register is written following the instruction to set the PRC2 bit in the PRCR register to 1
(write enabled).
2. During memory extension and microprocessor modes, the PDi register for the pins functioning as bus control
pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL / WR, WRH / BHE, ALE, RDY, HOLD, HLDA and BCLK)
cannot be modified.
Figure 21.7
Registers PD0 to PD10
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Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Port Pi Register (i = 0 to 10) (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
P0 to P3
P4 to P7
P8
P9, P10
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
03E0h, 03E1h, 03E4h, 03E5h
03E8h, 03E9h, 03ECh, 03EDh
03F0h
03F1h, 03F4h
Bit Name
Bit Symbol
Function
RW
The pin level on any I/O port which is set
for input mode can be read by reading the
corresponding bit in this register.
The pin level on any I/O port which is set
for output mode can be controlled by
writing to the corresponding bit in this
register
0 : “L” level
1 : “H” level (1)
RW
Pi_0
Port Pi_0 bit
Pi_1
Port Pi_1 bit
Pi_2
Port Pi_2 bit
Pi_3
Port Pi_3 bit
Pi_4
Port Pi_4 bit
Pi_5
Port Pi_5 bit
Pi_6
Port Pi_6 bit
RW
Pi_7
Port Pi_7 bit
RW
NOTES :
1. Since P7_0, P7_1, and P8_5 are N-channel open drain ports, the pin status becomes high-impedance.
2. During memory extension and microprocessor modes, the Pi register for the pins functioning as bus
control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL / WR, WRH / BHE, ALE, RDY, HOLD, HLDA
and BCLK) cannot be modified.
Figure 21.8
Registers P0 to P10
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RW
RW
RW
RW
RW
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Pull-up Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
After Reset
00h
Address
0360h
Bit Name
Bit Symbol
Function
0 : Not pulled high
1 : Pulled high (2)
RW
PU00
P0_0 to P0_3 pull-up
PU01
P0_4 to P0_7 pull-up
PU02
P1_0 to P1_3 pull-up
RW
PU03
P1_4 to P1_7 pull-up
RW
PU04
P2_0 to P2_3 pull-up
RW
PU05
P2_4 to P2_7 pull-up
RW
PU06
P3_0 to P3_3 pull-up
RW
PU07
P3_4 to P3_7 pull-up
RW
RW
RW
NOTES :
1. During memory extension or microprocessor mode, the corresponding register contents can be
modified, but the pins are not pulled high.
2. The pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high.
Pull-up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
After Reset (5)
00000000b
00000010b
Address
0361h
Bit Name
Bit Symbol
Function
(2)
0 : Not pulled high
1 : Pulled high (3)
RW
PU10
P4_0 to P4_3 pull-up
PU11
P4_4 to P4_7 pull-up (4)
PU12
P5_0 to P5_3 pull-up (2)
RW
PU13
P5_4 to P5_7 pull-up (2)
RW
PU14
P6_0 to P6_3 pull-up
RW
PU15
P6_4 to P6_7 pull-up
RW
PU16
P7_2 to P7_3 pull-up (1)
RW
PU17
P7_4 to P7_7 pull-up
RW
RW
RW
NOTES :
1. Pins P7_0 and P7_1 do not have pull-ups.
2. During memory extension and microprocessor modes, the pins are not pulled high although the contents of
these bits can be modified.
3. To enable the pull-up registers, the corresponding bit in the register should be set to 1 (pulled high) and the
respective bits in the direction register should be set to 0 (input mode).
4. If bits PM01 to PM00 in the PM0 register are set to 01b (memory expansion mode) or 11b (microprocessor
mode) in a program during single-chip mode, the PU11 bit becomes 1.
5. The values after hardware reset 1 or brown-out reset is as follows:
• 00000000b when input on CNVSS pin is “L”
• 00000010b when input on CNVSS pin is “H”
The values after software reset, watchdog timer reset, and oscillation stop detection reset are as follows:
• 00000000b when bits PM01 to PM00 are 00b (single-chip mode)
• 00000010b when bits PM01 to PM00 are 01b (memory expansion mode) or 11b (microprocessor mode)
Figure 21.9
Registers PUR0 and PUR1
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Pull-up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
0362h
After Reset
00h
Bit Name
Bit Symbol
Function
RW
0 : Not pulled high
1 : Pulled high (1)
PU20
P8_0 to P8_3 pull-up
PU21
P8_4 to P8_7 pull-up (2)
PU22
P9_0 to P9_3 pull-up
RW
PU23
P9_4 to P9_7 pull-up
RW
PU24
P10_0 to P10_3 pull-up
RW
PU25
P10_4 to P10_7 pull-up
RW
—
(b7-b6)
RW
RW
No register bits. If necessary, set to 0. Read as 0
—
NOTES :
1. To enable the pull-up registers, the corresponding bit in the register should be set to 1 (pulled high) and the
respective bits in the direction register should be set to 0 (input mode).
2. The P8_5 pin does not have pull-up.
Figure 21.10 PUR2 Register
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCR
Bit Symbol
After Reset
00000XX0b
Address
0366h
Bit Name
Function
RW
Operation performed when the P1 register is
read
0 : When the port is set for input, the input
levels of pins P1_0 to P1_7 are read.
When set for output, the port latch is read.
1 : The port latch is read regardless of
whether the port is set for input or output.
RW
PCR0
Port P1 control bit
—
(b4-b1)
No register bits. If necessary, set to 0. Read as 0
PCR5
PCR6
PCR7
INT6 input enable bit (1)
0 : Enabled
1 : Disabled
RW
INT7 input enable bit (2)
0 : Enabled
1 : Disabled
RW
Key input enable bit (3)
0 : Enabled
1 : Disabled
RW
NOTES :
1. To use the AN2_4 pin as an analog input pin, set the PCR5 bit to 1 (INT6 input disabled).
2. To use the AN2_5 pin as an analog input pin, set the PCR6 bit to 1 (INT7 input disabled).
3. To use pins AN4 to AN7 as analog input pins, set the PCR7 bit to 1 (key input disabled).
Figure 21.11 PCR Register
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—
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 21.1
21. Programmable I/O Ports
Unassigned Pin Handling in Single-chip Mode
Pin Name
Ports P0 to P5
Ports P6 to P10
XOUT (4)
XIN
AVCC, VREF
AVSS, BYTE
Connection (2)
One of the followings:
Set for input mode and connect a pin to VSS via resistor (pull-down)
Set for input mode and connect a pin to VCC2 via resistor (pull-up)
Set for output mode and leave the pins open (1)
One of the followings:
Set for input mode and connect a pin to VSS via resistor (pull-down)
Set for input mode and connect a pin to VCC1 via resistor (pull-up)
Set for output mode and leave the pins open (1, 3)
Open
Connect to VCC1 (pull-up) via resistor
Connect to VCC1
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input
mode until it is switched to output mode in a program after reset. For this reason, the voltage level on
the pin becomes indeterminate, causing the power supply current to increase while the port remains
in input mode.
2. Furthermore, by considering a possibility that the contents of the direction registers could be changed
by noise or noise-induced loss of control, it is recommended that the contents of the direction registers be regularly reset in software to improve reliability of the program.
3. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
4. When the ports P7_0, P7_1, and P8_5 are set for output mode, make sure a low-level signal is output from the pins.
5. The ports P7_0, P7_1, and P8_5 are N-channel open-drain outputs.
6. This applies when external clock is input to the XIN pin or when VCC1 is connected to via a resistor.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 21.2
21. Programmable I/O Ports
Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Connection (2)
Pin Name
Ports P0 to P5
One of the followings:
Set for input mode and connect a pin to VSS via resistor (pull-down)
Set for input mode and connect a pin to VCC2 via resistor (pull-up)
Set for output mode and leave the pins open (1, 3)
Ports P6 to P10
One of the followings:
Set for input mode and connect a pin to VSS via resistor (pull-down)
Set for input mode and connect a pin to VCC1 via resistor (pull-up)
Set for output mode and leave the pins open (1, 4)
BHE, ALE, HLDA,
Open
XOUT (5), BCLK (6)
HOLD , RDY
Connect to VCC2 (pull-up) via resistor
XIN
Connect to VCC1 (pull-up) via resistor
AVCC, VREF
Connect to VCC1
AVSS
Connect to VSS
NOTES:
1. When setting the port for output mode and leave it open, be aware that the port remains in input
mode until it is switched to output mode in a program after reset. For this reason, the voltage level on
the pin becomes indeterminate, causing the power supply current to increase while the port remains
in input mode.
2. Furthermore, by considering a possibility that the contents of the direction registers could be changed
by noise or noise-induced loss of control, it is recommended that the contents of the direction registers be regularly reset in software to improve reliability of the program.
3. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
4. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor
mode is switched over in a program after reset. For this reason, the voltage levels on these pins
become indeterminate, causing the power supply current to increase while they remain set for input
ports.
5. When the ports P7_0, P7_1, and P8_5 are set for output mode, make sure a low-level signal is output from the pins.
6. The ports P7_0, P7_1, and P8_5 are N-channel open-drain outputs.
7. This applies when external clock is input to the XIN pin or when VCC1 is connected to via a resistor.
8. If the PM07 bit in the PM0 register is set to 1 (BCLK not output), connect this pin to VCC2 via a resistor (pulled high).
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
21. Programmable I/O Ports
Microcomputer
Microcomputer
Port P0 to P10
(Input mode)
Port P6 to P10
.
.
.
.
.
.
(Input mode)
(Output mode)
.
.
.
.
.
.
(Input mode)
Open
VCC1
(Output mode)
VCC2
Port P4_5 / CS1
to P4_7 / CS3
XIN
XOUT
(Input mode)
Open
Open
VCC1
XIN
BHE
HLDA
ALE
VCC1
XOUT
BCLK (1)
AVCC
HOLD
VREF
Open
VCC2
VCC1
RDY
BYTE
AVCC
AVSS
VREF
VSS
In single-chip mode
AVSS
VSS
In memory expansion mode or
in microprocessor mode
NOTE:
1. If the PM07 bit in the PM0 register is set to 1 (BCLK not output), connect this pin to VCC2 via a resistor (pulled high).
Figure 21.12 Unassigned Pin Handling
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Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
22. Flash Memory Version
The flash memory can perform in three rewrite modes: CPU rewrite mode, standard serial I/O mode, and
parallel I/O mode. Table 22.1 lists specifications of the flash memory version. See Tables 1.1 and 1.2 Specifications Overview for the items not listed in Table 22.1.
Table 22.1
Flash Memory Version Specifications
Item
Flash Memory Rewrite Mode
Erase Block
Program ROM 1
Program ROM 2
Data Flash
Program Method
Erase Method
Program and Erase Control Method
Protect Method
Number of Commands
Program and Erase Endurance
Data Retention
ROM Code Protection
Specification
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
See Figure 22.1 “Flash Memory Block Diagram”
1 block (16 Kbytes)
2 blocks (4 Kbytes each)
In units of 2 words
Block erase
Program and erase controlled by software command
The lock bit protects each block
8 commands
100 times (2, 3)
10 years
Parallel I/O and standard serial I/O modes are supported
NOTE:
1. Definition of program and erase endurance
The program and erase endurance refers to the number of per-block erasures.
For example, assume a case where a 4 Kbyte block is programmed in 1,024 operations, writing two words at a
time, and erased thereafter. In this case, the block is reckoned as having been programmed and erased once.
If the program and erase endurance is 100 times, each block can be erased up to 100 times.
Table 22.2
Flash Memory Rewrite Modes Overview
Flash Memory
Rewrite Mode
Function
CPU rewrite Mode (1)
Program ROM 1, program ROM 2, and
data flash are rewritten when the CPU
executes software commands.
EW0 mode:
Rewritable in areas other than flash
memory (2)
EW1 mode:
Rewritable in the flash memory
Areas Which Can Program ROM 1, program ROM 2, and
Be Rewritten
data flash
Operating Mode Single-chip mode
Memory expansion mode (EW0 mode)
ROM Programmer None
Standard Serial I/O Mode
Parallel I/O Mode
Program ROM 1, program ROM
2, and data flash are rewritten
using a dedicated serial programmer.
Standard serial I/O mode 1:
clock synchronous serial I/O
Standard serial I/O mode 2:
clock asynchronous serial I/O
Program ROM 1, program ROM 2 and data
flash are rewritten using
a dedicated parallel programmer.
Program ROM 1, program ROM Program ROM 1 and
2, and data flash
program ROM 2
Boot mode
Parallel I/O mode
Serial programmer
Parallel programmer
NOTES:
1. The PM13 bit remains set to 1 while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The
PM13 bit is reverted to its original value by clearing the FMR01 bit to 0 (CPU rewrite mode disabled). However, if
the PM13 bit is changed during CPU rewrite mode, its changed value is not reflected until after the FMR01 bit is
cleared to 0.
2. In CPU rewrite mode, bits PM10 and PM13 in the PM1 register are set to 1. The rewrite control program can only
be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1. When the
PM13 bit = 0 and the flash memory is used in 4-Mbyte mode, the extended accessible area (40000h to BFFFFh)
cannot be used.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.1
22. Flash Memory Version
Memory Map
The flash memory contains program ROM 1, program ROM 2, and data flash. Figure 22.1 shows a Flash
Memory Block Diagram.
Program ROM 1 is divided into several blocks, each of which can be protected (locked) from program or
erase. Program ROM 1 and program ROM 2 can be rewritten in CPU rewrite, standard serial I/O, and parallel I/O modes.
Program ROM 2 can be used when the PRG2C0 bit in the PRG2C register is set to 0 (program ROM 2
enabled). The user boot code area is in program ROM 2. Data flash can be used when the PM10 bit in the
PM1 register is set to 1 (0E000h to 0FFFFh: data flash). Data flash is divided into block A and block B.
00E000h
00EFFFh
00F000h
00FFFFh
010000h
Block A
Data flash
Block B
Program ROM 2
013FFFh
080000h
Block 7 : 64 Kbytes
08FFFFh
090000h
Block 6 : 64 Kbytes
09FFFFh
0A0000h
Block 5 : 64 Kbytes
0AFFFFh
0B0000h
Block 4 : 64 Kbytes
0BFFFFh
0C0000h
Program ROM 1
Block 3 : 64 Kbytes
0CFFFFh
0D0000h
Block 2 : 64 Kbytes
0DFFFFh
0E0000h
Block 1 : 64 Kbytes
0EFFFFh
0F0000h
Block 0 : 64 Kbytes
0FFFFFh
NOTES:
1. To specify a block, use an even address in that block.
2. Shown here is a block diagram during single-chip mode.
Figure 22.1
Flash Memory Block Diagram
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.1.1
22. Flash Memory Version
Boot Mode
The microcomputer enters boot mode when a hardware reset occurs while an “L” signal is applied to the
P5_5 pin and an “H” signal is applied to pins CNVSS and P5_0. In boot mode, user boot mode or standard serial I/O mode is selected in accordance with the data in the user boot code area. Refer to 22.4
“Standard Serial I/O Mode” for details.
22.1.2
User Boot Function
User boot mode can be selected by the status of a port when the MCU starts in boot mode. Table 22.3
shows the user boot function specifications.
Table 22.3
User Boot Function Specifications
Item
Entry Pin
User Boot Start Level
User Boot Start Address
Specification
None or select a port from P0_0 to P10_7
Select “H” or “L”
Address 10000h (the start address of program ROM 2)
Set “UserBoot” in ASCII code to the addresses 13FF0h to 13FF7h in the user boot code area and
select a port for entry from addresses13FF8h to 13FF9h and the start level with the address 13FFBh.
After starting boot mode, user boot mode or standard serial I/O mode is selected in accordance with the
level of the selected port.
In addition, if addresses 13FF0h to 13FF7h are set to “UserBoot” in ASCII code and address 13FF8h to
13FFBh are set to “00h”, user boot mode is selected.
In user boot mode, the program of address 10000h (the start address of program ROM2) is executed.
Figure 22.2 shows user boot code area, Table 22.4 shows the start mode, Tables 22.5 and 22.6 the
values to be set to the user boot code area.
Program ROM 2
10000h
13FF0h
13FFFh
Figure 22.2
User Boot Start Address
User Boot Code Area
User Boot Code Area
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User Boot Code Area
13FF0h
Boot Code
13FF8h
Address
13FFAh
13FFBh
13FFCh
Bit
Start Level Select
13FFFh
Reserved Space
Port information for
entry
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Table 22.4
Start Mode (When the Port Pj_j is Selected for Entry)
Boot Code
(13FF0h to
13FF7h)
Port information for entry
“UserBoot” in
ASCII code
Other Than
“UserBoot” in
ASCII code
Port
Pi_j input
level
Start Mode
Address
(13FF8h to
13FF9h)
Bit
(13FFAh)
Start level
Select
(13FFBh)
0000h
00h
00h
–
User boot mode
Pi register
address
00h to 07h 00h
(value of j)
H
Standard serial I/O mode
L
User boot mode
Pi register
address
00h to 07h 01h
(value of j)
H
User boot mode
L
Standard serial I/O mode
–
–
–
Standard serial I/O mode
–
i=0 to 10, j=0 to 7
NOTES:
1. Do not use another combination of values apart from Table 22.4.
2. Refer to Table 22.5 ““UserBoot”in ASCII code”
3. Refer to Table 22.6 “Addresses of Selectable Ports for Entry”
Table 22.5
Address
ASCII code
Table 22.6
Port
P0
P1
P2
P3
P4
P5
“UserBoot”in ASCII code
13FF0h
13FF1h
13FF2h
13FF3h
13FF4h
13FF5h
13FF6h
13FF7h
55h
(U)
73h
(s)
65h
(e)
72h
(r)
42h
(B)
6Fh
(o)
6Fh
(o)
74h
(t)
Uppercase
Lower-case
Uppercase
Lower-case
Addresses of Selectable Ports for Entry
Address
03E0h
03E1h
03E4h
03E5h
03E8h
03E9h
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Port
P6
P7
P8
P9
P10
Oct 12, 2007
Address
03ECh
03EDh
03F0h
03F1h
03F4h
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.2
22. Flash Memory Version
Functions to Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code
check function for standard I/O mode to prevent the flash memory from reading or rewriting.
22.2.1
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel
input/output mode. Figure 22.3 shows the OFS1 Address. The OFS1 address is located in block 0 in
program ROM 1.
The ROM code protect function is enabled when the ROMCP1 bit is set to 0.
When exiting ROM code protect, erase block 0 including the OFS1 address by the CPU rewrite mode
or the standard serial I/O mode.
22.2.2
ID Code Check Function
Use the ID code check function in standard serial I/O mode. The ID code sent from the serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes do not match,
commands sent from the serial programmer are not accepted. However, if the four bytes of the reset
vector are “FFFFFFFFh”, ID codes are not compared, allowing all commands to be accepted.
The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh,
0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a
program with the ID codes set in these addresses.
Table 22.7 shows address for ID code stored.
The reserved character sequence of the ASCII codes “ALeRASE” is used for forced erase function.
The reserved character sequence of the ASCII codes “Protect” is used for standard serial I/O mode disabled function. Table 22.7 lists reserved character sequence.
When the ID codes stored in the ID code addresses in the user ROM area are set to the ASCII codes:
“ALeRASE” as the combination table listed in Table 22.7, forced erase function becomes active. When
the forced erase function or standard serial I/O mode disabled function is not used, use another combination of the ASCII codes.
Table 22.7
Reserved Character Sequence (Reserved Word)
Reserved word combination
of lD Code (ASCII)
ID Code Address
ALeRASE
Protect
FFFDFh
ID1
41h (A)
50h (upper-case P)
FFFE3h
ID2
4Ch (L)
72h (lower-case r)
FFFEBh
ID3
65h (e)
6Fh (lower-case o)
FFFEFh
ID4
52h (R)
74h (lower-case t)
FFFF3h
ID5
41h (A)
65h (lower-case e)
FFFF7h
ID6
53h (S)
63h (lower-case c)
FFFFBh
ID7
45h (E)
74h (lower-case t)
Reserve word for forced erase function: A set of reserved characters that match
all the ID code addresses in sequence as the combination table listed in Table
22.7.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.2.3
22. Flash Memory Version
Forced Erase Function
This function is available only in standard serial I/O mode.
When the reserved characters, “ALeRASE” in ASCII code, are sent from the serial programmer as ID
codes, the content of the user ROM area will be erased at once. However, if the ID codes stored in the
ID code addresses in the user ROM area are set to other than a reserved word “ALeRASE” (other than
the combination table listed in Table 22.7) when the ROMCP bit in the ROMCP address is set to other
than 11b (ROM code protect enabled), forced erase function is ignored and ID code check is executed.
Table 22.8 lists conditions and functions for forced erase function.
When both the ID codes sent from the serial programmer and the ID codes stored in the ID code
addresses correspond to the reserved word “ALeRASE”, the user ROM area will be erased. However,
when the serial programmer sends other than “ALeRASE”, even if the ID codes stored in the ID code
addresses are “ALeRASE”, there is no ID match and any command is ignored. The user ROM area
remains protected accordingly.
Table 22.8
Forced Erase Function
Condition
ID code from
Code in ID code
serial programmer stored address
ALeRASE
ALeRASE
Other than
ALeRASE (1)
Other than
ALeRASE
ALeRASE
Other than
ALeRASE (1)
Function
ROMCP1 bit in the
OFS1 address
–
1 (ROM code protect
disabled)
0(ROM code protect
enabled)
–
–
User ROM area all erase (forced erase
function)
ID code check
ID code check (no ID match)
ID code check
NOTE:
1. For the combination of the stored addresses is “Protect”, refer to 22.2.4 “Standard Serial I/O
Mode Disable Function”.
22.2.4
Standard Serial I/O Mode Disable Function
This function is available in standard serial I/O mode. When the ID codes in the ID code stored
addresses are set to “Protect” in ASCII code, the MCU does not communicate with a serial programmer. Therefore, the flash memory cannot be read, written or erased by a serial programmer. User boot
mode can be selected, when the ID codes set to “Protect”.
When the ID codes are set to “Protect” and the ROMCP1 bit in the address OFS1 is set to 0 (ROM
code protect enabled), ROM code protection cannot be disabled by a serial programmer. Therefore, the
flash memory cannot be read, written or erased by a serial or parallel programmer.
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Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Optional Feature Select Address (1)
Symbol
OFS1
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1
1 1
Address
FFFFFh
Bit Name
Bit Symbol
WDTON
—
(b2-b1)
Function
CSPROINI
RW
(3)
0 : Watchdog timer starts automatically
after reset
1 : Watchdog timer is in a stopped state
after reset
RW
Reserved bits
Set to 1
RW
0 : ROM code protection enabled
1 : ROM code protection disabled
RW
Reserved bits
Set to 1
RW
After-reset count source
protection mode select bit (3)
0 : Count source protection mode
enabled after reset
1 : Count source protection mode
disabled after reset
RW
Watchdog timer start select bit
ROMCP1 ROM code protection bit
—
(b6-b4)
After Reset
FFh (2)
NOTES :
1. The OFS1 address exists in flash memory. Set the values when writing a program.
2. The OFS1 address is set to FFh when a block including the OFS1 address is erased.
3. Set the WDTON bit to 0 (watchdog timer starts automatically after reset) when setting the CSPROINI bit to 0
(count source protection mode enabled after reset).
Figure 22.3
OFS1 Address
Address
0FFFDFh to 0FFFDCh
ID1
Undefined instruction vector
0FFFE3h to 0FFFE0h
ID2
Overflow vector
0FFFE7h to 0FFFE4h
BRK instruction vector
0FFFEBh to 0FFFE8h
ID3
Address match vector
0FFFEFh to 0FFFECh
ID4
Single step vector
0FFFF3h to 0FFFF0h
ID5
Watchdog timer vector
0FFFF7h to 0FFFF4h
ID6
DBC vector
0FFFFBh to 0FFFF8h
ID7
NMI vector
0FFFFFh to 0FFFFCh
OFS1
Reset vector
4 bytes
Figure 22.4
Address for ID Code Stored
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.3
22. Flash Memory Version
CPU Rewrite Mode
In CPU rewrite mode, the flash memory can be rewritten when the CPU executes software commands.
Program ROM 1, program ROM 2, and data flash can be rewritten with the microcomputer mounted on a
board without using a ROM programmer.
The program and block erase commands are executed only in each block area of program ROM 1, program ROM 2, and data flash.
Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode. Table 22.9
lists differences between erase-write 0 (EW0) and erase-write 1 (EW1) modes.
Table 22.9
EW0 Mode and EW1 Mode
Item
Operating Mode
EW0 Mode
• Single-chip mode
• Memory expansion mode
• Program ROM 1
• Program ROM 2
Rewrite Control Program Allocatable
Area
Rewrite Control Pro- The rewrite control program must be
transferred to any area other than the
gram Executable
flash memory (e.g., RAM) before being
Area
executed (2)
Rewritable Area
• Program ROM 1
• Program ROM 2
• Data flash
Software Command None
Restriction
Mode after Program Read status register mode
or Erase
Operating
CPU State during
Auto Write and Auto
Erase
Flash Memory Status Detection
• Read bits FMR00, FMR06, and
FMR07 in the FMR0 register by program
• Execute the read status register command to read bits SR7, SR5, and SR4
in the status register.
EW1 Mode
Single-chip mode
• Program ROM 1
• Program ROM 2
The rewrite control program can be executed in program ROM 1, program ROM
2, and data flash.
Program ROM 1, program ROM 2, and
data flash, excluding blocks with the
rewrite control program
• Program and block erase commands
cannot be executed in a block having
the rewrite control program.
• Read status register command cannot
be used.
Read array mode
Maintains hold state (I/O ports maintains
the state before the command execution) (1)
Read bits FMR00, FMR06, and FMR07
in the FMR0 register by program
NOTES:
1. Do not generate an interrupt (except NMI interrupt) or start a DMA transfer.
2. When in CPU rewrite mode, bits PM10 and PM13 in the PM1 register are set to 1. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when
the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is used in 4-Mbyte mode, the
extended accessible area (40000h to BFFFFh) cannot be used.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.3.1
22. Flash Memory Version
EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to 1 (CPU
rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR60
bit in the FMR6 register to 0. Figure 22.7 shows setting and resetting of EW0 mode.
The software commands control programming and erasing. The FMR0 register or the status register
indicates whether a program or erase operation is completed as expected or not.
22.3.2
EW1 Mode
EW1 mode is selected by setting the FMR60 bit to 1 after setting the FMR01 bit to 1. Figure 22.8 shows
setting and resetting of EW1 mode.
The FMR0 register indicates whether or not a program or erase operation has been completed as
expected. The status register cannot be read in EW1 mode.
When a program / erase operation is initiated, the CPU halts all program execution until the operation is
completed.
22.3.3
Flash Memory Control Register (Registers FMR0, FMR1, FMR2 and FMR6)
Figures 22.5 to 22.8 show the registers FMR0, FMR1, FMR2 and FMR6, respectively.
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Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
After Reset
FMR0
0220h
00000001b
Bit Name
Bit Symbol
Function
0 : Busy (being written or erased) (6)
1 : Ready
RW
FMR00
RY / BY status flag
FMR01
CPU rewrite mode select 0 : CPU rewrite mode disabled
1 : CPU rewrite mode enabled
bit (1)
RW
FMR02
Lock bit disable select bit 0 : Lock bit enabled
(2)
1 : Lock bit disabled
RW
FMSTP
Flash memory stop bit
(3, 5, 7)
RO
0 : Flash memory operation enabled
1 : Flash memory operation stopped
(placed in low power mode, flash memory
initialized)
RW
—
(b4)
Reserved bit
Set to 0
RW
—
(b5)
Reserved bit
Set to 0
RW
FMR06
Program status flag (4)
0 : Terminated normally
1 : Terminated in error
RO
FMR07
Erase Status Flag (4)
0 : Terminated normally
1 : Terminated in error
RO
NOTES :
1. To set the FMR01 bit to 1, write a 0 and then a 1 in succession. Make sure no interrupts or DMA transfers will
occur before writing a 1 after writing a 0. While in EW0 mode, write to this bit from a program in other than the
flash memory. Enter read array mode, and then set this bit to 0.
2. To set the FMR02 bit to 1, write a 0 and then a 1 in succession when the FMR01 bit = 1. Make sure no interrupts
or no DMA transfers will occur before writing a 1 after writing a 0.
3. Write to the FMSTP bit from a program in area other than the flash memory.
4. Bits FMR06 and FMR07 are cleared to 0 by executing the clear status command.
5. The FMSTP bit is valid when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP
bit can be set to 1 by writing 1 in a program, the flash memory is neither placed in low power mode nor initialized.
6. This status includes writing or reading with the lock bit program, block blank check, or read lock bit status
command.
7. When the FMR23 bit in the FMR 2 register is set to 1 (low-current consumption), do not set the FMSTP bit to 1
(flash memory stop). Also, when the FMSTP bit is set to 1, do not set the FMR23 bit to 1.
Figure 22.5
FMR0 Register
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset
FMR1
0221h
00X0XX0Xb
Bit Symbol
—
(b0)
Bit Name
Function
RW
Reserved bit
Read as undefined value
RO
FMR11
Write to FMR6 register
enable bit
0 : Disabled
1 : Enabled
RW
—
(b3-b2)
Reserved bits
Read as undefined value
RO
—
(b4)
Reserved bit
Set to 0
RW
—
(b5)
No register bit. If necessary, set to 0. Read as undefined value
RW
FMR16
Lock bit status flag
0 : Lock
1 : Unlock
RO
FMR17
Data flash wait bit (1)
0 : 1 wait
1 : Follow the setting of the PM17 bit
RW
NOTE :
1. When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20 MHz,
one wait is necessary to read the data flash. Use the PM17 or FMR17 bit to set one wait.
Figure 22.6
FMR1 Register
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Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Flash Memory Control Register 2
Symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0
FMR2
Bit Symbol
Address
After Reset
0222h
XXXX0000b
Bit Name
Function
RW
—
(b1-b0)
Reserved bit
Set to 0
RW
FMR22
Slow read mode enable
bit (1, 3, 4)
0 : Disabled
1 : Enabled
RW
FMR23
Low-current consumption
0 : Disabled
read mode enable bit
1 : Enabled
(2, 3, 4, 5, 6, 7)
RW
—
(b7-b4)
No register bit. If necessary, set to 0. Read as undefined value
—
NOTES:
1. Slow read mode can be used when f(BCLK) ≤ 5 MHz. When f(BCLK) > 5 MHz, set the FMR22 bit to 0 (slow
read mode disabled).
2. The low-current consumption read mode can be used when f(BCLK) ≤ 32.768 kHz. When f(BCLK) >
32.768 kHz, set the FMR23 bit to 0 (low-current consumption read mode disabled).
3. To set the FMR01 bit to 1, write a 0 and then a 1 in succession. Make sure no interrupts or DMA transfers
will occur before writing a 1 after writing a 0.
4. This bit enables the mode to reduce the amount of current consumption when reading the flash memory.
To rewrite flash memory (CPU rewrite mode), set the FMR22 and FMR23 bits to 0.
5. Set the FMR23 bit to 1 (low-current consumption read mode enabled) after the FMR22 bit is set to
1 (slow read mode enabled). Also, set the FMR22 bit to 0 (slow read mode disabled) after the FMR23 bit is
set to 0 (slow read mode disabled). Do not write the FMR22 and FMR23 bits at same time.
6. When the FMR23 bit is set to 1, do not set the FMSTP bit in the FMR0 register to 1 (flash memory
stopped). Also, when the FMSTP bit is set to 1, do not set the FMR23 bit to 1.
7. When the FMR23 bit in the FMR2 register is set to 1 (Low-current consumption read mode enabled),
do not enter wait mode or stop mode. To enter wait mode or stop mode, set the FMR23 bit to 0 (lowcurrent consumption read mode disabled) before entering.
Figure 22.7
FMR2 Register
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Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Flash Memory Control Register 6
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol
Address
After Reset
FMR6
0230h
XX0XXX00b
Bit Symbol
Bit Name
Function
EW1 mode select bit (1)
0 : EW0 mode
1 : EW1 mode
RW
—
(b1)
Reserved bit
Set to 1
RW
—
(b4-b2)
Reserved bits
Read as undefined value
RO
—
(b5)
Reserved bit
Set to 0
RW
—
(b7-b6)
Reserved bits
Read as undefined value
RO
FMR60
NOTE :
1. To set the FMR60 bit to 1, write 1 when both bits FMR01 and FMR11 are 1.
Figure 22.8
FMR6 Register
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RW
Oct 12, 2007
Under development
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Specification in this preliminary version is subject to change.
M16C/64 Group
22.3.3.1
22. Flash Memory Version
FMR00 Bit
This bit indicates the flash memory operating state. It is set to 0 while the program, block erase, lock
bit program, read lock bit status command, or block blank check command is being executed; otherwise, it is set to 1.
22.3.3.2
FMR01 Bit
The microcomputer can accept commands when the FMR01 bit is set to 1 (CPU rewrite mode).
22.3.3.3
FMR02 Bit
The lock bit is disabled by setting the FMR02 bit to 1 (lock bit disabled). (Refer to 22.3.6 “Data Protect Function”.) The lock bit is enabled by setting the FMR02 bit to 0 (lock bit enabled).
The FMR02 bit does not change the lock bit status but disables the lock bit function. If an erase command is executed when the FMR02 bit is set to 1, the lock bit status changes 0 (locked) to 1
(unlocked) after command execution is completed.
22.3.3.4
FMSTP Bit
The FMSTP bit resets the flash memory control circuits and minimizes power consumption in the
flash memory. Access to the flash memory is disabled when the FMSTP bit is set to 1 (flash memory
stops). Set the FMSTP bit by program in an area other than the flash memory.
Set the FMSTP bit to 1 if one of the followings occurs:
• A flash memory access error occurs while erasing or programming in EW0 mode (the FMR00 bit
does not switch back to 1 (ready)).
• Low-power consumption mode or on-chip oscillator low-power consumption mode is entered
Use the following steps to stop the flash memory.
(1) Set the FMSTP bit to 1
(2) Wait tps (the wait time to stabilize the flash memory circuit)
Use the following steps to restart.
(1) Set the FMSTP bit to 0
(2) Wait tps (the wait time to stabilize the flash memory circuit)
Figure 22.13 shows a Flow Chart Illustrating How to Start and Stop the Flash Memory Processing
Before and After Low-Power Consumption Mode or On-Chip Oscillator Low-Power Consumption
Mode. Follow the procedure on this flow chart.
When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or
wait mode, the flash memory is turned back on. The FMR0 register does not need to be set.
22.3.3.5
FMR06 Bit
This is a read-only bit indicating an auto program operation state. The FMR06 bit is set to 1 when a
program error occurs; otherwise, it is set to 0. Refer to 22.3.8 “Full Status Check”.
22.3.3.6
FMR07 Bit
This is a read-only bit indicating the auto erase operation status. The FMR07 bit is set to 1 when an
erase error occurs; otherwise, it is set to 0. The FMR07 bit is also used for blank check. For details,
refer to 22.3.8 “Full Status Check”.
22.3.3.7
FMR11 Bit
The FMR11 bit enables programming to the FMR6 register.
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22.3.3.8
22. Flash Memory Version
FMR16 Bit
This is a read-only bit indicating the execution result of the read lock bit status command.
When the block, where the read lock bit status command is executed, is locked, the FMR16 bit is set
to 0.
When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is
set to 1.
22.3.3.9
FMR17 Bit
This is a bit to select wait state for data flash.
22.3.3.10 FMR22 Bit
This bit enables the mode to reduce the amount of current consumption when reading the flash memory. When rewriting the flash memory (CPU rewrite mode), set the FMR22 bit to 0 (slow read mode
disabled).
Also, when f(BCLK) > 5 MHz, set the FMR22 bit to 0 (slow read mode disabled).
Figure 22.9 shows setting and resetting of the slow read mode.
Slow read mode
Set the frequency of CPU clock to 5 MHz or less
Setting
procedure
After writing 0, write 1 (enabled) to the FMR22 bit
Process in slow read mode
Write 0 to FMR22 bit
Resetting
procedure
Return to the prior frequency of the CPU clock
Slow read mode is completed
Figure 22.9
Setting and Resetting of Slow Read Mode
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22. Flash Memory Version
22.3.3.11 FMR23 Bit
This bit enables the mode to reduce the amount of current consumption when reading the flash memory. When rewriting the flash memory (CPU rewrite mode), set the FMR23 bit to 0 (low-current consumption read mode disabled).
This bit is effective when the FMR22 bit is enabled. When f(BCLK) > 32.768 kHz, set the FMR23 bit
to 0 (low-current consumption read mode disabled).
Figure 22.10 shows setting and resetting of the low-current consumption read mode.
Low-current consumption read mode
Write 1 to the CM07 bit to select
the sub clock in CPU clock (1)
Set the CM05 bit to 1 (main clock oscillation stop)
After writing 0, write 1 (enabled) to the FMR22 bit
Setting
procedure
After writing 0, write 1 (enabled) to the FMR23 bit
Process in low-current consumption mode
Write 0 to FMR23 bit (2)
Write 0 to FMR22 bit (2)
Resetting
Procedure
Return to the prior CPU clock
Slow read mode is completed
NOTES :
1. This is to use the low-power consumption mode.
To use 125 kHz on-chip oscillator low power consumption mode, set the 125 kHz
on-chip oscillator divided by 8 or 16 (Refer to Table 10.3 Setting Clock Related Bit
and Modes).
2. Do not write the FMR22 bit and FMR23 bit at the same time.
Figure 22.10 Setting and Resetting of Low-current Consumption Read Mode
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22. Flash Memory Version
22.3.3.12 FMR60 Bit
This bit is used to select EW1 mode when the FMR01 bit is set to 1 (CPU rewrite mode enabled).
Figure 22.11 shows Setting and Resetting of EW0 Mode. Figure 22.12 shows Setting and Resetting
of EW1 Mode.
Procedure to Enter EW0 Mode
Rewrite control program
Set the FMR01 bit to 0,
and then 1 (CPU rewrite mode enabled). (2)
Set the FMR11 bit to 1 (FMR6 register write enabled),
and then set the FMR6 register to 02h (EW0 mode),
and then set the FMR11 bit to 0 (FMR6 register write disabled).
Single-chip mode
or memory expansion mode
Transfer the rewrite control program in CPU rewrite
mode to an area other than the flash memory (4)
Set registers CM0, CM1, and PM1
(4)
Execute the software commands
(1)
Execute the read array command (3)
Jump to the rewrite control program transferred to an
area other than the flash memory. (In the following
steps, use the rewrite control program in an area
other than the flash memory)
Set the FMR01 bit to 0
(CPU rewrite mode disabled)
Jump to a desired address in the flash memory
NOTES :
1. In CPU rewrite mode, set the CM06 bit in the CM0 register and bits CM17 and CM16 in the
CM1 register to CPU clock frequency of 10 MHz or less. Set the PM17 bit in the PM1
register to 1 (with wait state).
2. Set the FMR01 bit to 1 immmediately after setting it to 0. Do not generate an interrupt or a
DMA transfer between setting the bit to 0 and setting it to 1. Set the FMR01 bit in a space
other than flash memory.
3. Exit CPU rewrite mode after executing the read array command.
4. When in CPU rewrite mode, bits PM10 and PM13 in the PM1 register are set to 1. The
rewrite control program can only be executed in the internal RAM or in an external area that
is enabled for use when the PM13 bit = 1. When the PM13 bit = 0 and the flash memory is
used in 4-Mbyte mode, the extended accessible area (40000h to BFFFFh) cannot be used.
Figure 22.11 Setting and Resetting of EW0 Mode
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22. Flash Memory Version
Procedure to Enter EW1 Mode
Program in the ROM
Single-chip mode
(1)
Set registers CM0, CM1, and PM1
(2)
Set the FMR01 bit to 1 (CPU rewrite mode enabled) after
writing a 0. (3)
Set the FMR11 bit to 1 (FMR6 register rewrite enabled),
and then set the FMR6 register to 03h (EW1 mode),
and then set the FMR11 bit to 0 (FMR6 register rewrite
disabled).
Execute the software commands
Set the FMR01 bit to 0
(CPU rewrite mode disabled)
NOTES:
1. In EW1 mode, do not enter memory expansion.
2. In CPU rewrite mode, set the CM06 bit in the CM0 register and bits CM17 and CM16
in the CM1 register to CPU clock frequency of 10 MHz or less. Set the PM17 bit in
the PM1 register to 1 (with wait state).
3. To set the FMR01 bit to 1, write a 0 and then a 1 to the FMR01 bit. Make sure no
interrupts or no DMA transfers will occur before writing a 1 after writing a 0. When
setting the FMR11 bit to 1, set 1 while the FMR01 bit is set to 1.
Figure 22.12 Setting and Resetting of EW1 Mode
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22. Flash Memory Version
Transfer the low-power consumption mode or
on-chip oscillator low-power consumption mode
program to an area other than the flash memory
Jump to the low-power consumption mode or
on-chip oscillator low-power consumption mode program
transferred to an area other than the flash memory. (In the
following steps, use the
low-power consumption mode or on-chip oscillator lowpower consumption mode program in an area other than
the flash memory.)
Low-power consumption
mode or on-chip oscillator
low-power consumption mode
program
Set the FMR01 bit to 1 after setting to 0
(CPU rewrite mode enabled)
Set the FMSTP bit to 1 (The flash memory stops
operating. In a low-power consumption state) (1)
Switch clock source of the CPU clock.
The main clock stops (2)
Process in low-power consumption mode or
on-chip oscillator low-power consumption mode
NOTES:
1. Set the FMSTP bit to 1 after the FMR01 bit is set to 1
(CPU rewrite mode enabled).
2. Wait until clock stabilizes to switch clock source of
the CPU clock to the main clock or sub clock.
3. Add tps wait time by program. Do not access the
flash memory during this wait time.
4. Before entering wait mode or stop mode, be sure
to set the FMR01 bit to 0.
Start main
clock oscillation
Wait until
oscillation
stabilizes
(4)
Switch clock source
of the CPU clock (2)
Set the FMSTP bit to 0 (flash memory operation)
Set the FMR01 bit to 0
(CPU rewrite mode disabled)
Wait until the flash memory stabilizes (tps) (3)
Jump to a desired address in the flash memory
Figure 22.13 Processing Before and After Low-Power Consumption Mode or On-Chip Oscillator
Low-Power Consumption Mode
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22.3.4
22.3.4.1
22. Flash Memory Version
Precautions on CPU Rewrite Mode
Operating Speed
Set the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register to a CPU clock
frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the
PM17 bit in the PM1 register to 1 (wait state).
22.3.4.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in the
flash memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK
instruction.
22.3.4.3
Interrupts (EW0 mode)
• To use interrupts with vectors in a relocatable vector table, relocate the vectors to the RAM area.
• The NMI and watchdog timer interrupts are available since registers FMR0 and FMR1 are forcibly
reset when either interrupt occurs. Allocate the jump addresses for each interrupt routine to the fixed
vector table. Flash memory rewrite operation stops when the NMI or watchdog timer interrupt
occurs. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
22.3.4.4
Interrupts (EW1 mode)
• Do not acknowledge any interrupts with vectors in a relocatable vector table or address match interrupt during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.
• The NMI interrupt is available since registers FMR0 and FMR1 are forcibly reset when the interrupt
occurs. Allocate the jump address for the interrupt routine to the fixed vector table. Flash memory
rewrite operation stops when the NMI interrupt occurs. Execute the rewrite program again after exiting the interrupt routine.
22.3.4.5
How to Access
To set the FMR01 or FMR02 bit to 1, write a 1 after first setting the bit to 0. Make sure that no interrupts or no DMA transfers will occur before writing a 1 after writing a 0.
22.3.4.6
Rewrite (EW0 mode)
If the supply voltage drops while rewriting the block where the rewrite control program is stored, the
rewrite control program is not correctly rewritten. This may cause the flash memory not to be rewritten. If this error occurs, use standard serial I/O mode or parallel I/O mode for rewriting.
22.3.4.7
Rewrite (EW1 mode)
Do not rewrite any block in which the rewrite control program is stored.
22.3.4.8
DMA Transfer
In EW1 mode, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to 0
(auto programming or auto erasing).
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22.3.4.9
22. Flash Memory Version
Writing Command and Data
Write commands and data to even addresses.
22.3.4.10 Wait Mode
When entering wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the
WAIT instruction.
22.3.4.11 Stop Mode
To enter stop mode, set the FMR01 bit to 0 (CPU rewrite mode disabled), and then disable DMA
transfer before setting the CM10 bit to 1 (stop mode).
22.3.4.12 Low-Power Consumption Mode and On-Chip Oscillator Low-power Consumption Mode
When the CM05 bit is set to 1 (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Lock bit program
• Read lock bit status
• Block blank check
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22.3.5
22. Flash Memory Version
Software Commands
Software commands are described below. Read and write the command code and data in 16-bit units,
from and to even addresses in the program ROM 1, program ROM 2, and data flash. When the command code is written, the 8 high-order bits (D15 to D8) are ignored.
Table 22.10
Software Commands
Command
Read Array
Read Status Register
Clear Status Register
Program
Block Erase
Lock Bit Program
Read Lock Bit Status
Block Blank Check
SRD
WA0
First Bus Cycle
Data
Mode Address (D15 to
D0)
Write
x
xxFFh
Write
x
xx70h
Write
x
xx50h
Write
WA0
xx41h
Write
x
xx20h
Write
BA
xx77h
Write
x
xx71h
Write
x
xx25h
Second Bus Cycle
Third Bus Cycle
Data
Data
Mode Address (D15 to Mode Address (D15 to
D0)
D0)
Read
x
SRD
Write
Write
Write
Write
Write
WA0
BA
BA
BA
BA
WD0
xxD0h
xxD0h
xxD0h
xxD0h
Write
WA1
WD1
: Data in the status register (D7 to D0)
: Address which low-order words are written (The address specified in the first bus
cycle is the same even address as the address specified in the second bus cycle.)
: Address which high-order words are written
: Write data low-order word (16 bits)
: Write data high-order word (16 bits)
: Highest-order block address (even address)
: Given even address in the program ROM 1, program ROM 2, and data flash
: Eight high-order bits of command code (ignored)
WA1
WD0
WD1
BA
x
xx
22.3.5.1
Read Array Command
The read array command reads the flash memory.
By writing the command code xxFFh in the first bus cycle, read array mode is entered. Content of a
specified address can be read in 16-bit units by entering an address to be read after the next bus
cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents from multiple addresses can be read consecutively.
22.3.5.2
Read Status Register Command
The read status register command reads the status register.
By writing the command code xx70h in the first bus cycle, the status register can be read in the second bus cycle (refer to 22.3.7 “Status Register”l). Read an even address in the program ROM 1,
program ROM 2, and data flash.
Do not execute this command in EW1 mode.
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22.3.5.3
22. Flash Memory Version
Clear Status Register Command
The clear status register command clears the status register. By writing xx50h in the first bus cycle,
bits FMR07 and FMR06 in the FMR0 register are set to 00b, and bits SR5 and SR4 in the status register are set to 00b.
22.3.5.4
Program Command
The program command writes 2-word (4 bytes) data to the flash memory. By writing xx41h in the first
bus cycle and data to the write address in the second and third bus cycles, an auto program operation (data program and verify) will start. The address value specified in the first bus cycle must be the
same even address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 register indicates whether an auto program operation has been completed. The FMR00 bit is set to 0 (busy) during auto program and to 1 (ready) while in an auto program operation.
After the completion of an auto program operation, the FMR06 bit in the FMR0 register indicates
whether or not the auto program operation has been completed as expected. (Refer to 22.3.8 “Full
Status Check”.)
An address that is already written cannot be altered or rewritten. Figure 22.14 shows a Flow Chart of
the Program Command Programming.
The lock bit protects each block from being programmed inadvertently. (Refer to 22.3.6 “Data Protect Function”.)
In EW1 mode, do not execute this command on the block to which the rewrite control program is allocated.
In EW0 mode, the microcomputer enters read status register mode as soon as an auto program
operation starts. The status register can be read. The SR7 bit in the status register is set to 0 at the
same time an auto program operation starts. It is set to 1 when the auto program operation is completed. The microcomputer remains in read status register mode until the read array command is
written. After completion of an auto program operation, the status register indicates whether or not
the auto program operation has been completed as expected.
Start
Write the command
code xx41h to an
address to be written
Write data to an
address to be written
FMR00 = 1?
NO
YES
Full status check
Program operation is
completed
NOTE:
1. Write the command code and data to even addresses.
Figure 22.14 Program Command
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22.3.5.5
22. Flash Memory Version
Block Erase Command
By writing xx20h in the first bus cycle and xxD0h in the second bus cycle to the highest-order even
address of a block, an auto erase operation (erase and verify) will start in the specified block.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
The FMR00 bit is set to 0 (busy) during auto erase and to 1 (ready) when the auto erase operation is
completed.
After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates
whether or not the auto erase operation has been completed as expected. (Refer to 22.3.8 “Full Status Check”.)
Figure 22.15 shows a Block Erase Command.
The lock bit protects each block from being erased inadvertently. (Refer to 22.3.6 “Data Protect
Function”.)
In EW1 mode, do not execute this command on the block where the rewrite control program is allocated.
In EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation starts. The status register can be read. The SR7 bit in the status register is set to 0 at the same
time an auto erase operation starts. It is set to 1 when an auto erase operation is completed. The
microcomputer remains in read status register mode until the read array command or read lock bit
status command is written. If an erase error occurs, execute the clear status register command and
then block erase command at least 3 times until an erase error is not generated.
Start
Write the command code
xx20h (1)
Write xxD0h to the highestorder block address
FMR00 YES
= 1?
NO
YES
Full status check (2, 3)
Block erase operation
is completed
NOTES:
1. Write the command code and data to even addresses.
2. Refer to Figure 22.15 Full Status Check and Handling Procedure
for Each Error.
3. If an erase error occurs, execute the clear status register command and then
block erase command at least 3 times until an erase error is not generated.
Figure 22.15 Block Erase Command
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22.3.5.6
22. Flash Memory Version
Lock Bit Program Command
The lock bit program command sets the lock bit for a specified block to 0 (locked).
By writing xx77h in the first bus cycle and xxD0h in the second bus cycle to the highest-order even
address of a block, the lock bit for the specified block is set to 0. The address value specified in the
first bus cycle must be the same highest-order address of a block specified in the second bus cycle.
Figure 22.16 shows a Flow Chart of the Lock Bit Program Command Programming. Execute read
lock bit status command to read lock bit state (lock bit data).
The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed.
Refer to 22.3.6 “Data Protect Function” for details on lock bit functions and how to set it to 1
(unlocked).
Start
Write the command code xx77h
to the highest-order block
address
Write xxD0h to the highestorder block address
FMR00 = 1?
NO
YES
Full status check
Lock bit program
operation is completed
NOTE:
1. Write the command code and data to even addresses.
Figure 22.16 Lock Bit Program Command
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22.3.5.7
22. Flash Memory Version
Read Lock Bit Status Command
The read lock bit status command reads the lock bit state of a specified block.
By writing xx71h in the first bus cycle and xxD0h in the second bus cycle to the highest-order even
address of a block, the FMR16 bit in the FMR1 register stores information on the lock bit status of a
specified block. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to 1 (ready).
Figure 22.17 shows a Flow Chart of the Read Lock Bit Status Command Programming.
Start
Write the command code xx71h
Write xxD0h to the highestorder block address
FMR00 = 1?
NO
YES
FMR16 = 0?
NO
YES
Block is locked
Block is not locked
NOTE:
1. Write the command code and data to even addresses.
Figure 22.17 Read Lock Bit Status Command
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22.3.5.8
22. Flash Memory Version
Block Blank Check
The block blank check command checks whether or not a specified block is blank (state after erase).
By writing xx25h in the first bus cycle and xxD0h in the second bus cycle to the highest-order even
address of a block, the check result is stored in the FMR07 bit in the FMR0 register. Read the FMR07
bit after the FMR00 bit in the FMR0 register is set to 1 (ready).
The block blank check command is valid for unlocked blocks. If the block blank check command is
executed to a block whose lock bit is 0 (locked), the FMR07 bit (SR5) is set to 1 (not blank) regardless of the FMR02 bit state.
Figure 22.18 shows a Flow Chart of the Block Blank Check Command Programming.
Start
Write the command code xx25h
Write xxD0h to the highestorder block address
FMR00 = 1?
NO
YES
FMR07 = 1?
NO
YES
Blank
Not blank
NOTE:
1. Write the command code and data to even addresses.
Figure 22.18 Block Blank Check Command
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22.3.6
22. Flash Memory Version
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02
bit to 0 (lock bit enabled). The lock bit allows each block to be individually protected (locked) against
program and erase. This prevents data from being inadvertently written to or erased from the flash
memory.
A block changes its status according to the lock bit status:
• When the lock bit status is set to 0, the block is locked (block is protected against program and
erase).
• When the lock bit status is set to 1, the block is not locked (block can be programmed or erased).
The lock bit status is set to 0 (locked) by executing the lock bit program command and to 1 (unlocked)
by erasing the block. No commands can set the lock bit status to 1.
The lock bit status can be read by the read lock bit status command.
When the FMR02 bit is set to 1, the lock bit function is disabled, and all blocks are unlocked. However,
individual lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit
to 0. Lock bit status is retained.
If the block erase command is executed while the FMR02 bit is set to 1, the target block or all blocks are
erased regardless of lock bit status. The lock bit status of each block is set to 1 after an erase operation
is completed.
Refer to 22.3.5 “Software Commands” for details on each command.
22.3.7
Status Register
The status register indicates the flash memory operation state and whether or not an erase or program
operation is completed as expected. Bits FMR00, FMR06, and FMR07 in the FMR0 register indicate
status register states.
Table 22.11 shows the Status Register.
In EW0 mode, the status register can be read when the followings occur.
• Any even address in the program ROM 1, program ROM 2, or data flash is read after writing the
read status register command.
• Any even address in the program ROM 1, program ROM 2, or data flash is read from when the program, block erase, lock bit program, or block blank check command is executed until when the
read array command is executed.
22.3.7.1
Sequence Status (Bits SR7 and FMR00)
The sequence status indicates the flash memory operation state. It is set to 0 while the program,
block erase, lock bit program, block blank check, or read lock bit status command is being executed;
otherwise, it is set to 1.
22.3.7.2
Erase Status (Bits SR5 and FMR07)
Refer to 22.3.8 “Full Status Check”.
22.3.7.3
Program Status (Bits SR4 and FMR06)
Refer to 22.3.8 “Full Status Check”.
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Table 22.11
22. Flash Memory Version
Status Register
Bits in Status Bit in FMR0
Register
Register
SR0 (D0)
SR1 (D1)
SR2 (D2)
SR3 (D3)
SR4 (D4)
SR5 (D5)
SR6 (D6)
SR7 (D7)
FMR06
FMR07
FMR00
Status name
Definition
0
Reserved
Reserved
Reserved
Reserved
Program status Terminated normally
Erase status
Terminated normally
Reserved
Sequencer status
Busy
1
Terminated in error
Terminated in error
Ready
Value after
Reset
0
0
1
D0 to D7 are the data buses read when the read status register command is executed.
Bits FMR07 (SR5) and FMR06 (SR4) are set to 0 when the clear status register command is executed.
When the FMR07 (SR5) or FMR06 bit (SR4) is set to 1, the program, block erase, lock bit program, block
blank check, and read lock bit status commands are not accepted.
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22.3.8
22. Flash Memory Version
Full Status Check
If an error occurs when a program or erase operation is completed, bits FMR06 and FMR07 in the
FMR0 register are set to 1, indicating a specific error. Therefore, execution results can be confirmed
by checking these status (full status check).
Table 22.12 lists Errors and FMR0 Register State. Figure 22.19 shows a Full Status Check and Handling Procedure for Each Error.
Table 22.12
Errors and FMR0 Register State
FMR00 Register
(Status Register)
State
FMR06
FMR07
bit
bit
(SR5 bit) (SR4 bit)
1
1
0
1
0
1
Error
Error Occurrence Conditions
Command
Sequence error
• Command is written incorrectly
• A value other than xxD0h or xxFFh is written in the second bus
cycle of the lock bit program or block erase command (1)
Erase error
• The block erase command is executed on a locked block (2)
• The block erase command is executed on an unlocked block,
but auto erase operation is not completed as expected
• The block blank check command is executed, and the check
result is not blank
• The block blank check command is executed on a locked block
Program error
• The program command is executed on a locked block (2)
• The program command is executed on an unlocked block, but
program operation is not completed as expected
• The lock bit program command is executed, but the lock bit is
not written as expected (2)
NOTES:
1. The flash memory enters read array mode by writing command code xxFFh in the second bus cycle
of the commands. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit is set to 1 (lock bit disabled), no error occurs even under the conditions above.
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Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Full status check
FMR06 =1
and
FMR07=1?
YES
Command
sequence error
(1) Execute the clear status register command and set bits FMR06 and FMR07
to 0 (completed as expected) .
(2) Rewrite command and execute again.
NO
FMR07=0?
NO
Erase error
(1) Execute the clear status register command and set the FMR07 bit to 0.
(2) Execute the read lock bit status command. Set the FMR02 bit to 1
(lock bit disabled) if the lock bit in the block where the error occurred is
set to 0 (locked).
(3) Execute the block erase command again.
(4) Execute (1), (2), and (3) at least 3 times until an erase error is not generated.
NOTE: If similar error still occurs, that block cannot be used.
If the lock bit is set to 1 (unlocked) in (2) above, that block
cannot be used.
YES
FMR06=0?
NO
Program error
[When a program operation is executed]
(1) Execute the clear status register command and set the FMR06 bit to 0
(completed
as expected) .
(2) Execute the read lock bit status command and set the FMR02 bit to 1 if the
lock bit in the block where the error occurred is set to 0.
(3) Execute the program command again.
NOTE: If similar error occurs, that block cannot be used.
If the lock bit is set to 1 in (2) above, that block cannot be used.
[When a lock bit program operation is executed]
(1) Execute the clear status register command and set the FMR06 bit to 0.
(2) Set the FMR02 bit in the FMR0 register to 1.
(3) Execute the block erase command to erase the block where the error
occurred.
(4) Execute the lock bit program command again.
YES
Full status check
completed
NOTE: If similar error occurs, that block cannot be used.
NOTE: When either FMR06 or FMR07 bit is set to 1 (terminated by error), the program, block erase, lock bit program, block blank check, and read
lock bit status commands cannot be accepted. Execute the clear status register command before each command.
Figure 22.19 Full Status Check and Handling Procedure for Each Error
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.4
22. Flash Memory Version
Standard Serial I/O Mode
In standard serial I/O mode, the serial programmer supporting the M16C/64 Group can be used to
rewrite the program ROM 1, program ROM 2, and data flash in the microcomputer mounted on a
board.
For more information about the serial programmer, contact your serial programmer manufacturer.
Refer to the user's manual included with your serial programmer for instructions.
Table 22.13 lists Pin Functions (Flash Memory Standard Serial I/O Mode). Figures 22.20 and 22.21
show Pin Connections in Serial I/O Mode.
22.4.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer match
those written in the flash memory. (Refer to 22.2 “Functions to Prevent Flash Memory from Rewriting”.)
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 22.13
Pin
22. Flash Memory Version
Pin Functions (Flash Memory Standard Serial I/O Mode)
Name
I/O
VCC1, VCC2, Power input
VSS
CNVSS
RESET
CNVSS
Reset input
I
I
XIN
XOUT
Clock input
Clock output
I
O
BYTE
AVCC, AVSS
BYTE input
Analog
power supply input
VREF
Reference
voltage input
P0_0 to P0_7 Input port P0
P1_0 to P1_7 Input port P1
P2_0 to P2_7 Input port P2
P3_0 to P3_7 Input port P3
P4_0 to P4_7 Input port P4
P5_1 to P5_4, Input port P5
P5_6, P5_7
P5_0
CE input
P5_5
EPM input
P6_0 to P6_3 Input port P6
P6_4 / RTS1 BUSY output
I
I
I
I
I
I
I
I
I
I
I
O
P6_5/CLK1
SCLK input
I
P6_6 / RXD1
P6_7 / TXD1
RXD input
TXD input
I
O
P7_0 to P7_7 Input port P7 I
P8_0 to P8_3, Input port P8 I
P8_6, P8_7
P8_4
P8_4 input
I
P8_5 / NMI
P9_0 to P9_7
P10_0 to
P10_7
Power
Description
Supply
Apply the flash program and erase voltage to the VCC1 pin,
and VCC2 to the VCC2 pin. The VCC apply condition is that
VCC2 = VCC1. Apply 0 V to the VSS pin.
VCC1 Connect to VCC1 pin.
VCC1 Reset input pin. While the RESET pin is “L” level, input a 20cycle or longer clock to the XIN pin.
VCC1 Connect a ceramic resonator or crystal oscillator between
VCC1 pins XIN and XOUT. To input an externally generated clock,
input it to the XIN pin and open the XOUT pin.
VCC1 Connect this pin to VCC1 or VSS.
Connect AVSS to VSS and AVCC to VCC1, respectively.
NMI input
I
Input port P9 I
Input port
I
P10
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
Reference voltage input pin for A/D converter. Connect to
VCC1.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
VCC2 Input “H” level signal.
VCC2 Input “L” level signal.
VCC1 Input “H” or “L” level signal or open.
VCC1 Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: monitor signal output pin to
check the boot program
operation
VCC1 Standard serial I/O mode 1: serial clock input pin
Standard serial I/O mode 2: Input “L”.
VCC1 Serial data input pin.
VCC1 Serial data output pin. (1)
VCC1 Input “H” or “L” level signal or open.
VCC1 Input “H” or “L” level signal or open.
VCC1 Input “L” level signal. (2)
VCC1 Input “H” or “L” level signal or open.
VCC1 Input “H” or “L” level signal or open.
VCC1 Input “H” or “L” level signal or open.
NOTES:
1. When using the standard serial I/O mode, the internal pull-up is enabled for the TXD1 (P6_7) pin
while the RESET pin is “L”.
2. When using the standard serial I/O mode, pins P0_0 to P0_7 and P1_0 to P1_7 may become indeterminate while the P8_4 pin is “H” and the RESET pin is “L”. If this causes a program, apply “L” to the
P8_4 pin.
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
22. Flash Memory Version
VCC2
M16C/64 Group
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
82
49
83
48
84
47
46
85
87
88
89
90
91
92
CE
45
44
86
43
M16C / 64 Group
Flash Memory Version
42
EPM
41
40
39
93
38
94
37
95
96
36
35
97
34
33
BUSY
32
RXD
98
99
SCLK
31
100
TXD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSS
Mode setup method
Signal
CNVSS
VCC1
CNVSS
RESET
Connect
oscillator
circuit
Oct 12, 2007
EPM
VSS
RESET
VSS to VCC1
CE
VCC2
Package: PRQP0100JD-B (100P6F-A)
Figure 22.20 Pin Connections for Standard Serial I/O Mode (1)
REJ09B0392-0064 Rev.0.64
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Value
VCC1
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
22. Flash Memory Version
VCC2
M16C/64 Group
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
79
80
47
81
45
82
44
83
84
43
42
85
41
46
86
87
40
39
M16C / 64 Group
Flash Memory Version
88
89
90
CE
EPM
38
37
36
91
35
92
93
34
33
94
32
BUSY
95
96
31
30
29
RXD
97
98
SCLK
TXD
28
27
26
99
100
1
2 3
4 5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
Mode setup method
Signal
Value
CNVSS VCC1
Connect
oscillator
circuit
CE
VCC1
CNVSS
RESET
EPM
VSS
RESET VSS to VCC1
Package: PLQP0100KB-A (100P6Q-A)
Figure 22.21 Pin Connections for Standard Serial I/O Mode (2)
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Oct 12, 2007
VCC2
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.4.2
22. Flash Memory Version
Example of Circuit Application in the Standard Serial I/O Mode
Figures 22.22 and 22.23 show examples of Circuit Application in Standard Serial I/O Mode 1 and Mode
2, respectively. Refer to the user's manual of your serial programmer to handle pins controlled by the
serial programmer.
VCC1
Microcomputer
SCLK input
VCC2
P6_5 / CLK1
VCC1
P5_0 (CE)
P6_7 / TXD1
TXD output
P5_5 (EPM)
VCC1
P6_4 / RTS1
BUSY output
RXD input
VCC1
Reset input
P6_6 / RXD1
CNVSS
RESET
User reset signal
NOTES:
1. Control pins and external circuitry will vary according to a programmer.
For more information, see the programmer manual.
2. In this example, modes are switched between single-chip mode and standard
serial input / output mode by controlling the CNVSS input with a switch.
3. If in standard serial input / output mode 1 there is a possibility that the user reset
signal will go low during serial input / output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 22.22 Circuit Application in Standard Serial I/O Mode 1
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22. Flash Memory Version
Microcomputer
TXD output
P6_5 / CLK1
P5_0 (CE)
P6_7 / TXD1
P5_5 (EPM)
VCC2
VCC1
P6_4 / RTS1
Monitor output
RXD intput
VCC1
Reset input
P6_6 / RXD1
CNVSS
RESET
User reset signal
NOTE:
1. In this example, modes are switched between single-chip mode and standard serial input /
output mode by controlling the CNVSS input with a switch.
Figure 22.23 Circuit Application in Standard Serial I/O Mode 2
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
22.5
22. Flash Memory Version
Parallel I/O Mode
In parallel I/O mode, the program ROM 1 and program ROM 2 can be rewritten by a parallel programmer
supporting the M16C/64 Group. Contact your parallel programmer manufacturer for more information on
the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions.
22.5.1
ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten. (Refer to
22.2 “Functions to Prevent Flash Memory from Rewriting”.)
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
23. Electrical Characteristics
23.1
Electrical Characteristics
Table 23.1
Absolute Maximum Ratings
Rated Value
Unit
VCC1,
VCC2
Symbol
Supply Voltage
Parameter
VCC1=VCC2
=AVCC
Condition
−0.3 to 6.5
V
AVCC
Analog Supply Voltage
VCC1=AVCC
−0.3 to 6.5
V
VI
Input Voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7,
P14_0, P14_1,
XIN
−0.3 to VCC1+0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
−0.3 to VCC2+0.3
V
−0.3 to 6.5
V
−0.3 to VCC1+0.3
V
−0.3 to VCC2+0.3
V
−0.3 to 6.5
V
300
mW
−20 to 85 / −40 to 85
°C
P7_0, P7_1, P8_5
VO
Output Voltage P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XOUT
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
P7_0, P7_1, P8_5
−40°C<Topr≤85°C
Pd
Power Dissipation
Topr
Operating
When the Microcomputer is Operating
Ambient Tem- Flash Program Erase
perature
Tstg
Storage Temperature
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
0 to 60
−65 to 150
°C
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 23.2
23. Electrical Characteristics
Recommended Operating Conditions (1)
Symbol
VCC1,
VCC2
Parameter
Standard
Supply Voltage (VCC1 = VCC2)
Unit
Min.
Typ.
Max.
2.7
5.0
5.5
V
AVCC
Analog Supply Voltage
VCC1
V
VSS
Supply Voltage
0
V
AVSS
Analog Supply Voltage
0
V
VIH
HIGH Input Volt- P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
age
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
VIL
0.8VCC2
VCC2
V
0.8VCC2
VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0.5VCC2
VCC2
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
0.8VCC1
VCC1
V
P7_0, P7_1, P8_5
0.8VCC1
6.5
V
0
0.2VCC2
V
0
0.2VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0
0.16VCC2
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
0
0.2VCC
V
LOW Input Volt- P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
age
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
IOH(peak)
HIGH Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
−10.0
mA
IOH(avg)
HIGH Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
−5.0
mA
IOL(peak)
LOW Peak Out- P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
put Current
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
10.0
mA
IOL(avg)
LOW Average
Output Current
5.0
mA
20
MHz
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7
f(XIN)
Main Clock Input Oscillation Frequency
f(XCIN)
Sub-Clock Oscillation Frequency
f(OCO)
125kHz On-chip Oscillation Frequency
VCC1=2.7V to 5.5V
0
32.768
50
125
f(PLL)
PLL Clock Oscillation Frequency
f(BCLK)
CPU Operation Clock
VCC1=2.7V to 5.5V
tSU(PLL)
PLL Frequency Synthesizer Stabilization Wait VCC1=5.5V
Time
kHz
kHz
10
25
MHz
0
25
MHz
20
ms
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7 and P8_0 to P8_5 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2
must be −40mA max. The total IOH(peak) for ports P3, P4 and P5 must be −40mA max. The total IOH(peak) for
ports P6, P7_2 to P7_7 and P8_0 to P8_4 must be −40mA max.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 23.3
23. Electrical Characteristics
A/D Conversion Characteristics (1)
Symbol
Parameter
Measuring Condition
Standard
Min.
-
Resolution
INL
Integral Non-Linearity
Error
-
Absolute Accuracy
10bit
10bit
Typ.
Unit
Max.
VREF=VCC1
10
Bits
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
5.0V
ANEX0, ANEX1 input
±3
LSB
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
3.3V
ANEX0, ANEX1 input
±3
LSB
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
3.0V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
±3
LSB
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5.0V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
±3
LSB
VREF= AN0 to AN7 input,
VCC1 AN0_0 to AN0_7 input,
=3.3V AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
±3
LSB
VREF= AN0 to AN7 input,
VCC1 AN0_0 to AN0_7 input,
=3.0V AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
±3
LSB
kΩ
-
Tolerance Level Impedance
DNL
Differential Non-Linearity Error
3
±1
LSB
-
Offset Error
±3
LSB
±3
LSB
40
kΩ
-
Gain Error
RLADDER
Ladder Resistance
VREF=VCC1
tCONV
10-bit Conversion Time
VREF=VCC1=5V, φAD=25MHz
tSAMP
Sampling Time
VREF
Reference Voltage
VIA
Analog Input Voltage
NOTES:
1.
2.
3.
10
1.60
μs
0.60
μs
VCC1
0
V
VREF
V
Referenced to VCC1=AVCC=VREF=3.0 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85°C / -40 to 85°C unless otherwise specified.
Set φAD frequency as follows:
When VCC1 = 4.0 to 5.5 V, 2 MHz ≤ φAD ≤ 25 MHz
When VCC1 = 3.2 to 4.0 V, 2 MHz ≤ φAD ≤ 16 MHz
When VCC1 = 3.0 to 3.2 V, 2 MHz ≤ φAD ≤ 10 MHz
Use when VREF=VCC1.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 23.4
23. Electrical Characteristics
D/A Conversion Characteristics (1)
Symbol
Parameter
Measuring Condition
Standard
Min.
-
Resolution
-
Absolute Accuracy
tSU
Setup Time
RO
Output Resistance
IVREF
Reference Power Supply Input Current
NOTES:
1.
2.
Typ.
Unit
Max.
8
Bits
2.5
LSB
3
(NOTE 2)
μs
kΩ
6
1.5
mA
Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85°C / -40 to 85°C unless otherwise specified.
This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor ladder
of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id disconnected by the A/D control register.
Table 23.5
Flash Memory Version Electrical Characteristics (1)
Symbol
Parameter
Standard
Min.
-
Program and Erase Endurance (2)
-
Typ.
Unit
Max.
Other than data flash
100
cycle
Data flash
100
cycle
2 Word Program Time
(VCC1=3.3V at Topr=25°C)
Other than data flash
150
μs
Data flash
300
μs
Lock Bit Program Time
(VCC1=3.3V at Topr=25°C)
Other than data flash
70
μs
140
μs
Block Erase Time
(VCC1=3.3V at Topr=25°C)
4-Kbyte block
0.20
s
16-Kbyte block
0.20
s
64-Kbyte block
0.20
-
Data flash
tPS
Flash Memory Circuit Stabilization Wait Time
-
Data Hold Time (3)
s
50
10
μs
year
NOTES:
1. Referenced to VCC1=2.7 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2. Definition of program and erase endurance
The program and erase endurance refers to the number of per-block erasures.
If the program and erase endurance is n (n=100), each block can be erased n times.
For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this
counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited)
3. Topr = -40 to 85 °C / -20 to 85 °C
Table 23.6
Flash Memory Version Program / Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C)
Flash Program, Erase Voltage
Flash Read Operation Voltage
VCC2 = 2.7 to 5.5 V
VCC1=2.7 to 5.5 V
REJ09B0392-0064 Rev.0.64
Page 304 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 23.7
23. Electrical Characteristics
Low Voltage Detection Circuit Electrical Characteristics
Symbol
Parameter
Measuring Condition
Standard
Min.
VCC1=0.8V to 5.5V
Vdet2
Low Voltage Detection Voltage (1)
Vdet0
Reset Level Detection
Voltage (1)
Vdet2 -Vdet0
Electric potential difference of Low Voltage
Detection and Reset Level Detection
Vdet0s
Low Voltage Reset Retention Voltage
Vdet0r
Low Voltage Reset Release Voltage
3.3
Unit
Typ.
Max.
3.8
4.4
1.9
0.3
V
0.8
2.0
(2)
V
V
V
V
NOTES:
1. Vdet2 > Vdet0.
2. Vdet0r > Vdet0 is not guaranteed.
3. The voltage detection circuit is designed to use when VCC1 is set to 5V.
Table 23.8
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Measuring Condition
Standard
Min.
td(P-R)
Time for Internal Power Supply Stabilization During Powering-On
td(R-S)
td(W-S)
td(S-R)
Brown-out Detection Reset (Hardware
Reset 2) Release Wait Time
VCC1=Vdet3r to 5.5V
td(E-A)
Low Voltage Detection Circuit Operation
Start Time
VCC1=2.7V to 5.5V
Typ.
5
ms
STOP Release Time
150
μs
Low Power Dissipation Mode Wait Mode
Release Time
150
μs
20
ms
20
μs
NOTE:
1. When VCC1 = 5V.
REJ09B0392-0064 Rev.0.64
Page 305 of 373
Oct 12, 2007
VCC1=2.7V to 5.5V
Unit
Max.
6 (1)
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
Recommended
operation voltage
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
VCC1
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
CPU clock
(a)
td(R-S)
(b)
td(W-S)
td(S-R)
Low Voltage Detection
Reset (Hardware Reset 2)
Release Wait Time
Vdet3r
VCC1
td(S-R)
CPU clock
td(E-A)
VC26, VC27
Low Voltage Detection Circuit
Operation Start Time
Low Voltage
Detection Circuit
Stop
Operate
td(E-A)
Figure 23.1
Power Supply Circuit Timing Diagram
REJ09B0392-0064 Rev.0.64
Page 306 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Table 23.9
Electrical Characteristics (1)
Symbol
(1)
Parameter
Measuring Condition
Standard
Min.
VOH
VOH
VOH
VOL
VOL
IOH=−5mA
VCC1−2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOH=−5mA
VCC2−2.0
VCC2
HIGH Output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
Voltage
OH=−200μA
VCC1−0.3
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOH=−200μA
VCC2−0.3
VCC2
HIGH Output Voltage
LOW Output
Voltage
LOW Output
Voltage
XOUT
XCOUT
HIGHPOWER
IOH=−1mA
VCC1−2.0
VCC1
LOWPOWER
IOH=−0.5mA
VCC1−2.0
VCC1
HIGHPOWER
With no load applied
2.9
LOWPOWER
With no load applied
2.2
IOL=5mA
2.0
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOL=5mA
2.0
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOL=200μA
0.45
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOL=200μA
0.45
HIGHPOWER
IOL=1mA
2.0
LOWPOWER
IOL=0.5mA
2.0
LOW Output Voltage
XOUT
XCOUT
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
Hysteresis
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7,
SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2,
SDA5 to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT,
KI0 to KI3, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4
VT+-VT-
Hysteresis
RESET
IIH
HIGH Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=5V
IIL
LOW Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=0V
RPULLUP Pull-Up
Resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VI=0V
V
V
V
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7
LOW Output Voltage
VT+-VT-
Unit
Max.
HIGH Output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
Voltage
HIGH Output Voltage
VOL
Typ.
V
V
V
V
0.2
1.0
0.2
2.5
V
5.0
μA
−5.0
μA
170
kΩ
30
50
V
RfXIN
Feedback Resistance XIN
1.5
MΩ
RfXCIN
Feedback Resistance XCIN
15
MΩ
VRAM
RAM Retention Voltage
At stop mode
2.0
V
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=25MHz unless
otherwise specified.
REJ09B0392-0064 Rev.0.64
Page 307 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 23.10
Symbol
23. Electrical Characteristics
Electrical Characteristics (2) (1)
Parameter
Measuring Condition
Standard
Min.
ICC
Idet2
Idet0
Reset Area Detection Dissipation Current
(4)
Unit
Max.
f(BCLK)=25MHz,
No division,
PLL operation
20
mA
No division,
125 kHz On-chip
oscillation
450
μA
Flash Memory
Program
f(BCLK)=10MHz,
VCC1=5.0V
20
mA
Flash Memory
Erase
f(BCLK)=10MHz,
VCC1=5.0V
30
mA
Flash Memory
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
45
μA
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
FMR22=FMR23=1
160
μA
125 kHz On-chip
oscillation,
Wait mode
12
μA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
11.5
μA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
6.2
μA
Stop mode
Topr =25°C
3.0
μA
3.0
μA
6.0
μA
Flash
Power Supply Current
In single-chip
Memory
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
other pins are VSS
Low Voltage Detection Dissipation Current (4)
Typ.
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=25MHz unless
otherwise specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet2: VC27 bit in the VCR2 register
Idet0: VC25 bit in the VCR2 register
REJ09B0392-0064 Rev.0.64
Page 308 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.11
External Clock Input (XIN input) (1)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc
External Clock Input Cycle Time
50
ns
tw(H)
External Clock Input HIGH Pulse Width
25
ns
tw(L)
External Clock Input LOW Pulse Width
25
tr
External Clock Rise Time
15
ns
tf
External Clock Fall Time
15
ns
ns
NOTE:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 23.12
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Unit
Max.
tac1(RD-DB)
Data Input Access Time (for setting with no wait)
(NOTE 1)
ns
tac2(RD-DB)
Data Input Access Time (for setting with wait)
(NOTE 2)
ns
tac3(RD-DB)
Data Input Access Time (when accessing multiplex bus area)
(NOTE 3)
ns
tsu(DB-RD)
Data Input Setup Time
40
ns
tsu(RDY-BCLK) RDY Input Setup Time
30
ns
tsu(HOLDBCLK)
HOLD Input Setup Time
40
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
0
ns
th(BCLK-HOLD) HOLD Input Hold Time
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 45 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
3.
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
REJ09B0392-0064 Rev.0.64
Page 309 of 373
n is “2” for 2-wait setting, “3” for 3-wait setting.
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.13
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
100
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
40
ns
tw(TAL)
TAiIN Input LOW Pulse Width
40
ns
Table 23.14
Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
Standard
Min.
tc(TA)
TAiIN Input Cycle Time
Unit
Max.
400
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
200
ns
tw(TAL)
TAiIN Input LOW Pulse Width
200
ns
Table 23.15
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
200
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
100
ns
tw(TAL)
TAiIN Input LOW Pulse Width
100
ns
Table 23.16
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tw(TAH)
TAiIN Input HIGH Pulse Width
100
ns
tw(TAL)
TAiIN Input LOW Pulse Width
100
ns
Table 23.17
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(UP)
TAiOUT Input Cycle Time
2000
ns
tw(UPH)
TAiOUT Input HIGH Pulse Width
1000
ns
tw(UPL)
TAiOUT Input LOW Pulse Width
1000
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
400
ns
th(TIN-UP)
TAiOUT Input Hold Time
400
ns
Table 23.18
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
tc(TA)
TAiIN Input Cycle Time
Unit
Max.
800
ns
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
200
ns
tsu(TAOUT-TAIN) TAiIN Input Setup Time
200
ns
REJ09B0392-0064 Rev.0.64
Page 310 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.19
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on one edge)
40
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on one edge)
40
ns
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
200
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on both edges)
80
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on both edges)
80
ns
Table 23.20
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TB)
TBiIN Input Cycle Time
400
tw(TBH)
TBiIN Input HIGH Pulse Width
200
ns
tw(TBL)
TBiIN Input LOW Pulse Width
200
ns
Table 23.21
ns
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TB)
TBiIN Input Cycle Time
400
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
200
ns
tw(TBL)
TBiIN Input LOW Pulse Width
200
ns
Table 23.22
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(AD)
ADTRG Input Cycle Time
1000
ns
tw(ADL)
ADTRG input LOW Pulse Width
125
ns
Table 23.23
Serial Interface
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(CK)
CLKi Input Cycle Time
200
ns
tw(CKH)
CLKi Input HIGH Pulse Width
100
ns
tw(CKL)
CLKi Input LOW Pulse Width
100
ns
td(C-Q)
TXDi Output Delay Time
th(C-Q)
TXDi Hold Time
0
ns
tsu(D-C)
RXDi Input Setup Time
70
ns
th(C-D)
RXDi Input Hold Time
90
ns
Table 23.24
80
ns
External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tw(INH)
INTi Input HIGH Pulse Width
250
ns
tw(INL)
INTi Input LOW Pulse Width
250
ns
REJ09B0392-0064 Rev.0.64
Page 311 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.25
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Unit
Max.
25
ns
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
4
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
ns
25
ns
15
ns
25
ns
4
ns
−4
See
Figure 23.2
ns
0
ns
25
0
ns
40
ns
ns
Data Output Delay Time (in relation to WR)
(NOTE 1)
th(WR-DB)
Data Output Hold Time (in relation to WR) (3)
(NOTE 2)
td(BCLK-HLDA)
HLDA Output Delay Time
ns
40
NOTES:
2.
3.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ]
f(BCLK) is 12.5MHz or less.
f ( BCLK )
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 23.2
Ports P0 to P14 Measurement Circuit
REJ09B0392-0064 Rev.0.64
Page 312 of 373
Oct 12, 2007
R
DBi
C
30pF
ns
4
td(DB-WR)
1.
ns
ns
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.26
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Unit
Max.
25
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
ns
4
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
ns
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
25
15
See
Figure 23.2
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to
ns
25
ns
0
ns
25
td(DB-WR)
HLDA Output Delay Time
ns
ns
0
th(BCLK-DB)
th(WR-DB)
ns
-4
td(BCLK-WR)
td(BCLK-HLDA)
ns
4
(3)
WR)(3)
ns
40
ns
4
ns
(NOTE 1)
ns
(NOTE 2)
ns
40
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
2.
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3.
This standard value shows the timing when the output is
off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pullup (pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ,
hold time of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
REJ09B0392-0064 Rev.0.64
Page 313 of 373
Oct 12, 2007
R
DBi
C
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.27
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
th(RD-AD)
th(WR-AD)
Measuring
Condition
Standard
Min.
Unit
Max.
25
ns
4
ns
Address Output Hold Time (in relation to RD)
(NOTE 1)
ns
Address Output Hold Time (in relation to WR)
(NOTE 1)
ns
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
25
4
ns
ns
th(RD-CS)
Chip Select Output Hold Time (in relation to RD)
(NOTE 1)
ns
th(WR-CS)
Chip Select Output Hold Time (in relation to WR)
(NOTE 1)
ns
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
25
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)
4
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
(NOTE 2)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)
(NOTE 1)
ns
0
ns
25
See
Figure 23.2
ns
0
ns
ns
40
ns
td(BCLK-HLDA) HLDA Output Delay Time
40
ns
td(BCLK-ALE) ALE Signal Output Delay Time (in relation to BCLK)
15
ns
−4
ns
td(AD-ALE)
ALE Signal Output Delay Time (in relation to Address)
(NOTE 3)
ns
th(AD-ALE)
ALE Signal Output Hold Time (in relation to Address)
(NOTE 4)
ns
td(AD-RD)
RD Signal Output Delay From the End of Address
0
ns
td(AD-WR)
WR Signal Output Delay From the End of Address
0
tdz(RD-AD)
Address Output Floating Start Time
th(BCLK-ALE) ALE Signal Output Hold Time (in relation to BCLK)
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
3.
n is “2” for 2-wait setting, “3” for 3-wait setting.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 25 [ ns ]
f ( BCLK )
4.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 15 [ ns ]
f ( BCLK )
REJ09B0392-0064 Rev.0.64
Page 314 of 373
Oct 12, 2007
ns
8
ns
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
th(TIN-UP) tsu(UP-TIN)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 23.3
Timing Diagram (1)
REJ09B0392-0064 Rev.0.64
Page 315 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 23.4
Timing Diagram (2)
REJ09B0392-0064 Rev.0.64
Page 316 of 373
Oct 12, 2007
th(C-D)
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA input
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK−HLDA)
Hi−Z
(1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
· Measuring conditions :
· VCC1=VCC2=5V
· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
· Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 23.5
Timing Diagram (3)
REJ09B0392-0064 Rev.0.64
Page 317 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
25ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
25ns.max
RD
th(BCLK-RD)
0ns.min
tac1(RD-DB)
(0.5 × tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 23.6
Timing Diagram (4)
REJ09B0392-0064 Rev.0.64
Page 318 of 373
Oct 12, 2007
th(WR-DB)
(0.5 × tcyc-10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
ADi
BHE
4ns.min
th(RD-AD)
0ns.min
th(BCLK-ALE)
td(BCLK-ALE)
25ns.max
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
0ns.min
25ns.max
RD
tac2(RD-DB)
(1.5×tcyc-45)ns.max
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
4ns.min
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
WR, WRL,
WRH
th(BCLK-WR)
0ns.min
td(BCLK-DB)
DBi
tcyc=
td(DB-WR)
(0.5×tcyc-40)ns.min
1
f(BCLK)
・Measuring conditions
・VCC1=VCC2=5V
・Input timing voltage : VIL=0.8V, VIH=2.0V
・Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 23.7
Timing Diagram (5)
REJ09B0392-0064 Rev.0.64
Page 319 of 373
Oct 12, 2007
th(BCLK-DB)
40ns.max
Hi-Z
4ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
ALE
RD
tac2(RD-DB)
(2.5×tcyc-45)ns.max
DBi
Hi-Z
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
4ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
CSi
ADi
BHE
td(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5×tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
40ns.max
Hi-Z
DBi
Tcyc=
td(DB-WR)
(1.5×tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.8
th(BCLK-DB)
4ns.min
Timing Diagram (6)
REJ09B0392-0064 Rev.0.64
Page 320 of 373
Oct 12, 2007
th(WR-DB)
(0.5×tcyc-10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
25ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
25ns.max
0ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
25ns.max
RD
tac2(RD-DB)
(3.5×tcyc-45)ns.max
DBi
Hi-Z
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
25ns.max
4ns.min
td(BCLK-AD)
th(BCLK-AD)
CSi
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
25ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
(2.5×tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.9
Timing Diagram (7)
REJ09B0392-0064 Rev.0.64
Page 321 of 373
Oct 12, 2007
th(WR-DB)
(0.5×tcyc-10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection )
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
25ns.max
4ns.min
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
ADi
/DBi
(0.5×tcyc-15)ns.min
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-45)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
40ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
(0.5×tcyc-10)ns.min
th(BCLK-ALE)
25ns.max
−4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
25ns.max
0ns.min
RD
Write timing
BCLK
th(BCLK-CS)
th(WR-CS)
tcyc
td(BCLK-CS)
4ns.min
(0.5×tcyc-10)ns.min
25ns.max
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
40ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-40)ns.min
td(AD-ALE)
(0.5×tcyc-25)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
td(AD-WR)
−4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
25ns.max
WR,WRL,
WRH
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.10 Timing Diagram (8)
REJ09B0392-0064 Rev.0.64
Page 322 of 373
Oct 12, 2007
th(BCLK-WR)
0ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
25ns.max
th(BCLK-CS)
4ns.min
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
ADi
/DBi
(0.5×tcyc-15)ns.min
Address
td(BCLK-AD)
8ns.max
td(AD-RD)
25ns.max
ADi
BHE
Data input
tdZ(RD-AD)
tac3(RD-DB)
(2.5×tcyc-45)ns.max
0ns.min
tsu(DB-RD)
th(RD-DB)
0ns.min
th(BCLK-AD)
4ns.min
40ns.min
(no multiplex)
td(BCLK-ALE)
25ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
25ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
25ns.max
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
40ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5×tcyc-25)ns.min
td(DB-WR)
(2.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
th(WR-AD)
-4ns.min
td(AD-WR)
(0.5×tcyc-10)ns.min
0ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
25ns.max
WR, WRL
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 23.11 Timing Diagram (9)
REJ09B0392-0064 Rev.0.64
Page 323 of 373
Oct 12, 2007
0ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Table 23.28
Electrical Characteristics (1)
Symbol
(1)
Parameter
Measuring Condition
Standard
Min.
VOH
VOH
HIGH Output Voltage
IOH=−1mA
VCC1−
0.5
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOH=−1mA (2)
VCC2−
0.5
VCC2
HIGHPOWER
IOH=−0.1mA
VCC1−
0.5
VCC1
LOWPOWER
IOH=−50μA
VCC1−
0.5
VCC1
HIGH Output Voltage
VOL
LOW Output Voltage
Unit
Max.
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
HIGH Output Voltage
VOL
Typ.
XOUT
XCOUT
HIGHPOWER
With no load applied
2.9
LOWPOWER
With no load applied
2.2
IOL=1mA
0.5
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
IOL=1mA (2)
0.5
LOW Output Voltage
XOUT
XCOUT
HIGHPOWER
IOL=0.1mA
0.5
LOWPOWER
IOL=50μA
0.5
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
V
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
LOW Output Voltage
V
V
V
V
VT+-VT- Hysteresis
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT7, NMI,
ADTRG, CTS0 to CTS2, CTS5 to CTS7,
SCL0 to SCL2, SCL5 to SCL7,
SDA0 to SDA2, SDA5 to SDA7,
CLK0 to CLK7, TA0OUT to TA4OUT,
KI0 to KI3, RXD0 to RXD2, RXD5 to RXD7,
SIN3, SIN4
VT+-VT- Hysteresis
RESET
1.8
V
IIH
HIGH Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=3V
4.0
μA
IIL
LOW Input
Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
XIN, RESET, CNVSS, BYTE
VI=0V
−4.0
μA
RPULLUP
Pull-Up
Resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
VI=0V
500
kΩ
RfXIN
Feedback Resistance XIN
0.2
0.2
RfXCIN
Feedback Resistance XCIN
VRAM
RAM Retention Voltage
At stop mode
50
2.0
0.8
(0.7)
100
V
3.0
MΩ
25
MΩ
V
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=25MHz
unless otherwise specified.
2. VCC1 for the port P6 to P10 and VCC2 for the port P0 to P5.
REJ09B0392-0064 Rev.0.64
Page 324 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Table 23.29
Symbol
23. Electrical Characteristics
Electrical Characteristics (2) (1)
Parameter
Measuring Condition
Standard
Min.
ICC
In single-chip mode, Flash
Power Supply Current
Memory
(VCC1=VCC2=2.7V to 3.6V) the output pins are
open and other pins
are VSS
20
mA
No division,
125 kHz On-chip oscillation
450
μA
Flash Memory
Program
f(BCLK)=10MHz,
VCC1=3.0V
20
mA
Flash Memory
Erase
f(BCLK)=10MHz,
VCC1=3.0V
30
mA
Flash Memory
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
40
μA
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
FMR22=FMR23=1
160
μA
9
μA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability
High
9.5
μA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability
Low
5.7
μA
3
μA
3
μA
6
μA
Stop mode
Topr =25°C
Idet0
Low Voltage Detection Dissipation Current (4)
Reset Area Detection Dissipation Current
(4)
Unit
Max.
f(BCLK)=25MHz,
No division
125 kHz On-chip
oscillation,
Wait mode
Idet2
Typ.
NOTES:
1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C,
f(BCLK)=25MHz unless otherwise specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet2: VC27 bit in the VCR2 register
Idet0: VC25 bit in the VCR2 register
REJ09B0392-0064 Rev.0.64
Page 325 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
External Clock Input (XIN input)(1)
Table 23.30
Symbol
Parameter
Standard
Min.
Unit
Max.
tc
External Clock Input Cycle Time
50
ns
tw(H)
External Clock Input HIGH Pulse Width
20
ns
tw(L)
External Clock Input LOW Pulse Width
20
ns
tr
External Clock Rise Time
9
ns
tf
External Clock Fall Time
9
ns
NOTE:
1. The condition is VCC1=VCC2=2.7 to 3.0V.
Table 23.31
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Unit
Max.
tac1(RD-DB)
Data Input Access Time (for setting with no wait)
(NOTE 1)
ns
tac2(RD-DB)
Data Input Access Time (for setting with wait)
(NOTE 2)
ns
tac3(RD-DB)
Data Input Access Time (when accessing multiplex bus area)
(NOTE 3)
ns
tsu(DB-RD)
Data Input Setup Time
50
ns
tsu(RDY-BCLK)
RDY Input Setup Time
40
ns
tsu(HOLD-BCLK) HOLD Input Setup Time
50
ns
th(RD-DB)
Data Input Hold Time
0
ns
th(BCLK-RDY)
RDY Input Hold Time
0
ns
th(BCLK-HOLD)
HOLD Input Hold Time
0
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 60 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
3.
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
REJ09B0392-0064 Rev.0.64
Page 326 of 373
n is “2” for 2-wait setting, “3” for 3-wait setting.
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.32
Timer A Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
150
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
60
ns
tw(TAL)
TAiIN Input LOW Pulse Width
60
ns
Table 23.33
Timer A Input (Gating Input in Timer Mode)
Symbol
Parameter
Standard
Min.
tc(TA)
TAiIN Input Cycle Time
Unit
Max.
600
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
300
ns
tw(TAL)
TAiIN Input LOW Pulse Width
300
ns
Table 23.34
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TA)
TAiIN Input Cycle Time
300
ns
tw(TAH)
TAiIN Input HIGH Pulse Width
150
ns
tw(TAL)
TAiIN Input LOW Pulse Width
150
ns
Table 23.35
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tw(TAH)
TAiIN Input HIGH Pulse Width
150
ns
tw(TAL)
TAiIN Input LOW Pulse Width
150
ns
Table 23.36
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(UP)
TAiOUT Input Cycle Time
3000
ns
tw(UPH)
TAiOUT Input HIGH Pulse Width
1500
ns
tw(UPL)
TAiOUT Input LOW Pulse Width
1500
ns
tsu(UP-TIN)
TAiOUT Input Setup Time
600
ns
th(TIN-UP)
TAiOUT Input Hold Time
600
ns
Table 23.37
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
2
μs
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
500
ns
tsu(TAOUT-TAIN) TAiIN Input Setup Time
500
ns
tc(TA)
TAiIN Input Cycle Time
REJ09B0392-0064 Rev.0.64
Page 327 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.38
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
150
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on one edge)
60
ns
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on one edge)
60
tc(TB)
TBiIN Input Cycle Time (counted on both edges)
300
ns
tw(TBH)
TBiIN Input HIGH Pulse Width (counted on both edges)
120
ns
tw(TBL)
TBiIN Input LOW Pulse Width (counted on both edges)
120
ns
Table 23.39
Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TB)
TBiIN Input Cycle Time
600
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
300
ns
tw(TBL)
TBiIN Input LOW Pulse Width
300
ns
Table 23.40
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(TB)
TBiIN Input Cycle Time
600
ns
tw(TBH)
TBiIN Input HIGH Pulse Width
300
ns
tw(TBL)
TBiIN Input LOW Pulse Width
300
ns
Table 23.41
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(AD)
ADTRG Input Cycle Time
1500
ns
tw(ADL)
ADTRG Input LOW Pulse Width
200
ns
Table 23.42
Serial Interface
Symbol
Parameter
Standard
Min.
Unit
Max.
tc(CK)
CLKi Input Cycle Time
300
ns
tw(CKH)
CLKi Input HIGH Pulse Width
150
ns
tw(CKL)
CLKi Input LOW Pulse Width
150
td(C-Q)
TXDi Output Delay Time
th(C-Q)
TXDi Hold Time
tsu(D-C)
RXDi Input Setup Time
100
ns
th(C-D)
RXDi Input Hold Time
90
ns
Table 23.43
ns
160
0
ns
ns
External Interrupt INTi Input
Symbol
Parameter
Standard
Min.
Unit
Max.
tw(INH)
INTi Input HIGH Pulse Width
380
ns
tw(INL)
INTi Input LOW Pulse Width
380
ns
REJ09B0392-0064 Rev.0.64
Page 328 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.44
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Unit
Max.
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
4
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 2)
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
td(BCLK-ALE)
ALE Signal Output Delay Time
th(BCLK-ALE)
ALE Signal Output Hold Time
td(BCLK-RD)
RD Signal Output Delay Time
30
RD Signal Output Hold Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK) (3)
td(DB-WR)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
4
See
Figure 23.12
WR Signal Output Delay Time
HLDA Output Delay Time
ns
30
ns
30
ns
ns
0
ns
ns
40
ns
4
(3)
ns
(NOTE 1)
ns
(NOTE 2)
ns
40
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 23.12 Ports P0 to P14 Measurement Circuit
Oct 12, 2007
ns
25
0
NOTES:
1.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ] f (BCLK) is 12.5MHz or less.
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
This standard value shows the timing when the output is off, and does
not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pulldown) resistance value.
Hold time of data bus is expressed in
t= −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ,
hold time of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
REJ09B0392-0064 Rev.0.64
Page 329 of 373
ns
−4
td(BCLK-WR)
td(BCLK-HLDA)
ns
30
th(BCLK-RD)
th(WR-DB)
ns
ns
R
DBi
C
30pF
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.45
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
Parameter
Measuring
Condition
Standard
Min.
30
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
th(RD-AD)
th(WR-AD)
ns
4
ns
Address Output Hold Time (in relation to RD)
0
ns
Address Output Hold Time (in relation to WR)
(NOTE 2)
ns
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
30
ns
25
th(BCLK-ALE) ALE Signal Output Hold Time
See
Figure
23.12
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
ns
-4
ns
30
ns
0
ns
30
ns
0
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)
td(DB-WR)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to
ns
4
td(BCLK-ALE) ALE Signal Output Delay Time
th(WR-DB)
Unit
Max.
(3)
WR)(3)
ns
40
ns
4
ns
(NOTE 1)
ns
(NOTE 2)
td(BCLK-HLDA) HLDA Output Delay Time
ns
40
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
2.
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3.
This standard value shows the timing when the output is off, and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t=−CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R =
1kΩ, hold time of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
REJ09B0392-0064 Rev.0.64
Page 330 of 373
Oct 12, 2007
R
DBi
C
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 23.46
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Parameter
td(BCLK-AD)
Address Output Delay Time
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
th(RD-AD)
th(WR-AD)
Measuring
Condition
Standard
Min.
Unit
Max.
50
ns
4
ns
Address Output Hold Time (in relation to RD)
(NOTE 1)
ns
Address Output Hold Time (in relation to WR)
(NOTE 1)
ns
td(BCLK-CS)
Chip Select Output Delay Time
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
50
4
ns
ns
th(RD-CS)
Chip Select Output Hold Time (in relation to RD)
(NOTE 1)
ns
th(WR-CS)
Chip Select Output Hold Time (in relation to WR)
(NOTE 1)
ns
td(BCLK-RD)
RD Signal Output Delay Time
th(BCLK-RD)
RD Signal Output Hold Time
40
td(BCLK-WR)
WR Signal Output Delay Time
th(BCLK-WR)
WR Signal Output Hold Time
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)
4
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
(NOTE 2)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)
(NOTE 1)
ns
0
See
Figure
23.12
ns
ns
40
0
ns
ns
50
ns
td(BCLK-HLDA) HLDA Output Delay Time
40
ns
td(BCLK-ALE) ALE Signal Output Delay Time (in relation to BCLK)
25
ns
−4
ns
td(AD-ALE)
ALE Signal Output Delay Time (in relation to Address)
(NOTE 3)
ns
th(AD-ALE)
ALE Signal Output Hold Time (in relation to Address)
(NOTE 4)
ns
td(AD-RD)
RD Signal Output Delay From the End of Address
0
ns
td(AD-WR)
WR Signal Output Delay From the End of Address
0
tdz(RD-AD)
Address Output Floating Start Time
th(BCLK-ALE) ALE Signal Output Hold Time (in relation to BCLK)
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
2.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 50 [ ns ]
f ( BCLK )
3.
n is “2” for 2-wait setting, “3” for 3-wait setting.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ]
f ( BCLK )
4.
Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 15 [ ns ]
f ( BCLK )
REJ09B0392-0064 Rev.0.64
Page 331 of 373
Oct 12, 2007
ns
8
ns
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in
Event Counter Mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 23.13 Timing Diagram (1)
REJ09B0392-0064 Rev.0.64
Page 332 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 23.14 Timing Diagram (2)
REJ09B0392-0064 Rev.0.64
Page 333 of 373
Oct 12, 2007
th(C-D)
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA output
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
td(BCLK−HLDA)
Hi−Z
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
· VCC1=VCC2=3V
· Input timing voltage : Determined with V IL=0.6V, VIH=2.4V
· Output timing voltage : Determined with V OL=1.5V, VOH=1.5V
Figure 23.15 Timing Diagram (3)
REJ09B0392-0064 Rev.0.64
Page 334 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
ADi
BHE
4ns.min
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
30ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
4ns.min
th(BCLK-ALE)
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
30ns.max
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(BCLK-DB)
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.16 Timing Diagram (4)
REJ09B0392-0064 Rev.0.64
Page 335 of 373
Oct 12, 2007
th(WR-DB)
(0.5 × tcyc-10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
ADi
BHE
td(BCLK−ALE)
4ns.min
th(RD−AD)
th(BCLK−ALE)
0ns.min
−4ns.min
30ns.max
ALE
td(BCLK−RD)
th(BCLK−RD)
0ns.min
30ns.max
RD
tac2(RD−DB)
(1.5 × tcyc−60)ns.max
Hi−Z
DBi
th(RD−DB)
tsu(DB−RD)
0ns.min
50ns.min
Write timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK−ALE)
th(BCLK−ALE)
th(WR−AD)
(0.5 × tcyc−10)ns.min
−4ns.min
30ns.max
ALE
td(BCLK−WR)
30ns.max
th(BCLK−WR)
0ns.min
WR,WRL,
WRH
td(BCLK−DB)
th(BCLK−DB)
40ns.max
4ns.min
Hi−Z
DBi
td(DB−WR)
tcyc=
(0.5 × tcyc−40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.17 Timing Diagram (5)
REJ09B0392-0064 Rev.0.64
Page 336 of 373
Oct 12, 2007
th(WR−DB)
(0.5 × tcyc−10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
40ns.max
4ns.min
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
ADi
/DBi
th(ALE-AD)
(0.5×tcyc-15)ns.min
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-60)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
50ns.min
td(AD-RD)
th(BCLK-AD)
0ns.min
td(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(RD-AD)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
Write timing
BCLK
tcyc
td(BCLK-CS)
th(BCLK-CS)
th(WR-CS)
(0.5×tcyc-10)ns.min
40ns.max
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-50)ns.min
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
40ns.max
td(AD-WR)
th(BCLK-ALE)
-4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
WR,WRL,
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.18 Timing Diagram (6)
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th(BCLK-WR)
0ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
30ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
4ns.min
30ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
30ns.max
0ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
30ns.max
RD
tac2(RD-DB)
(3.5 × tcyc-60)ns.max
DBi
Hi-Z
tsu(DB-RD)
th(RD-DB)
50ns.min
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-AD)
th(BCLK-AD)
4ns.min
30ns.max
CSi
4ns.min
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
0ns.min
30ns.max
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
(2.5 × tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.19 Timing Diagram (7)
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th(WR-DB)
(0.5 × tcyc-10)ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
40ns.max
4ns.min
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
ADi
/DBi
th(ALE-AD)
(0.5×tcyc-15)ns.min
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-60)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
50ns.min
td(AD-RD)
th(BCLK-AD)
0ns.min
td(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(RD-AD)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
Write timing
BCLK
tcyc
td(BCLK-CS)
th(BCLK-CS)
th(WR-CS)
(0.5×tcyc-10)ns.min
40ns.max
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-50)ns.min
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
40ns.max
td(AD-WR)
th(BCLK-ALE)
-4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
WR,WRL,
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.20 Timing Diagram (8)
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Oct 12, 2007
th(BCLK-WR)
0ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
23. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
6ns.min
40ns.max
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(ALE-AD)
(0.5×tcyc-15)ns.min
ADi
/DBi
Address
td(BCLK-AD)
40ns.max
ADi
BHE
(No multiplex)
Data input
th(RD-DB)
tdZ(RD-AD)
td(AD-RD)
tac3(RD-DB)
8ns.max
(2.5×tcyc-60)ns.max
0ns.min
td(BCLK-ALE)
40ns.max
tsu(DB-RD)
0ns.min
th(BCLK-AD)
50ns.min
4ns.min
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
40ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
40ns.max
th(BCLK-CS)
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5×tcyc-40)ns.min
td(DB-WR)
(2.5×tcyc-50)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
th(WR-AD)
-4ns.min
td(AD-WR)
(0.5×tcyc-10)ns.min
0ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
WR, WRL
WRH
tcyc=
40ns.max
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 23.21 Timing Diagram (9)
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Oct 12, 2007
0ns.min
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24. Precautions
24. Precautions
24.1
SFR
24.1.1
Register Settings
Table 24.1 lists Registers with Write-Only Bits. Set these registers with immediate values. When establishing a next value by altering the existing value, write the existing value to the RAM as well as to the
register. Transfer the next value to the register after making changes in the RAM.
Table 24.1
Registers with Write-Only Bits
Register
Symbol
Address
Watchdog timer reset register
WDTR
037Dh
Watchdog timer start register
WDTS
037Eh
Timer A1-1 register
TA11
0303h to 0302h
Timer A2-1 register
TA21
0305h to 0304h
Timer A4-1 register
TA41
0307h to 0306h
Dead time timer
DTT
030Ch
Timer B2 interrupt generation frequency set counter
ICTB2
030Dh
SI/O3 bit rate register
S3BRG
0273h
SI/O4 bit rate register
S4BRG
0277h
UART0 bit rate register
U0BRG
0249h
UART1 bit rate register
U1BRG
0259h
UART2 bit rate register
U2BRG
0269h
UART5 bit rate register
U5BRG
0289h
UART6 bit rate register
U6BRG
0299h
UART7 bit rate register
U7BRG
02A9h
UART0 transmit buffer register
U0TB
024Bh to 024Ah
UART1 transmit buffer register
U1TB
025Bh to 025Ah
UART2 transmit buffer register
U2TB
026Bh to 026Ah
UART5 transmit buffer register
U5TB
028Bh to 028Ah
UART6 transmit buffer register
U6TB
029Bh to 029Ah
UART7 transmit buffer register
U7TB
02ABh to 02AAh
Timer A0 register
TA0
0327h to 0326h
Timer A1 register
TA1
0329h to 0328h
Timer A2 register
TA2
032Bh to 032Ah
Timer A3 register
TA3
032Dh to 032Ch
Timer A4 register
TA4
032Fh to 032Eh
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.2
24. Precautions
Reset
24.2.1
VCC1
When supplying power to the microcomputer, the power supply voltage applied to the VCC1 pin must
meet the conditions of SVCC.
Symbol
SVCC
Parameter
Power supply rising gradient (VCC1) (Voltage range 0 to 2)
Standard
Min.
Typ. Max.
0.05
Unit
V / ms
Voltage
SVCC
Power supply rising
gradient (VCC1)
2V
SVCC
0V
Figure 24.1
24.2.2
Time
Timing of SVCC
CNVSS
To start to operate in single-chip mode after reset, connect to VSS via resistor. The internal pull-up of
the CNVSS pin is on immediately after hardware reset 1 or 2 is released in single-chip mode. Therefore, the CNVSS pin level becomes high for two cycles of fOCO-S maximum.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.3
24. Precautions
Bus
• When hardware reset 1 or brown-out reset is performed with “H” input on the CNVSS pin, contents of
internal ROM cannot be read.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.4
24. Precautions
PLL Frequency Synthesizer
To use the PLL frequency synthesizer, stabilize supply voltage so that the standard of the power supply
ripple is met.
Symbol
Parameter
f (ripple)
VP-P (ripple)
VCC (|ΔV /ΔT|)
Power supply ripple allowable frequency (VCC1)
Power supply ripple allowable
(VCC1 = 5V)
amplitude voltage
(VCC1 = 3V)
Power supply ripple rising / falling
(VCC1 = 5V)
gradient
(VCC1 = 3V)
f (ripple)
Power supply ripple allowable
frequency (VCC1)
Vp-p (ripple)
Power supply ripple allowable
amplitude voltage
Figure 24.2
Oct 12, 2007
Unit
kHz
V
V
V / ms
V / ms
f (ripple)
VCC1
Voltage Fluctuation Timing
REJ09B0392-0064 Rev.0.64
Page 344 of 373
Standard
Min.
Typ.
Max.
10
0.5
0.3
0.3
0.3
Vp-p (ripple)
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.5
24. Precautions
Power Control
• When exiting stop mode by hardware reset 1, set the RESET pin to “L” until a main clock oscillation is
stabilized.
• Set the MR0 bit in the TAiMR register (i = 0 to 4) to 0 (pulse is not output) to use the timer A to exit
stop mode.
• After the WAIT instruction, insert at least four NOP instructions. When entering wait mode, the
instruction queue reads ahead the instructions following WAIT, and depending on timing, some of
these may execute before the microcomputer enters wait mode.
Program example when entering wait mode is shown below.
Program Example:
FSET
I
;
WAIT
;Enter wait mode
NOP
;More than four NOP instructions
NOP
NOP
NOP
• When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which
sets the CM10 bit in the CM1 register to 1, and then insert at least four NOP instructions. When
entering stop mode, the instruction queue reads ahead the instructions following the instruction which
sets the CM10 bit to 1 (all clock stop), and some of these may execute before the microcomputer
enters stop mode or before the interrupt routine for returning from stop mode.
Program example when entering stop mode
Program Example:
FSET
BSET
JMP.B
I
0, CM1
L2
; Enter stop mode
; Insert a JMP.B instruction
L2:
NOP
NOP
NOP
NOP
; More than four NOP instructions
• The CLKOUT pin outputs high in stop mode. Therefore, when the CLKOUT pin changes state from
high to low and is immediately driven in stop mode, the low level width becomes short.
Stop mode
CLKOUT
• Wait until the main clock oscillation stabilizes, before switching the clock source for the CPU clock to
the main clock. Similarly, wait until the sub clock oscillates stably before switching the clock source
for the CPU clock to the sub clock.
• Do not stop the externally-generated clock when the externally-generated clock is input to the XIN pin
and the main clock is used as the clock source for the CPU clock.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24. Precautions
• Suggestions to reduce power consumption
Refer to the following descriptions when designing a system or programming.
Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active output ports. A pass current flows to input ports in high-impedance state. When
entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
A/D converter
When A/D conversion is not performed, set the ADSTBY bit in the ADCON1 register to 0 (A/D operation
stop). When A/D conversion is performed, start the A/D conversion at least 1 φAD cycle or longer after
setting the ADSTBY bit to 1 (A/D operation enabled).
D/A converter
When not performing D/A conversion, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output
inhibited) and the DAi register to 00h.
Stopping peripheral functions
Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions during wait mode.
Switching the oscillation-driving capacity
Set the driving capacity to “L” when oscillation is stable.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.6
24. Precautions
Protect
Set the PRC2 bit to 1 (write enabled) and then write to given SFR address, and the PRC2 bit will be
cleared to 0 (write protected). Change the registers protected by the PRC2 bit in the next instruction after
setting the PRC2 bit to 1. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to 1 and the next instruction.
REJ09B0392-0064 Rev.0.64
Page 347 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.7
24. Precautions
Interrupt
24.7.1
Reading address 00000h
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the
CPU reads interrupt information (interrupt number and interrupt request priority level) from the address
00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to 0.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is cleared to 0. This factors a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
24.7.2
SP Setting
Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is cleared to
0000h after reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP),
the program may go out of control.
Especially when using the NMI interrupt, set a value in the ISP at the beginning of the program. Only for
the first instruction after reset, all interrupts including the NMI interrupt are disabled.
24.7.3
NMI Interrupt
• The NMI interrupt cannot be disabled. If this interrupt is not used, set the PM24 bit in the PM2 register to 0 (port P8_5 function).
• Stop mode cannot be entered into while input on the NMI pin is low because the CM10 bit in the
CM1 register is fixed to 0.
• Do not enter wait mode while input on the NMI pin is low because the CPU clock remains active
even though the CPU stops, and therefore, the current consumption in the chip does not drop. In
this case, normal condition is restored by a subsequent interrupt generated.
• Set the low and high level durations of the input signal to the NMI pin to 2 CPU clock cycles + 300
ns or more.
REJ09B0392-0064 Rev.0.64
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Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.7.4
24. Precautions
Changing an Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed
interrupt may inadvertently be set to 1 (interrupt requested). To use an interrupt, change the interrupt
generate factor, and then be sure to clear the IR bit for that interrupt to 0 (interrupt not requested).
Changing the interrupt generate factor referred to here means any act of changing the source, polarity
or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of
any peripheral function involves changing the source, polarity or timing of an interrupt, be sure to clear
the IR bit for that interrupt to 0 (interrupt not requested) after making such changes. Refer to the
description of each peripheral function for details about the interrupts from peripheral functions.
Figure 24.3 shows the Procedure for Changing the Interrupt Generate Factor.
Change the interrupt source
Disable interrupts (2, 3)
Change the interrupt generate factor
(including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to 0 (interrupt not requested) (3)
Enable interrupts (2, 3)
Change is completed
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
NOTES :
1. The above settings must be executed individually. Do not execute two or more
settings simultaneously (using one instruction).
2. Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an
interrupt request before changing the interrupt generate factor. In this case, if the
maskable interrupts can all be disabled without causing a problem, use the I flag.
Otherwise, use the corresponding bits ILVL2 to ILVL0 for the interrupt whose interrupt
generate factor is to be changed.
3. Refer to 23.7.6 Rewrite the Interrupt Control Register for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 24.3
24.7.5
Procedure for Changing the Interrupt Generate Factor
INT Interrupt
• Either an “L” level of at least tw (INL) width or an “H” level of at least tw (INH) width is necessary for
the signal input to pins INT0 through INT7 regardless of the CPU operation clock.
• If the POL bit in registers INT0IC to INT7IC, bits IFSR7 to IFSR0 in the IFSR register, or bits
IFSR31 and IFSR30 in the IFSR3A register are changed, the IR bit may inadvertently set to 1
(interrupt requested). Be sure to clear the IR bit to 0 (interrupt not requested) after changing any of
those register bits.
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.7.6
24. Precautions
Rewriting the Interrupt Control Register
(a) The interrupt control register for any interrupt should be modified in places where no requests for
that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control
register.
(b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with
the instruction to be used.
• Changing any bit other than the IR bit
When interrupts corresponding to the register occur, the IR bit may not become 1 (interrupt
requested) and the interrupts may be ignored. If this causes any troubles, use any of the
following instructions to change registers.
Instruction: AND, OR, BCLR, or BSET.
• Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to 0 (interrupt not
requested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(c) When using the I flag to disable an interrupt, set the I flag while referring to the sample program
fragments shown below. (Refer to (b) for details about rewriting the interrupt control registers in the
sample program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to 1 (interrupt enabled) before the
interrupt control register is rewritten, owing to the effects of the internal bus and the instruction queue
buffer.
Example 1: Using the NOP instruction to keep the program waiting until the interrupt control register is
modified
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Set the TA0IC register to 00h.
NOP
;
NOP
FSET
I
; Enable interrupts.
The number of the NOP instructions is as follows.
PM20 = 1 (1 wait) : 2, PM20 = 0 (2 waits) : 3, when using the HOLD function : 4.
Example 2: Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Set the TA0IC register to 00h.
MOV.W
MEM, R0
; Dummy read.
FSET
I
; Enable interrupts.
Example 3: Using the POPC instruction to change the I flag
INT_SWITCH3:
PUSHC
FLG
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Set the TA0IC register to 00h.
POPC
FLG
; Enable interrupts.
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.7.7
24. Precautions
Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
REJ09B0392-0064 Rev.0.64
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Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24.8
24. Precautions
DMAC
24.8.1
Write to the DMAE Bit in the DMiCON Register (i = 0 to 3)
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to 1 (DMAi is in active state) again while it remains 1.
• A DMA request may occur simultaneously when the DMAE bit is being written.
Steps
(1) Write a 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1).
(2) Make sure that the DMAi is in initial state (2) in a program.
If the DMAi is not in initial state, repeat the above steps.
NOTE:
1. The DMAS bit remains unchanged even if a 1 is written. However, if a 0 is written to this bit, it is
set to 0 (DMA not requested). In order to prevent the DMAS bit from being modified to 0, 1
should be written to the DMAS bit when 1 is written to the DMAE bit. In this way the state of the
DMAS bit immediately before being written can be maintained.
2. Similarly, when writing to the DMAE bit with a read-modify-write instruction, 1 should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
3. Read the TCRi register to verify whether the DMAi is in initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in initial state.
(In the case a DMA request occurs after writing to the DMAE bit, the read value is a value written
to the TCRi register minus one.) If the read value is a value in the middle of transfer, the DMAi is
not in initial state.
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24.9
24. Precautions
Timers
24.9.1
24.9.1.1
Timer A
Timer A (Timer Mode)
The timer is stopped after reset. Set the mode, count source, counter value, and others using registers TAiMR, TAi, TACS0 to TACS2, and TAPOFS before setting the TAiS bit in the TABSR register to
1 (count starts) (i = 0 to 4).
Always make sure registers TAiMR, TACS0 to TACS2, and TAPOFS are modified while the TAiS bit
is 0 (count stops) regardless of whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, if the counter is read at the same time it is reloaded, the value FFFFh is read. Also, if
the counter is read before it starts counting after a value is set in the TAi register while not counting,
the set value is read.
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go
to high-impedance state.
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24.9.1.2
24. Precautions
Timer A (Event Counter Mode)
The timer is stopped after reset. Set the mode, count source, counter value, and others using the
TAiMR register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF
register and the TRGSR register, and TAPOS register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4).
Always make sure the TAiMR register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the
ONSF register, the TRGSR register, and TAPOFS register are modified while the TAiS bit is 0 (count
stops) regardless of whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register. However, while reloading, FFFFh can be read in underflow, and 0000h in overflow. When the
counter is read before it starts counting after a value is set in the TAi register while not counting, the
set value is read.
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (threephase output forcible cutoff by input on SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to
high-impedance state.
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24.9.1.3
24. Precautions
Timer A (One-Shot Timer Mode)
The timer is stopped after reset. Set the mode, count source, counter value, and others using the
TAiMR register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2 and the TAPOFS register before setting the TAiS bit in the TABSR
register to 1 (count starts) (i = 0 to 4).
Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR
register, registers TACS0 to TACS2, and the TAPOFS register are modified while the TAiS bit is 0
(count stops) regardless of whether after reset or not.
When setting the TAiS bit to 0 (count stops), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” when the POFSi bit in the TAPOFS register is 0; outputs “H” when 1.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to 1 (interrupt requested).
Output in one-shot timer mode synchronizes with a count source internally generated. When an
external trigger is selected, one-and-half-cycle delay of a count source as maximum occurs between
a trigger input to the TAiIN pin and output in one-shot timer mode.
The IR bit is set to 1 when timer operating mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operating mode from timer mode to one-shot timer mode.
• Change an operating mode from event counter mode to one-shot timer mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to 0 after the changes listed above are made.
When a trigger occurs while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a
second trigger between generating the previous trigger and operating longer than one cycle of a
timer count source.
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go
to high-impedance state.
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24.9.1.4
24. Precautions
Timer A (Pulse Width Modulation Mode)
The timer is stopped after reset. Set the mode, count source, counter value, and others using the
TAiMR register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register, registers TACS0 to TACS2, and the TAPOF register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4).
Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR
register, registers TACS0 to TACS2, and the TAPOFS register are modified while the TAiS bit is 0
(count stops) regardless of whether after reset or not.
The IR bit is set to 1 when setting a timer operating mode with any of the following procedures:
• Select PWM mode after reset.
• Change an operating mode from timer mode to PWM mode.
• Change an operating mode from event counter mode to PWM mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 by program after the changes listed above are
made.
When setting the TAiS register to 0 (count stops) during PWM pulse output, the following action
occurs.
When the POFSi bit in the TAPOFS register is 0:
• Stop counting.
• When the TAiOUT pin is output “H,” output level is set to “L” and the IR bit is set to 1.
• When the TAiOUT pin is output “L,” both output level and the IR bit remains unchanged.
When the POFSi bit in the TAPOFS register is 1:
• Stop counting.
• When the TAiOUT pin is output “L,” output level is set to “H” and the IR bit is set to 1.
• When the TAiOUT pin is output “H,” both output level and the IR bit remains unchanged.
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (threephase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go
to high-impedance state.
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24.9.2
24.9.2.1
24. Precautions
Timer B
Timer B (Timer Mode)
The timer is stopped after reset. Set the mode, count source, counter value, and others using registers TBiMR, TBi, and TBCS0 to TBCS3 before setting the TBiS bit in the TABSR or the TBSR register
to 1 (count starts) (i = 0 to 5).
Always make sure the TBiMR register and registers TBCS0 to TBCS3 are modified while the TBiS bit
is 0 (count stops) regardless of whether after reset or not.
A value of a counter while counting, can be read in the TBi register at any time. FFFFh is read while
reloading. If the counter is read before it starts counting after a value is set in the TBi register while
not counting, the set value is read.
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24.9.2.2
24. Precautions
Timer B (Event Counter Mode)
The timer is stopped after reset. Set the mode, count source, counter value, and others using the
TBiMR register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 1
(count starts) (i = 0 to 5).
Always make sure the TBiMR register is modified while the TBiS bit is 0 (count stops) regardless of
whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TBi register. However, if this register is read at the same time the counter is reloaded, the read value is always
FFFFh. If the TBi register is read after setting a value in it while not counting but before the counter
starts counting, the read value is the value set in the register.
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24.9.2.3
24. Precautions
Timer B (Pulse Period / Pulse Width Measurement Mode)
The timer is stopped after reset. Set the mode, count source, etc. using the TBiMR register before
setting the TBiS bit in the TABSR or the TBSR register to 1 (count starts) (i = 0 to 5).
Always make sure the TBiMR register and registers TBCS0 to TBCS3 are modified while the TBiS bit
is 0 (count stops) regardless of whether after reset or not. To clear the MR3 bit to 0 by writing to the
TBiMR register while the TBiS bit = 1 (count starts), be sure to write the same value as previously
written to bits TMOD0, TMOD1, MR0, MR1, TCK0, and TCK1 and a 0 to bit 4.
The IR bit in the TBiIC register goes to 1 (interrupt requested) when an effective edge of a measurement pulse is input or Timer Bi is overflowed (i = 0 to 5). The factor of interrupt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine.
If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse
input and a timer overflow occur at the same time, use another timer to count the number of times
Timer B has overflowed.
Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor.
When a count is started and the first effective edge is input, an indeterminate value is transferred to
the reload register. At this time, Timer Bi interrupt request is not generated.
A value of the counter is indeterminate after reset. If a count is started in this state, the MR3 bit may
be set to 1 and Timer Bi interrupt request may be generated after a count start before an effective
edge input. When a value is set to the TBi register while the TBiS bit is 0 (count stops), the same
value is written to the counter.
For pulse width measurement, pulse widths are successively measured. Use program to check
whether the measurement result is “H” level width or “L” level width.
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24. Precautions
24.10 Serial Interface
24.10.1 Clock Synchronous Serial I/O
24.10.1.1 Transmission / Reception
When the RTS function is used with an external clock, RTSi pin (i = 0 to 2, 5 to 7) outputs “L,” which
informs the transmitting side that the MCU is ready for a receive operation. The RTSi pin outputs “H”
when a receive operation starts. Therefore, a transmit timing and receive timing can be synchronized
by connecting the RTSi pin to the CTSi pin of the transmitting side. The RTS function is disabled
when an internal clock is selected.
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (threephase output forcible cutoff by input on SD pin enabled), the following pins go to high-impedance
state:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V, P7_4/TA2OUT/W, P7_5/TA2IN/ W, P8_0/
TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U
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24. Precautions
24.10.1.2 Transmission
If an external clock is selected, the following conditions must be met while the external clock is held
“H” when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is set to 0 (transmit data output at the
falling edge and receive data input at the rising edge of the serial clock), or while the external clock is
held “L” when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input
at the falling edge of the serial clock).
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
• If CTS function is selected, input on the CTSi pin = “L”
24.10.1.3 Reception
In clock synchronous serial I/O mode, the shift clock is generated by activating a transmitter. Set the
UARTi-associated registers for a transmit operation even if the MCU is used for receive operation
only. Dummy data is output from the TXDi pin (i = 0 to 2, 5 to 7) while receiving.
When an internal clock is selected, the shift clock is generated by setting the TE bit in the UiC1 register to 1 (transmission enabled) and placing dummy data in the UiTB register. When an external clock
is selected, set the TE bit to 1 (transmission enabled), place dummy data in the UiTB register, and
input an external clock to the CLKi pin to generate the shift clock.
If data is received consecutively, an overrun error occurs when the RI bit in the UiC1 register is set to
1 (data present in the UiRB register) and the next receive data is received in the UARTi receive register. And then, the OER bit in the UiRB register is set to 1 (overrun error occurred). At this time, the
UiRB register is undefined. If an overrun error occurs, the IR bit in the SiRIC register remains
unchanged.
To receive data consecutively, set dummy data in the low-order byte in the UiTB register per each
receive operation.
If an external clock is selected, the following conditions must be met while the external clock is held
“H” when the CKPOL bit is set to 0 (transmit data output at the falling edge and receive data input at
the rising edge of the serial clock), or while the external clock is held “L” when the CKPOL bit is set to
1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock).
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
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24. Precautions
24.10.2 UART (Clock Asynchronous Serial I/O) Mode
24.10.2.1 Transmission / Reception
When the RTS function is used with an external clock, RTSi pin (i = 0 to 2, 5 to 7) outputs “L,” which
informs the transmitting side that the MCU is ready for a receive operation. The RTSi pin outputs “H”
when a receive operation starts. Therefore, a transmit timing and receive timing can be synchronized
by connecting the RTSi pin to the CTSi pin of the transmitting side. The RTS function is disabled
when an internal clock is selected.
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (threephase output forcible cutoff by input on SD pin enabled), the following pins go to high-impedance
state:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V, P7_4/TA2OUT/W, P7_5/TA2IN/ W, P8_0/
TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/CTS5/RTS5/U
24.10.2.2 Transmission
If an external clock is selected, the following conditions must be met while the external clock is held
“H” when the CKPOL bit in the UiC0 register (i = 0 to 2, 5 to 7) is set to 0 (transmit data output at the
falling edge and receive data input at the rising edge of the serial clock), or while the external clock is
held “L” when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input
at the falling edge of the serial clock).
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
• If CTS function is selected, input on the CTSi pin = “L”
24.10.3 Special Mode 1 (I2C Mode)
When generating start, stop, and restart conditions, set the STSPSEL bit in the UiSMR4 register (i = 0
to 2, 5 to 7) to 0 and wait for more than half cycle of the transfer clock before setting each condition
generation bit (STAREQ, RSTAREQ, and STPREQ) from 0 to 1.
24.10.4 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2C1 register to 1
(transmission completed) and 1 (error signal output), respectively. Therefore, when using SIM mode,
make sure to clear the IR bit to 0 (interrupt not requested) after setting these bits.
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24. Precautions
24.10.5 SI/O3, SI/O4
The SOUTi default value which is set to the SOUTi pin by the SMi7 bit approximately 10 ns may be output when changing the SMi3 bit from 0 (I/O port) to 1 (SOUTi output and CLK function) while the SMi2
bit in the SiC to 0 (SOUTi output) and the SMi6 bit is set to 1 (internal clock). And then the SOUTi pin is
held high-impedance.
If the output level from the SOUTi pin is a problem when changing the SMi3 bit from 0 to 1, set the
default value of the SOUTi pin by the SMi7 bit.
i = 3, 4
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24. Precautions
24.11 A/D Converter
Set registers ADCON0 (except bit 6), ADCON1, and ADCON2 when A/D conversion is stopped (before a
trigger occurs). After A/D conversion is stopped, set the ADSTBY bit from 1 to 0.
When the ADSTBY bit in the ADCON1 register is changed from 0 (A/D operation stopped) to 1 (A/D operation enabled), wait for 1 φAD cycle or longer to start A/D conversion.
To prevent noise-induced device malfunction or latchup, as well as to minimize conversion errors, insert
capacitors between pins AVCC, VREF, analog input (ANi (i = 0 to 7), AN0_i, AN2_i), and AVSS. Similarly,
insert a capacitor between pins VCC1 and VSS. Figure 24.4 shows an example connection of individual
pin.
Make sure the port direction bits corresponding to the pins that are used as analog inputs are set to 0
(input mode).
When the TRG bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the
ADTRG pin is set to 0 (input mode).
When using key input interrupts, do not use any of the four pins AN4 to AN7 as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
When changing an A/D operating mode, set bits CH2 to CH0 in the ADCON0 register and bits SCAN1 to
SCAN0 in the ADCON1 register again to select analog input pins.
VCC1
C4
Microcomputer
VCC1
VCC1
AVCC
VSS
VREF
VCC1
C1
AVSS
VCC2
C5
C2
C3
VCC2
ANi
VSS
ANi: ANi, AN0_i, and AN2_i (i = 0 to 7)
NOTES :
1. C1≥0.47mF, C2≥0.47mF, C3≥100pF, C4≥0.1mF, C5≥0.1mF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
Figure 24.4
Use of Capacitors to Reduce Noise
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24. Precautions
When A/D conversion is forcibly terminated by setting the ADST bit in the AD0CON0 register to 0 (A/D
conversion stops) by program during A/D conversion, the A/D conversion result is undefined. The ADi
register not performing A/D conversion may also be undefined. If the ADST bit is set to 0 by program during A/D conversion, do not use values obtained from any ADi registers.
The applied intermediate potential may cause more increase in power consumption to AN4 to AN7 than to
other analog input pins (AN0 to AN3, AN0_0 to AN0_7, and AN2_0 to AN2_7) since AN4 to AN7 are used
with KI0 to KI3.
When A/D conversion is stopped in one-shot mode or single sweep mode, the ADST bit in the ADCON0
register becomes 0 (A/D conversion stop). Also, when a trigger by ADTRG is selected, the ADST bit
becomes 0. Therefore, set the ADST bit to 1 (A/D conversion start) by a program if there is a possibility
that a trigger is input subsequently.
Connect the VREF pin to VCC1 pin. Because the VREF pin is connected to VCC1 pin inside, current
flows if potential difference occurs between the pins.
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24. Precautions
24.12 Programmable I/O Ports
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on the SD pin enabled), pins P7_2 to P7_5 and P8_0 and P8_1 go to highimpedance state.
Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to high-impedance state.
Similarly, setting the SM42 bit in the S4C register to 1 causes the P9_6 pin to go to high-impedance state.
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24. Precautions
24.13 Flash Memory Version
24.13.1 Functions to Inhibit Rewriting Flash Memory
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and
0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in
standard serial I/O mode.
The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses
(H) of fixed vectors.
24.13.2 Stop Mode
When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit in the CM1
register to 1 (stop mode) after setting the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and disabling the DMA transfer.
24.13.3 Wait Mode
When shifting to wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the
WAIT instruction.
24.13.4 Low Power Consumption Mode, On-Chip Oscillator Low Power Consumption Mode
If the CM05 bit in the CM0 register is set to 1 (main clock stop), do not execute the following commands.
• Program
• Block erase
• Lock bit program
24.13.5 Writing Command and Data
Write the command code and data at even addresses.
24.13.6 Program Command
Write xx41h in the first bus cycle and write data to the write address in the second bus cycle, and an
auto program operation (data program and verify) will start. Make sure the address value specified in
the first bus cycle is the same even address as the write address specified in the second bus cycle.
24.13.7 Lock Bit Program Command
Write xx77h in the first bus cycle and write xxD0h in the second bus cycle to the highest-order even
address of a block, and the lock bit for the specified block is cleared to 0. Make sure then address value
specified in the first bus cycle is the same highest-order block address that is specified in the second
bus cycle.
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24. Precautions
24.13.8 Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to 0
(main clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and bits
CM17 and CM16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state).
24.13.9 Instructions Inhibited against Use
The following instructions cannot be used in EW0 mode because the flash memory internal data is
referred: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
24.13.10 Interrupts
EW0 Mode
• Any interrupt which has a vector in the relocatable vector table can be used providing that its vector
is transferred into the RAM area.
• The NMI and watchdog timer (oscillation stop, re-oscillation detect, and low voltage detect) interrupts can be used because registers FMR0 and FMR1 are initialized when one of those interrupts
occurs. The jump addresses for those interrupt routines should be set in the fixed vector table.
• Because the rewrite operation stops when an NMI or watchdog timer (oscillation stop, re-oscillation
detect, and low voltage detect) interrupt occurs, the rewrite program must be executed again after
exiting the interrupt routine.
• The address match interrupt cannot be used because the flash memory internal data is referred.
EW1 Mode
• Make sure that any interrupt which has a vector in the relocatable vector table or address match
interrupt will not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer (oscillation stop, re-oscillation detect, and low voltage detect) interrupts.
• The NMI interrupt can be used because registers FMR0 and FMR1 are initialized when this interrupt occurs. The jump address for the interrupt routine should be set in the fixed vector table.
• Because the rewrite operation is halted when an NMI interrupt occurs, execute the rewrite program
again after exiting the interrupt routine.
24.13.11 How to Access
To set the FMR01, FMR02, or FMR11 bit to 1, write 0 and then 1 in succession. Ensure that no interrupts or DMA transfers will occur before writing 1 after writing 0. Perform it when the NMI pin is “H” level
if the PM24 bit is 1 (NMI).
24.13.12 Writing in the User ROM Area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, the rewrite control program may not be correctly rewritten and, consequently, the flash
memory becomes unable to be rewritten thereafter. In this case, use standard serial I/O or parallel
I/O mode.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
24.13.13 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register =
0 (during the auto program or auto erase period).
REJ09B0392-0064 Rev.0.64
Page 368 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24. Precautions
24.13.14 Programming / Erasing Endurance and Execution Time
As the number of programming / erasing times increases, so does the execution time for software commands (program, block erase, and lock bit program commands).
The software commands are stopped by hardware reset 1, brown-out reset, NMI interrupt, and watchdog timer (oscillation stop, re-oscillation detect, and low voltage detect) interrupt. If a software command is stopped by such reset or interrupt, erase the block in process before reexecuting the stopped
command.
REJ09B0392-0064 Rev.0.64
Page 369 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
24. Precautions
24.14 Noise
Connect a bypass capacitor (approximately 0.1 µF) across pins VCC1 and VSS, and pins VCC2 and VSS
using the shortest and thicker possible wiring. Figure 24.5 shows the Bypass Capacitor Connection.
Bypass Capacitor
Connecting Pattern
Connecting Pattern
VCC2
VSS
M16C / 64 Group
VSS
VCC1
Connecting Pattern
Connecting Pattern
Bypass Capacitor
Figure 24.5
Bypass Capacitor Connection
REJ09B0392-0064 Rev.0.64
Page 370 of 373
Oct 12, 2007
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JD-B
Previous Code
100P6F-A
MASS[Typ.]
1.8g
Under development
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
30
Index mark
c
F
A1
A
ZD
A2
1
L
*3
e
y
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
bp
x
Detail F
Previous Code
100P6Q-A / FP-100U / FP-100UV
D
E
A2
HD
HE
A
A1
bp
c
e
x
y
ZD
ZE
L
Dimension in Millimeters
Min Nom Max
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.25 0.3 0.4
0.13 0.15 0.2
10°
0°
0.65
0.13
0.10
0.575
0.825
0.4 0.6 0.8
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
26
1
ZE
Terminal cross section
100
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
REJ09B0392-0064 Rev.0.64
Page 371 of 373
Oct 12, 2007
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Register Index
REGISTER INDEX
I
A
ICTB2 ..................................................... 169
IDB0, IDB1 ............................................. 169
IFSR ....................................................... 113
IFSR2A, IFSR3A .................................... 114
INT0IC to INT7IC ................................... 106
INVC0 ..................................................... 167
INVC1 ..................................................... 168
AD0 to AD7 ............................................ 233
ADCON0, ADCON1 ......................................
........................ 232, 235, 237, 239, 241, 243
ADCON2 ................................................ 233
ADIC .............................................. 105, 106
AIER ....................................................... 117
AIER2 ..................................................... 117
K
B
KUPIC .................................................... 105
BCNIC ............................................ 105, 106
O
C
OFS1 .............................................. 120, 269
ONSF ..................................................... 140
CM0 ......................................................... 76
CM1 ......................................................... 77
CM2 ......................................................... 78
CPSRF ........................................... 141, 156
CRCD ..................................................... 248
CRCIN .................................................... 248
CSE .......................................................... 62
CSPR ..................................................... 120
CSR ......................................................... 55
D
D4INT ....................................................... 39
DA0, DA1 ............................................... 247
DACON .................................................. 247
DAR0 to DAR3 ....................................... 128
DBR ......................................................... 67
DM0CON to DM3CON ........................... 127
DM0IC .................................................... 106
DM0IC to DM3IC .................................... 105
DM0SL to DM3SL .................................. 125
DTT ........................................................ 169
F
FMR0 ..................................................... 272
FMR1 ..................................................... 273
FMR6 ..................................................... 275
REJ09B0392-0064 Rev.0.64
Page 372 of 373
Oct 12, 2007
P
P0 to P10 ............................................... 257
PCLKR ..................................................... 79
PCR ................................................ 114, 259
PD0 to PD10 .......................................... 256
PLC0 ........................................................ 80
PM0 .......................................................... 48
PM1 .......................................................... 49
PM2 .......................................................... 79
PRCR ....................................................... 98
PRG2C ..................................................... 50
PUR0, PUR1 .......................................... 258
PUR2 ...................................................... 259
R
RMAD0 to RMAD3 ................................. 117
RSTFR ..................................................... 46
S
S0RIC to S2RIC, S5RIC to S7RIC ......... 105
S0TIC to S2TIC, S5TIC to S7TIC .......... 105
S34C2 .................................................... 225
S3BRG, S4BRG ..................................... 224
S3C, S4C ............................................... 224
S3IC, S4IC ............................................. 106
S3TRR, S4TRR ...................................... 224
SAR0 to SAR3 ....................................... 128
Under development
Preliminary Specification
Specification in this preliminary version is subject to change.
M16C/64 Group
Register Index
T
U
TA0 to TA4 ............................................. 138
TA0IC to TA4IC ...................................... 105
TA0MR to TA4MR .. 138, 143, 145, 150, 152
TA1, TA2 ................................................ 170
TA11 ....................................................... 170
TA1MR, TA2MR ..................................... 172
TA21 ....................................................... 170
TA2MR to TA4MR .................................. 147
TA4 ......................................................... 170
TA41 ....................................................... 170
TA4MR ................................................... 172
TABSR ................................... 139, 156, 171
TACS0, TACS1 ...................................... 141
TACS2 .................................................... 142
TAPOFS ................................................. 142
TB0 to TB5 ............................................. 155
TB0IC to TB5IC ...................................... 105
TB0MR to TB5MR .......... 155, 159, 161, 163
TB2 ........................................................ 171
TB2MR ................................................... 172
TB2SC ................................................... 170
TBCS0 to TBCS3 ................................... 157
TBSR ..................................................... 156
TCR0 to TCR3 ....................................... 128
TRGSR .......................................... 140, 171
U0BCNIC, U1BCNIC, U5BCNIC to U7BCNIC
................................................................ 105
U0BRG to U2BRG ................................. 180
U0C0 to U2C0 ........................................ 181
U0C1 to U2C1 ........................................ 182
U0MR to U2MR ...................................... 180
U0RB to U2RB ....................................... 179
U0SMR to U2SMR ................................. 183
U0SMR2 to U2SMR2 ............................. 184
U0SMR3 to U2SMR3 ............................. 184
U0SMR4 to U2SMR4 ............................. 185
U0TB to U2TB ........................................ 179
U1BCNIC ............................................... 106
U5BCNICÅ`U7BCNIC ............................ 106
U5BRG to U7BRG ................................. 180
U5C0 to U7C0 ........................................ 181
U5C1 to U7C1 ........................................ 182
U5MR to U7MR ...................................... 180
U5RB to U7RB ....................................... 179
U5SMR to U7SMR ................................. 183
U5SMR2 to U7SMR2 ............................. 184
U5SMR3 to U7SMR3 ............................. 184
U5SMR4 to U7SMR4 ............................. 185
U5TB to U7TB ........................................ 179
UCON ..................................................... 183
UDF ........................................................ 139
V
VCR1 ........................................................ 38
VCR2 ........................................................ 38
VW0C ....................................................... 40
W
WDTS ..................................................... 119
REJ09B0392-0064 Rev.0.64
Page 373 of 373
Oct 12, 2007
Revision History
Rev.
Date
0.51
0.61
Jun 06, 2007
Jun 22, 2007
0.62
Jul 04, 2007
Page
3
4
17
32
51
75
163
186
220
224
256
260
267
264
287
265
290
267
268
319
320
321
322
0.63
Sep 21, 2007
343
362
3
5
29
79
92
114
234
238
259
263
M16C/64 Group Hardware Manual
Description
Summary
First Edition issued.
Table 1.2 Specifications (2) is partly revised.
Table 1.3 Product List is partly revised.
3. Memory (including the figure) is partly revised.
Figure 5.1 Example Reset Circuit is partly revised.
7.3 Internal Memory is partly revised.
Figure 10.1 System Clock Generation Circuit is partly revised.
Figure 15.24 TBiMR Register in Pulse Period and Pulse Width
Measurement Mode is partly revised.
Table 17.1 Clock Synchronous Serial I/O Mode Specifications is partly
revised.
Figure 17.33 Transmit and Receive Timing in SIM Mode is partly
revised.
Figure 17.38 Registers S3C, S4C, S3BRG, S4BRG, S3TRR, and
S4TRR is partly revised.
Table 19.2 One-Shot Mode Specifications is partly revised.
Table 19.4 Single Sweep Mode Specifications is partly revised.
Figure 19.9 Analog Input Pin and External Sensor Equivalent Circuit is
22.1 Memory Map is partly revised.
23.1.1 Boot Mode is partly revised.
22.1.2 User Boot Function is added.
23.2.4 Standard Serial I/O Mode Disable Function is added.
22.2.2 ID Code Check Function is added.
22.2.3 Forced Erase Function is added.
Figure 23.20 Pin Connections for Standard Serial I/O Mode (1) is partly
revised.
Figure 23.21 Pin Connections for Standard Serial I/O Mode (2) is partly
revised.
Figure 23.22 Circuit Application in Standard Serial I/O Mode 1 is partly
revised.
Figure 23.23 Circuit Application in Standard Serial I/O Mode 2 is partly
revised.
24.5 Power Control is partly revised.
24.11 A/D Converter is partly revised.
Table 1.2 Specifications (2) is partly revised.
Figure 1.2 Marking Diagram of Flash Memory Version (Top View) is
partly revised.
Table 4.12 SFR Information (12) is partly revised.
Figure 10.5 PM2 Register is partly revised.
Table 10.7 Pin Status in Stop Mode is partly revised.
Figure 12.12 Registers IFSR2A, IFSR3A, and PCR is partly revised.
Table 18.2 One-Shot Mode Specifications is partly revised.
Table 18.4 Single Sweep Mode Specifications is partly revised.
Figure 21.11 PCR Register is partly revised.
Table 22.1 Flash Memory Version Specifications is partly revised.
A- 1
Revision History
Rev.
Date
0.64
Oct 12, 2007
Page
263
268
268
272
274
303
304
3
11
13
32
92
230
231
233
234
235
236
237
238
239
240
241
242
243
260
261
262
295
301
302
303
307
342
342
364
365
M16C/64 Group Hardware Manual
Description
Summary
Table 22.2 Flash Memory Rewrite Modes Overview is partly revised.
22.1.3 Standard Serial I/O Mode Disable Function is moved to 22.2.4.
Table 22.8 Forced Erase Function is partly revised
Figure 22.5 FMR0 Register is partly revised.
Figure 22.7 FMR2 Register is partly revised.
Figure 23.3 A/D Conversion Characteristics is partly revised.
Table 23.5 Flash Memory Version Electrical Characteristics is partly
revised.
Table 1.2 Specifications (2) is partly revised.
Table 1.6 Pin Functions (1) is partly revised.
Table 1.8 Pin Functions (3) is parly revised.
Figure 5.1 Example Reset Circuit is partly revised.
10.4.3 Stop Mode is partly revised.
Table 18.1 A/D Converter Specifications is partly revised.
Figure 18.1 A/D Converter Block Diagram is partly revised.
Figure 18.3 Registers ADCON2 and AD0 to AD7 is partly revised.
Table 18.2 One-Shot Mode Specifications is partly revised.
Figure 18.4 Registers ADCON0 and ADCON1 (One-shot Mode) is
partly revised.
Table 18.3 Repeat Mode Specifications is partly revised.
Figure 18.5 Registers ADCON0 and ADCON1 (Repeat Mode) is partly
revised.
Table 18.4 Single Sweep Mode Specifications is partly revised.
Figure 18.6 Registers ADCON0 and ADCON1 (Single Sweep Mode) is
partly revised.
Table 18.5 Repeat Sweep Mode 0 Specifications is partly revised.
Figure 18.7 Registers ADCON0 and ADCON1 (Repeat Sweep Mode 0)
is partly revised.
Table 18.6 Repeat Sweep Mode 1 Specifications is partly revised.
Figure 18.8 Registers ADCON0 and ADCON1 (Repeat Sweep Mode 1)
is partly revised.
Table 21.1 Unassigned Pin Handling in Single-chip Mode is partly
revised.
Table 21.2 Unassigned Pin Handling in Memory Expansion Mode and
Microprocessor Mode is partly revised.
Figure 21.12 Unassigned Pin Handling is partly revised.
Table 22.13 Pin Functions (Flash Memory Standard Serial I/O Mode) is
partly revised.
Table 23.1 Absolute Maximum Ratings is partly revised.
Table 23.2 Recommended Operating Conditions is partly revised.
Table 23.3 A/D Conversion Characteristics is partly revised.
Table 23.9 Electrical Characteristics (1) is partly revised.
24.2.1 VCC1 is added.
24.2.2 CNVSS is added.
Figure 24.4 Use of Capacitors to Reduce Noise is partly revised.
24.11 A/D Converter is partly revised.
A- 2
M16C/64 Group Hardware Manual
Publication Date: Feb 28, 2007
Oct 12, 2007
Published by:
Rev.0.20
Rev.0.64
Sales Strategic Planning Div.
Renesas Technology Corp.
2-6-2, Otemachi, Chiyoda-ku, Tokyo 100-0004
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
M16C/64 GROUP
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan