MM74HC02 Quad 2-Input NOR Gate Features General Description • Typical Propagation Delay: 8 ns • Wide Power Supply Range: 2 V to 6 V • Low Quiescent Supply Current: 20 μA Maximum (74HC Series) The MM74HC02 NOR gates utilize advanced silicongate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. • Moisture Level Sensitivity 1 • Low Input Current: 1 μA Maximum • High Output Current: 4 mA Minimum Ordering Information Part Number Top Mark Package Packing Method MM74HC02M MM74HC02M SOIC 14L Rail MM74HC02MX MM74HC02M SOIC 14L Tape and Reel MM74HC02MTC HC02 TSSOP 14L Rail MM74HC02MTCX HC02 TSSOP 14L Tape and Reel All packages are lead free per JEDEC: J-STD-020B standard. Connection Diagram Logic Diagram Pin Assignment for SOIC, TSSOP Top View © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com MM74HC02 — Quad 2-Input NOR Gate March 2015 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Unit VCC Supply Voltage -0.5 to +7.0 V VIN DC Input Voltage -1.5 to VCC+1.5 V DC Output Voltage -0.5 to VCC+0.5 V VOUT IIK, IOK Clamp Diode Current ±20 mA IOUT DC Output Current, per pin ±25 mA ICC DC VCC or GND Current, per pin ±50 mA -65 to +150 °C TSTG Storage Temperature Range PD Power Dissipation TL Lead Temperature (Soldering 10 seconds) (2) 600 S.O. Package only 500 mW 260 °C Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power dissipation temperature derating - plastic “N” package: -12 mW/°C from 65°C to 85°C. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN, VOUT TA tr, tf Min. Max. Unit Supply Voltage Parameter 2 6 V DC Input or Output Voltage 0 VCC V 85 °C Operating Temperature Range Input Rise or Fall Times © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 -40 VCC = 2.0 V 1000 VCC = 4.5 V 500 VCC = 6.0 V 400 ns www.fairchildsemi.com 2 MM74HC02 — Quad 2-Input NOR Gate Absolute Maximum Ratings(1) Symbol Parameter VCC (V) Conditions TA = 25°C Typ. VIH VIL Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage 2.0 1.50 1.50 1.50 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20 2.0 0.50 0.50 0.50 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80 2.0 1.9 1.9 1.9 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 2.0 4.5 VOH Minimum HIGH Level Output Voltage 6.0 |IOUT| ≤ 20 μA VIN = VIL, |IOUT| ≤ 4.0 mA 4.20 3.98 3.84 3.70 6.0 VIN = VIL, |IOUT| ≤ 5.2 mA 5.70 5.48 5.34 5.20 4.5 Minimum LOW Level Output Voltage VIN = VIL, 4.5 2.0 VOL TA =-40 TA =-55 to 85°C to 125°C Unit Guaranteed Limits 6.0 VIN = VIH or VIL, |IOUT| ≤ 20 μA 0 0.1 0.1 0.1 0 0.1 0.1 0.1 0 0.1 0.1 0.1 4.5 VIN = VIH or VIL, |IOUT| ≤ 4.0 mA 0.20 0.26 0.33 0.40 6.0 VIN = VIH or VIL, |IOUT| ≤ 5.2 mA 0.20 0.26 0.33 0.40 V V V V IIN Maximum Input Current 6.0 VIN = VCC or GND ±0.1 ±0.1 ±0.1 μA ICC Maximum Quiescent Supply Current 6.0 VIN = VCC or GND IOUT = 0 μA 2.0 20 40 μA Note: 3. For a power supply of 5 V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5 V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5 V and 4.5 V respectively. (The VIH value at 5.5 V is 3.85 V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0 V values should be used. © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com 3 MM74HC02 — Quad 2-Input NOR Gate DC Electrical Characteristics(3) VCC = 5 V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter Conditions tPHL, tPLH Maximum Propagation Delay Typ. Guaranteed Limit Unit 8 15 ns AC Electrical Characteristics VCC = 2.0 V to 6.0 V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter VCC (V) Conditions TA = 25°C Typ. tPHL, tPLH Maximum Propagation Delay tTLH, tTHL Maximum Output Rise and Fall Time CPD CIN Power Dissipation Capacitance(4) TA =-40 TA =-55 to 85°C to 125°C Unit Guaranteed Limits 2.0 45 90 113 134 4.5 9 18 23 27 6.0 8 15 19 23 2.0 30 75 95 110 4.5 8 15 19 22 6.0 7 13 16 19 (per gate) 20 Maximum Input Capacitance 5 ns ns pF 10 10 10 pF Note: 4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com 4 MM74HC02 — Quad 2-Input NOR Gate AC Electrical Characteristics MM74HC02 — Quad 2-Input NOR Gate Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION M C B A (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-LEAD, SOIC, JEDEC MS-012, 0.150 INCH, NARROW BODY © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com 5 0.65 5.00±0.10 0.43TYP A 14 8 B 6.4 4.40±0.10 6.10 3.2 1 PIN#1 IDENT 0.2 C B A 7 TOP VIEW 1.65 ALL LEAD TIPS 0.45 RECOMMENDED LAND PATTERN SEE DETAIL A 1.2 MAX 0.90+0.15 -0.10 0.20 0.09 0.10±0.05 0.30 0.19 ALL LEAD TIPS 0.1 C 0.13 0.65 A B C C 12.00° TOP & BOTTOM FRONT VIEW 0.09 MIN NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS. 0°- 8° C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 2009. E. LANDPATTERN STANDARD: SOP65P640X110-14M. F. DRAWING FILE NAME: MKT-MTC14rev7. GAGE PLANE 0.09 MIN 0.6±0.1 1.00 0.25 SEATING PLANE DETAIL A Figure 2. 14-LEAD, TSSOP, JEDEC MO-153, 4.4 MM WIDE © 1983 Fairchild Semiconductor Corporation MM74HC02 Rev. 1.4 www.fairchildsemi.com 6 MM74HC02 — Quad 2-Input NOR Gate Physical Dimensions (Continued) TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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