74AUP1G97 TinyLogic® Low Power Universal Configurable Two-Input Logic Gate Features Description 0.8V to 3.6V VCC Supply Operation High Speed tPD - 3.1ns: Typical at 3.3V Power-Off High-Impedance Inputs and Outputs The 74AUP1G97 is a universal configurable 2-input logic gate that provides a high performance and low power solution ideal for battery-powered portable applications. This product is designed for a wide low voltage operating range (0.8V to 3.6V) and guarantees very low static and dynamic power consumption across the entire voltage range. All inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. Low Dynamic Power Consumption - CPD=2.5pF Typical at 3.3V Ultra-Small MicroPak™ Packages 3.6V Over-Voltage Tolerant I/Os at VCC from 0.8V to 3.6V Low Static Power Consumption - ICC=0.9µA Maximum The 74AUP1G97 provides for multiple functions as determined by various configurations of the three inputs. The potential logic functions provided are MUX, AND, OR, NAND, and NOR, inverter and buffer. Refer to Figures 3 to 9. Ordering Information Part Number Top Mark Package Packing Method 74AUP1G97L6X AD 6-Lead MicroPak™, 1.0mm Wide 5000 Units on Tape & Reel 74AUP1G97FHX AD 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 www.fairchildsemi.com 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate October 2010 A 3 4 B C 1 6 Figure 1. Logic Diagram (Positive Logic) Pin Configurations B 1 6 C GND 2 5 VCC A 3 4 Y Figure 2. MicroPak™ (Top Through View) Pin Definitions Pin # Name 1 B 2 GND 3 A Data Input 4 Y Output 5 VCC 6 C © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 Description Data Input Ground Supply Voltage Data Input Y 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate Logic Diagram www.fairchildsemi.com 2 Inputs 74AUP1G97 C B A Y=Output L L L L L L H L L H L H L H H H H L L L H L H H H H L L H H H H H = HIGH Logic Level L = LOW Logic Level Function Selection Table 2-Input Logic Function Connection Configuration 2-to-1 MUX Figure 3 2-Input AND Gate Figure 4 2-Input OR Gate with One Inverted Input Figure 5 2-Input NAND Gate with One Inverted Input Figure 5 2-Input AND Gate with One Inverted Input Figure 6 2-Input NOR Gate with One Inverted Input Figure 6 2-Input OR Gate Figure 7 Inverter Figure 8 Buffer Figure 9 © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate Function Table www.fairchildsemi.com 3 implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure 3 through Figure 9 show the logical functions that can be implemented using the 74AUP1G97. The diagrams show the DeMorgan’s equivalent logic duals for a given two-input function. The logical VCC VCC C B B Y A A 1 6 2 5 3 4 C C Y Y A A GND Note: 1. When C is L, Y=B. 2. When C is H, Y=A. 1 6 2 5 3 4 C Y GND Figure 3. 2-to-1 MUX Figure 4. 2-Input AND Gate VCC VCC C C A C A Y B Y B Y A 1 6 2 5 3 4 C C Y B Y GND 1 6 2 5 3 4 C Y GND Figure 5. Input OR Gate with One Inverted Input Figure 6. 2-Input AND Gate with One Inverted Input 2-Input NAND Gate with One Inverted Input 2-Input NOR Gate with One Inverted Input VCC VCC C B Y B 1 6 2 5 3 4 C C Y Y GND 1 6 2 5 3 4 C Y 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate 74AUP1G97 Logic Configurations GND Figure 8. Figure 7. 2-Input OR Gate Inverter VCC B B Y 1 6 2 5 3 4 Y GND Figure 9. © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 Buffer www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VOUT IIK IOK IOH / IOL IO ICC or IGND TSTG HIGH or LOW State DC Output Voltage (3) VCC=0V DC Input Diode Current DC Output Diode Current Min. Max. Unit -0.5 4.6 V -0.5 4.6 V -0.5 VCC + 0.5 -0.5 4.6 VIN < 0V -50 VOUT < 0V -50 VOUT > VCC +50 V mA mA DC Output Source / Sink Current ±50 mA Continuous Output Current ±20 mA DC VCC or Ground Current per Supply Pin ±50 mA +150 °C TJ Junction Temperature Under Bias +150 °C TL Junction Lead Temperature, Soldering 10s +260 °C PD ESD Storage Temperature Range Power Dissipation at +85°C -65 MicroPak-6 130 MicroPak2-6 120 Human Body Model, JEDEC:JESD22-A114 5000+ Charged Device Model, JEDEC:JESD22-C101 1500 mW V Note: 3. IO absolute maximum rating must be observed. Recommended Operating Conditions(4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT IOH/IOL Output Voltage Output Current TA Operating Temperature, Free Air θJA Thermal Resistance Conditions Min. Max. Unit 0.8 3.6 V 0 3.6 V VCC=0V 0 3.6 HIGH or LOW State 0 VCC V VCC=3.0V to 3.6V ±4.0 VCC=2.3V to 2.7V ±3.1 VCC=1.65V to 1.95V ±1.9 VCC=1.4V to 1.6V ±1.7 VCC=1.1V to 1.3V ±1.1 VCC=0.8V ±20.0 µA +85 °C -40 MicroPak-6 500 MicroPak2-6 560 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate Absolute Maximum Ratings mA °C/W Note: 4. Unused inputs must be held HIGH or LOW. They may not float. © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 www.fairchildsemi.com 5 Symbol Parameter VCC Conditions 0.80 VP VN VH Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage ΔIOFF ICC ΔICC Min. Max. 0.30 0.60 0.30 0.60 0.53 0.90 0.53 0.90 1.11 0.74 1.11 1.65 0.91 1.29 0.91 1.29 2.30 1.37 1.77 1.37 1.77 3.00 1.88 2.29 1.88 2.29 0.80 0.10 0.60 0.10 0.60 1.10 0.26 0.65 0.26 0.65 1.40 0.39 0.75 0.39 0.75 1.65 0.47 0.84 0.47 0.84 2.30 0.69 1.04 0.69 1.04 3.00 0.88 1.24 0.88 1.24 0.80 0.07 0.50 0.07 0.50 1.10 0.08 0.46 0.08 0.46 1.40 0.18 0.56 0.18 0.56 1.65 0.27 0.66 0.27 0.66 2.30 0.53 0.92 0.53 0.92 0.79 1.31 0.79 1.31 0.80 ≤ VCC ≤ 3.60 IOH=-20µA VCC-0.1 VCC-0.1 1.10 ≤ VCC ≤ 1.30 IOH=-1.1mA 0.75 x VCC 0.70 x VCC 1.40 ≤ VCC ≤ 1.60 IOH=-1.7mA 1.11 1.03 HIGH Level Output 1.65 ≤ VCC ≤ 1.95 IOH=-1.9mA Voltage IOH=-2.3mA 2.30 ≤ VCC ≤ 2.70 IOH=-3.1mA 1.32 1.30 2.05 1.97 1.90 1.85 IOH=-2.7mA 2.72 2.67 IOH=-4.0mA 2.60 2.55 LOW Level Output Voltage Units V V V V 0.80 ≤ VCC ≤ 3.60 IOL=20µA 0.10 0.10 1.10 ≤ VCC ≤ 1.30 IOL=1.1mA 0.30 x VCC 0.30 x VCC 1.40 ≤ VCC ≤ 1.60 IOL=1.7mA 0.31 0.37 1.65 ≤ VCC ≤ 1.95 IOL=1.9mA 0.31 0.35 IOL=2.3mA 0.31 0.33 IOL=3.1mA 0.44 0.45 IOL=2.7mA 0.31 0.33 IOL=4.0mA 0.44 0.45 0 ≤ VIN ≤ 3.6 ±0.1 ±0.5 µA 0 ≤ (VIN,VO)≤ 3.6 0.2 0.6 µA VIN or VO = 0V to 3.6V 0.2 0.6 µA VIN - VCC or GND 0.5 0.9 2.70 ≤ VCC ≤ 3.60 IOFF Max. 0.74 2.30 ≤ VCC ≤ 2.70 IIN Min. 1.40 3.00 ≤ VCC ≤ 3.60 VOL TA=-40 to +85°C 1.10 3.00 VOH TA=+25°C Input Leakage Current Power Off Leakage Current Additional Power Off Leakage Current 0V to 3.6V 0V 0V to 0.2V Quiescent Supply Current 0.8V to 3.6V Increase in ICC per Input 3.3V © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 VCC ≤ VIN ≤ 3.6 VIN = VCC -0.6V V 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate DC Electrical Characteristics µA ±0.9 40.0 50.0 µA www.fairchildsemi.com 6 Symbol Parameter VCC Conditions Min. 1.65 ≤ VCC ≤ 1.95 tPHL, tPLH Max Min Max CL=5pF, RL=1MΩ 2.8 8.6 12.6 2.5 13.0 2.3 5.2 7.6 2.5 8.2 2.1 4.3 6.2 2.0 6.8 2.30 ≤ VCC ≤ 2.70 1.9 3.3 4.8 1.7 5.3 3.00 ≤ VCC ≤ 3.60 1.6 3.1 3.9 1.5 4.1 0.80 Propagation Delay Typ. Units 29.4 1.10 ≤ VCC ≤ 1.30 3.2 9.4 14.3 2.9 14.9 1.40 ≤ VCC ≤ 1.60 CL=10pF, 1.65 ≤ VCC ≤ 1.95 RL=1MΩ 2.6 6.3 8.7 2.8 9.4 2.2 4.9 7.0 2.1 7.8 2.30 ≤ VCC ≤ 2.70 2.0 4.2 5.2 2.1 5.9 3.00 ≤ VCC ≤ 3.60 1.9 3.6 4.6 1.7 4.9 0.80 ns 31.3 1.10 ≤ VCC ≤ 1.30 3.6 9.6 16.0 3.2 16.7 1.40 ≤ VCC ≤ 1.60 CL=15pF, 1.65 ≤ VCC ≤ 1.95 RL=1MΩ 2.9 6.3 9.6 3.1 10.4 2.4 5.4 7.8 2.3 8.7 2.30 ≤ VCC ≤ 2.70 2.3 4.7 5.8 2.1 6.5 3.00 ≤ VCC ≤ 3.60 2.0 4.0 5.1 1.8 5.5 0.80 32.1 1.10 ≤ VCC ≤ 1.30 CL=30pF, 1.40 ≤ VCC ≤ 1.60 R =1MΩ L 1.65 ≤ VCC ≤ 1.95 3.4 9.5 18.5 3.4 19.0 3.1 5.9 10.5 3.1 11.0 1.8 4.8 8.7 1.8 9.5 2.30 ≤ VCC ≤ 2.70 1.7 3.7 6.5 1.7 7.1 3.00 ≤ VCC ≤ 3.60 1.3 3.1 5.6 1.3 6.3 CIN Input Capacitance 0 2.1 pF COUT Output Capacitance 0 3,0 pF CPD Power Dissipation Capacitance 0.80 1.7 1.10 ≤ VCC ≤ 1.30 1.8 1.40 ≤ VCC ≤ 1.60 VIN=0V or VCC, 1.65 ≤ V ≤ 1.95 f=10MHz 1.81 2.30 ≤ VCC ≤ 2.70 2.1 3.00 ≤ VCC ≤ 3.60 2.5 1.84 CC © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 Figure 25.1 0.80 1.10 ≤ VCC ≤ 1.30 1.40 ≤ VCC ≤ 1.60 TA=-40 to +85°C TA=+25°C Figure 10 Figure 11 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate AC Electrical Characteristics pF www.fairchildsemi.com 7 Figure 10. AC Test Circuit Figure 11. AC Waveforms VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.10V 1.2V ± 0.10V 0.8V Vmi VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 Vmo VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate AC Loadings and Waveforms www.fairchildsemi.com 8 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate Physical Dimensions 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X Notes: (0.13) 4X BOTTOM VIEW DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 12. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 9 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 0.35 6 5 4 BOTTOM VIEW 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 Figure 13. 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 10 74AUP1G97 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate © 2008 Fairchild Semiconductor Corporation 74AUP1G97 • 1.0.5 www.fairchildsemi.com 11