FAN5903 Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Features Description 2.7 V to 5.5 V Input Voltage Range VOUT Range from 0.4 V to 3.5 V (or VIN) Small Form Factor Inductor o 2012 470 nH or 540 nH for Minimal PCB Area o 2520 1.0 µH for Higher Efficiency FAN5903 is a high-efficiency, low-noise, synchronous, step-down, DC-DC converter designed for powering 3G / 3.5G / 4G RF Power Amplifiers (PAs) in handsets and other mobile applications. The output voltage may be dynamically varied from 0.40 V to 3.50 V, proportional to an analog input VCON, ranging from 0.16 V to 1.40 V provided by an external DAC. This allows the PA to be supplied with the voltage that enables maximum power-added efficiency. Bypass Dropout at 500 mA, 60 mV Typical 3 MHz / 6 MHz Selectable Switching Frequency to Facilitate System Optimization High-Efficiency PFM Operation at Low Power Up to 96% Efficient Synchronous Operation at High-Power Conditions The FAN5903 offers fast transition times, enabling changes to the output voltage in less than 10 µs for power transitions. Moreover, a Current-Mode control loop with fast transient response ensures excellent line and load regulation. 10 µs Output Voltage Step Response for Early Power Loop Settling Light-load efficiency is optimized by operating in PFM Mode for load currents typically less than 100 mA. 100% Duty Cycle for Low Dropout Operation Input Under-Voltage Lockout / Thermal Shutdown 1.34 mm x 1.29 mm, 9-Bump, 0.4 mm-Pitch, Wafer-Level Chip-Scale Package (WLCSP) Sleep Mode for Very Low IQ Operation Applications Dynamic Supply Bias for 3G/3.5G and 4G PAs Power Supply for WCDMA/LTE PAs Resources For more information or a full copy of this datasheet, please contact a Fairchild representative. An integrated bypass FET automatically switches on when battery voltage drops close to the desired output voltage (VOUT = VBAT - 200 mV). The DC-DC switches back to Synchronous Mode when the voltage dropout exceeds 375 mV. The integrated bypass FET is also enabled when VCON is nominally greater than to 1.5 V. FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs June 2013 The switching frequency may be set to 3 MHz or 6 MHz, enabling further optimization of system performance. The FAN5903 typically uses a single, small-form-factor inductor of 470 nH or 540 nH. Efficiency may be further optimized using a 1.0 µH inductor when running at 3 MHz. When output regulation is not required, the FAN5903 may be placed in Sleep Mode by setting VCON nominally to 50 mV. This ensures a very low IQ (<70 µA) while enabling a fast return to output regulation. The FAN5903 enables significant current reduction and increased talk time and is available in a 1.34 mm x 1.29 mm, 9-bump, 0.40 mm-pitch, WLCSP package. Ordering Information Part Number Operating Temperature Range FAN5903UCX -40 to +85°C © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 Package 1.34 mm x 1.29 mm, 9-bump, 0.4 mm Pitch, Wafer-Level Chip-Scale Package (WLCSP) Packing Method Tape and Reel www.fairchildsemi.com CIN 10 µF EN COUT FB FAN5903 FSEL 4.7 µF PGND 3/6 MHz DC-DC VCON AGND BPEN From External DAC VOUT SW 470nH L1 PVIN Figure 1. Application Circuit FAN5903 Bypass Controller PVIN VIN 2.7V – 4.5V CPA PA UMTS BAND 1, … ,13 CIN CPA FB 0.4Vto 3.4V Up to 800mArms Switcher GPIO GPIO Optional L1 BPEN Optional PFM/PWM Controller SW FSEL GPIO FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Application Diagrams VOUT PA UMTS BAND 1, … ,13 COUT CPA EN PGND DAC/GPIO VCON PA Reference AGND UMTS BAND 1, … ,13 CHIPSET Bandgap CPA PA UMTS BAND 1, … ,13 CPA PA UMTS BAND 1, … ,13 Figure 2. Typical Application with a 5-Band WCDMA / HSPA PA System © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 2 PGND PGND AGND VCON A1 A2 A3 A3 A2 A1 EN FSEL SW SW FSEL EN B1 B2 B3 B3 B2 B1 BPEN FB PVIN PVIN FB BPEN C1 C2 C3 C3 C2 C1 0.4 1.29 mm 1.29 mm 0.4 AGND 0.4 VCON 1.34 mm 1.34 mm Figure 3. Top-Through View, Bumps Face Down 0.4 Figure 4. Top-Through View, Bumps Face Up Pin Definitions Pin # Name Description A1 VCON Analog control pin. Shield signal routing against noise. A2 AGND Analog ground, reference ground for the IC. Follow PCB routing notes for connecting this pin. A3 PGND Power ground of the internal MOSFET switches. Follow routing notes for connections between PGND and AGND. B1 EN Enables switching when HIGH, Shutdown Mode when LOW. This pin should not be left floating. B2 FSEL Switching frequency select. When FSEL is LOW, the DC-DC operates at 6 MHz. When FSEL is HIGH, the DC-DC operates at 3 MHz. This pin should not be left floating. B3 SW C1 BPEN C2 FB C3 PVIN FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Pin Configuration Switching node of the internal MOSFET switches. Connect to output inductor. Force bypass transistor when HIGH; auto-bypass when LOW. This pin should not be left floating. Output voltage-sense pin. Connect to VOUT to establish feedback path for regulation point. Supply voltage input to the internal MOSFET switches; connect to input power source. © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Min. Max. PVIN -0.3 6.0 Voltage On Any Other Pin -0.3 PVIN + 0.3 TJ Junction Temperature -40 +125 °C TSTG Storage Temperature -65 +150 °C +260 °C VIN TL ESD Parameter Lead Soldering Temperature (10 Seconds) Electrostatic Discharge Protection Human Body Model, JESD22-A114 2.0 Charged Device Model, JESD22-C101 1.5 Unit V kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Typ. Max. Unit VIN Supply Voltage Range 2.7 5.5 V VOUT Output Voltage Range 0.35 <VIN V 2.4 A 1.0 A IOUT_BYP Output Current (Bypass Mode) IOUT_DCDC Output Current (DCDC Mode) L1 470 fSW = 6 MHz Inductor fSW = 3 MHz CIN COUT Input Capacitor nH 540 (1) FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Absolute Maximum Ratings 1.00 µH 10 µF 4.7 µF Output Capacitor 2.2 TA Operating Ambient Temperature Range -40 +85 °C TJ Operating Junction Temperature Range -40 +125 °C Note: 1. A large enough input capacitor value is required for limiting the input voltage drop during bursts, bypass transitions, or during large output voltage transitions. Ensure the input capacitor value is greater than the output capacitor’s. See the inrush current specifications below. Dissipation Ratings Symbol ΘJA Parameter Min. (2) Junction-to-Ambient Thermal Resistance Typ. 110 Max. Unit °C/W Note: 2. Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer 2s2p boards in accordance to JESD51- JEDEC standard. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperate TA. © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 4 VIN = VOUT + 0.6 V, IOUT = 200 mA, EN = VIN, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VIN = 3.7 V. Symbol Parameter Condition Min. Typ. Max. Unit 5.5 V 3 µA Power Supplies VIN Input Voltage Range IOUT ≤ 800 mA ISD Shutdown Supply Current EN = 0 V 1 IQ Quiescent Current Sleep Enabled 70 VUVLO VIH Under Voltage Lockout Threshold VIN Rising 2.7 2.30 Hysteresis VIL Logic Threshold Voltage: EN, FSEL and BPEN Input HIGH Threshold IEN EN Input Bias Current EN = VIN or GND fSW Average Oscillator Frequency FSEL = 0 fSW Average Oscillator Frequency FSEL = 1 2.45 µA 2.60 175 V mV 1.2 V Input LOW Threshold 0.5 V 0.01 1.00 µA 5.4 6.0 6.6 MHz 2.7 3.0 3.3 MHz Oscillator DC-DC Mode RDSON PMOS On Resistance(3) VIN = VGS = 3.7 V 230 mΩ NMOS On Resistance(3) VIN = VGS = 3.7 V 150 mΩ ILIMp P-Channel Current Limit 1.2 1.5 1.8 A ILIMn N-Channel Current Limit 0.8 1.1 1.4 A VOUT_MIN Minimum Output Voltage VCON = 0.16 V 0.35 0.40 0.45 V VOUT_MAX Maximum Output Voltage VCON = 1.40 V 3.45 3.50 3.55 V +50 mV Gain VOUT_ACC Gain in Control Range 0.16V to 1.40V VOUT Accuracy 2.5 Ideal = 2.5 x VCON -50 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Electrical Characteristics Bypass Mode RFET VOUT_BP Bypass FET Resistance(4) VIN = VGS = 3.7 V Bypass Mode Output Voltage Drop IOUT = 500 mA 210 mΩ 60 mV +5 mV +25 mV Output Regulation VOUT_RLine VOUT Line Regulation VOUT_RL VOUT Load Regulation IOUT ≤ 800 mA VCON_SL_EN VCON Sleep Mode Enter VCON Voltage that Forces Very Low IQ Sleep Mode VCON_SL_EX VCON Sleep Mode Exit VCON Voltage that Exits Sleep Mode VCON_BP_EN VCON Forced Bypass Mode Enter VCON Voltage that Forces Bypass, VIN = 2.70 V – 4.75 V VCON_BP_EX VCON Forced Bypass Mode Exit VCON Voltage that Exits Forced; Bypass, VIN = 2.70 V – 4.75 V 50 mV 135 1.6 mV V 1.4 V VBP_ThH Voltage Threshold to Enter Bypass VIN – VOUT Mode 160 200 240 mV VBP_ThL Voltage Threshold to Exit Bypass Mode 320 375 440 mV TOTP Over-Temperature Protection © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 VIN – VOUT Rising Temperature +150 Hysteresis +20 °C www.fairchildsemi.com 5 VIN = VOUT + 0.6 V, IOUT = 200 mA, EN = VIN, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, VIN = 3.7 V. Symbol Parameter Condition Min. Typ. Max. Unit 40 µs Timings Startup Time VIN = 3.7 V, VOUT from 0 V to 3.1 V, COUT = 4.7 µF, 10 V, X5R 30 tSP_en Sleep Mode Enter Time VCON < 50 mV 40 µs tSP_ex Sleep Mode Exit Time VCON ≥ 135 mV 11 µs tDC-DC_TR VOUT Step Response Rise Time(3) VOUT from 5% to 95%, VOUT < 2 V (1.4 V – 3.4 V) , RLOAD ≤ 7 10 µs tDC-DC_TF VOUT Step Response Fall Time(3) VOUT from 95% to 5%, VOUT < 2 V (3.4 V – 1.4 V), RLOAD ≤ 7 12 µs tDC-DC_CL Maximum Allowed Time for (5) Consecutive Current Limits 40 µs tDCDC_CLR Consecutive Current Limit Recovery Time(3) 180 µs tSS Notes: 3. Guaranteed by design; not tested in production. 4. Bypass FET resistance does not include the PFET RDSON and inductor DCR in parallel with the bypass FET in Bypass Mode. 5. Protects part under short circuit conditions. After 40 µs, operation halts and restarts after 180 µs. Under heavy capacitive loads, VCON slew rate may be reduced to avoid consecutive current limits. Under typical conditions for a 3 V change at the output, a capacitive only load of up to 40 µF is supported, assuming a step at the VCON input. © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Electrical Characteristics www.fairchildsemi.com 6 Unless otherwise noted, VIN = EN = 3.7 V, L1 = 1.0 µH, CLOAD = 4.7 µF, and TA = +25°C. 90% 90% 80% 80% Efficiency (%) 100% Efficiency (%) 100% 70% VIN = 2.7V VIN = 3.7V VIN = 4.2V VIN = 5.5V 60% 50% 40% 70% 60% VIN = 2.7V 50% VIN = 4.2V VIN = 3.7V VIN = 5.5V 40% 0 100 200 300 400 500 0 Output Current (mA) 90% 80% 80% Efficiency (%) 90% Efficiency (%) 100% 70% VIN = 2.7V VIN = 3.7V VIN = 4.2V VIN = 5.5V 1 2 3 70% VIN = 2.7V 60% VIN = 3.7V VIN = 4.2V 50% VIN = 5.5V 0 4 Figure 7. Efficiency vs. Output Voltage vs. Input Voltage, fSW = 6 MHz, RPA = 7 90% 80% 80% Efficiency (%) 90% Efficiency (%) 100% 70% VIN = 2.7V VIN = 3.7V VIN = 4.2V VIN = 5.5V 100 200 300 4 400 70% VIN = 2.7V 60% VIN = 3.7V VIN = 4.2V 50% VIN = 5.5V 0 500 100 200 300 400 Output Current (mA) Output Current (mA) Figure 9. Efficiency vs. Output Current vs. Input Voltage, fSW = 3 MHz, RPA = 7 © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 3 40% 40% 0 2 Figure 8. Efficiency vs. Output Voltage vs. Input Voltage, fSW = 6 MHz, RPA = 10 100% 50% 1 Output Voltage (V) Output Voltage (V) 60% 400 40% 40% 0 300 Figure 6. Efficiency vs. Output Current vs. Input Voltage, fSW = 6 MHz, RPA = 10 100% 50% 200 Output Current (mA) Figure 5. Efficiency vs. Output Current vs. Input Voltage, fSW = 6 MHz, RPA = 7 60% 100 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Typical Characteristics Figure 10. Efficiency vs. Output Current vs. Input Voltage, fSW = 3 MHz, RPA = 10 www.fairchildsemi.com 7 Unless otherwise noted, VIN = EN = 3.7 V, L1 = 1.0 µH, CLOAD = 4.7 µF, and TA = +25°C. 90% 90% 80% 80% Efficiency (%) 100% Efficiency (%) 100% 70% VIN = 2.7V VIN = 3.7V VIN = 4.2V VIN = 5.5V 60% 50% 70% VIN = 2.7V 60% VIN = 3.7V VIN = 4.2V 50% VIN = 5.5V 40% 40% 0 1 2 3 4 0 Output Voltage (V) 2 3 4 Output Voltage (V) Figure 11. Efficiency vs. Output Voltage vs. Input Voltage, fSW = 3 MHz, RPA = 7 Figure 12. Efficiency vs. Output Voltage vs. Input Voltage, fSW = 3 MHz, RPA = 10 100 3.30 Sleep Current (mA) Shutdown Current (mA) 1 2.80 2.30 1.80 1.30 -40°C +25°C 0.80 90 80 70 -40°C 60 +25°C +85°C +85°C 50 0.30 2.5 3.5 4.5 2.5 5.5 3.5 4.5 5.5 Input Voltage (V) Input Voltage (V) Figure 13. Shutdown Current vs. Input Voltage vs. Temperature Figure 14. Sleep Mode Current vs. Input Voltage vs. Temperature Figure 15. Rise Times for 300 mV, 500 mV, and 2 V VOUT (VIN = 3.7 V) Figure 16. Rise Times for 300 mV, 500 mV, and 2 V VOUT (VIN = 3.7 V) © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Typical Characteristics www.fairchildsemi.com 8 Unless otherwise noted, VIN = EN = 3.7 V, L1 = 1.0 µH, CLOAD = 4.7 µF, and TA = +25°C. Figure 17. Line Transient VIN = 3.7 V to 4.2 V, VOUT = 2.5 V, 10 Load, 50 µs/div. Figure 18. Line Transient VIN = 3.7 V to 4.2 V, VOUT = 1.0 V, 10 Load, 50 µs/div. Figure 19. Load Transient, 0 mA to 400 mA, VOUT = 1.0 V Figure 20. Load Transient, 200 mA to 800 mA, VOUT = 1.0 V Figure 21. Load Transient, 0 mA to 400 mA, VOUT = 2.5 V Figure 22. Load Transient, 200 mA to 800 mA, VOUT = 2.5 V © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Typical Characteristics www.fairchildsemi.com 9 Unless otherwise noted, VIN = EN = 3.7 V, L1 = 1.0 µH, CLOAD = 4.7 µF, and TA = +25°C. Figure 23. Switching Waveforms, PFM Mode, ILOAD = 10 mA (Light Load) Figure 24. Switching Waveforms, PWM Mode, fSW = 6 MHz, ILOAD = 300 mA (Heavy Load) Figure 25. VOUT Rising Transition 0.5 V to 2.5 V, VIN = 3.7 V Figure 26. VOUT Falling Transition 2.5 V to 0.5 V, VIN = 3.7 V Figure 27. VOUT Transient Response VOUT = 3 V Figure 28. VOUT Transient and Bypass Response VOUT > 3 V, VCON Stepped Above 1.5 V © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Typical Characteristics www.fairchildsemi.com 10 Unless otherwise noted, VIN = EN = 3.7 V, L1 = 1.0 µH, CLOAD = 4.7 µF, and TA = +25°C. ILIM Figure 29. Soft-Start Transient Response from 0 mA to 100 mA Figure 30. Cold-Start Transient Response from 0 mA to 100 mA Figure 31. Soft-Start Transient Response from 0 mA to 800 mA Figure 32. Cold-Start Transient Response from 0 mA to 800 mA FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Typical Characteristics Figure 33. Shutdown Transient Response © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 11 FB Bypass Controller PVIN Positive Current Limit CIN PWM VCON Controller SW 3 MHz OSC L1 0 : Div 1 1 : Div 2 COUT FSEL To PWM CTL EN BPEN Negative Current Limit PGND AGND Figure 34. Block Diagram Operating Mode Description The FAN5903 is a high-efficiency synchronous stepdown DC-DC converter operating with a Current-Mode control. It adjusts the output voltage, VOUT, depending on the set voltage VCON provided by an external DAC. Regulated VOUT is set to 2.5 times input voltage VCON. monitored. A current sense flags when the P-channel transistor current exceeds the current limit and the switcher is turned off to decrease the inductor current and prevent magnetic saturation. Similarly, the current sense flags when the N-channel transistor current exceeds the current limit and re-directs discharging current through the inductor back to the battery. The DC-DC operates in PWM Mode or PFM Mode, depending on the output voltage and load current. Bypass Mode is supported where the output voltage is shorted to the input voltage via a low on-state resistance bypass FET. In Pulse Frequency Modulation (PFM) Mode, at low output voltages and load currents, typically less than 100 mA; the DC-DC operates in a constant On-Time Mode. In the on-state, the P-channel is turned on during a well-defined on-time before switching to the off state, whereby the N-channel switch is turned on and the inductor current is decreased to 0 A. The switcher output is put into high-resistance state until the new regulation cycle starts. The FAN5903 supports a wide range of load currents. High-current applications, up to a DC output of 800 mA, mandated by 3G / 3.5G and 4G applications, for example, are supported. System performance may be optimized by enabling the DC-DC to run at either a 3 MHz or 6 MHz switching rate. PFM Mode realizes high efficiency while maintaining RF system performance down to low load currents. Auto Mode In Pulse Width Modulation (PWM) Mode, regulation starts with an on-state where a P-channel transistor is turned on and the inductor current is ramped up until the off state begins. In the off state, the P-channel is switched off and an N-channel transistor is turned on. The inductor current decreases to maintain an average value equal to the DC load current. The inductor current is continuously © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Block Diagram Bypass Mode In Bypass Mode, the FAN5903 operates at 100% duty cycle with the bypass FET turned on. This enables a very low voltage dropout with up to 2.4 A DC load current. In applications with 3G / 3.5G and 4G PAs, the Bypass Mode typically handles 800 mA. www.fairchildsemi.com 12 # Mode Conditions Mode Description FSEL BPEN EN VCON 1 Shutdown Mode The whole IC is disabled. X X 0 0 2 Sleep Mode The DC-DC is in Sleep Mode and consumes less than 70 µA of current. X X 1 0 3 6 MHz Auto Mode The DC-DC is in Auto Mode and switches at 6 MHz.(6,7) 0 0 1 1 4 3 MHz Auto Mode The DC-DC is in Auto Mode and switches at 3 MHz. 1 0 1 1 5 Bypass Mode The bypass FET is forced ON. The DC-DC is set to 100% duty cycle. X 1 1 1 Notes: 6. When VOUT exceeds VIN – 200 mV, the bypass FET is enabled and the DC-DC goes to 100% duty cycle. When VOUT ≤ VIN – 375 mV, the bypass FET is disabled and the DC-DC goes to Auto Mode. 7. When the load current is smaller than PFM current threshold, the DC-DC changes to PFM Mode. DC Output Voltage Bypass Mode The output voltage of the DC-DC is determined by VCON, provided by an external DAC or voltage reference: The trigger to enter Bypass Mode is based on the voltage difference between the battery voltage (sensed through the PVIN pin) and the internally generated reference voltage, VREF, as depicted in Figure 36. The DC-DC enters Bypass Mode when VIN = VOUT + 200 mV. It then turns into 100% duty cycle and the low-RDSON bypass FET is turned on. As VOUT approaches VIN; the DC-DC operates in a constant off-time mode, the frequency is decreased to achieve a high duty cycle, and the system continues to run in a regulated mode until the bypass condition is satisfied. VOUT 2.5 VCON (1) 5.0 4.5 4.0 3.5 VOUT (V) 3.0 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Table 1. Mode Descriptions As noted above, Bypass Mode is also entered when VCON exceeds 1.5 V. 2.5 2.0 1.5 Sleep Mode 1.0 0.0 0.00 FB PVIN DCDC Mode 0.5 Bypass Mode - 0.25 0.50 0.75 1.00 1.25 1.50 1.75 250mV 2.00 VCON (V) VCON + Bypass Slew Controller + VREF - Figure 35. Output Voltage vs. Control Voltage VREF The DC-DC is able to provide a regulated VOUT only if VCON is between 0.16 V to 1.40 V. This allows VOUT to be adjusted between 0.40 V and 3.50 V. If VCON is below this range, VOUT is clamped to 0.40 V as minimum and enters bypass for VCON > 1.50 V. If VCON is less than 50 mV, FAN5903 enters a non-regulated Sleep Mode. This reduces current consumption to less than 70 µA while allowing for a rapid return to regulation. DC-DC Switcher SW L1 Figure 36. Enabling Bypass Transistor Circuit The bypass FET is turned on progressively using a slew rate controller to limit the inrush current. The inrush current is expressed as a function of the specified slew rate as follows: FAN5903 automatically switches between PFM, PWM, and Bypass Modes. I INRUSH COUT The DC-DC is able to provide a regulated VOUT only if the battery voltage is 200 mV greater than VOUT. © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 PWM Controller V REF ranges from 0.4 V to 3.4V when VIN is higher than 3.4V VOUT COUT VBP_SLEW t (2) The slew rate controller is not used when releasing the Bypass Mode. www.fairchildsemi.com 13 In some cases, it may be desirable to change the DCDC’s switching frequency from 6 MHz (FSEL = 0) to 3 MHz (FSEL = 1). At 3 MHz operation the DC-DC’s efficiency is generally higher than that at 6 MHz. The primary tradeoff with this is increased voltage ripple at the lower frequency. A 1.0 µH inductor may be used in 3 MHz operation to optimize efficiency and ripple. VOUT Transition to or from Bypass Mode The transition to or from Bypass Mode requires the bypass conditions be met. The FAN5903 performs detection of the bypass conditions 2 µs after VCON transition and enables the required charging / discharging circuit to realize a transition time of 10 µs. The FAN5903 is designed to have minimal impact on the RF output spectrum at either switching frequency. VOUT Transition at Startup At startup, after EN rising edge is detected, the system requires 40 µs to enable all internal voltage references and amplifiers before enabling the DC-DC function. Dynamic Output Voltage Transitions The FAN5903 has a complex voltage transition controller that realizes less than 10 µs transition times with a large output capacitor and output voltage ranges. VOUT negative step VOUT Transition After BPEN When BPEN goes HIGH, the controller dismisses the internal bypass flags and sensors and enables Bypass Mode. However, the transition is managed with the same current limit and slew rate used during regular transitions. VOUT transition to or from Bypass Mode Thermal Protection VOUT transition at startup If the junction temperature exceeds the maximum specified junction temperature, the FAN5903 enters Power-Down Mode (except the thermal detection circuit). The transition controller manages five transitions: VOUT positive step VOUT transition after BPEN In most cases, sharp VCON transitions and letting the transition controller optimize the output voltage slew rate are recommended. Sleep Mode The FAN5903 offers a Sleep mode to minimize current, while also enabling a rapid return to regulation. Sleep Mode is entered when VCON is held below 50 mV for at least 40 µs. In this mode, current consumption is reduced to under 70 µA. Sleep Mode is exited after approximately 12 µs when VCON is set above 135 mV. VOUT Positive Step After a VCON positive step, the DC-DC enters a CurrentLimit Mode, where VOUT ramps with a constant slew rate dictated by the output capacitor and the current limit. FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs VOUT Negative Step After a VCON negative step, the DC-DC enters CurrentLimit Mode, where VOUT is reduced with a constant slew rate dictated by the output capacitor and the current limit. Switching Frequency Selection (FSEL) Typical Voltage Transitions Figure 37. Rise and Fall Times for 300 mV, 500 mV, and 2 V VOUT (VIN = 3.7 V) © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 Figure 38. Rise Times for 300 mV, 500 mV, and 2 V VOUT (VIN = 3.7 V) www.fairchildsemi.com 14 Figure 39 illustrates an application of the FAN5903 in a 3G / 4G transmitter. The FAN5903 is designed for driving multiple PAs. Figure 40 presents a timing diagram designed to meet WCDMA specifications. The FAN5903 supports voltage transients less than 10 µs. FB PVIN CIN 10µF 540nH FAN5903 SW L1 0.4V to VBAT Up to 800mA DC FSEL COUT BPEN VIN EN From DAC 4.7µF PGND VCON Power Ground Plane AGND Analog Ground Plane VOUT 1000pF 100pF 1000pF 1000pF 100pF 100pF PA PA RF Ground Plane PA RF Ground Plane RF Ground Plane Figure 39. Typical Application Diagram of FAN5903 Supplying Power to Three 3G or 4G PAs 30µs DC-DC_EN VCON 8µs 8µs DC - DC VOUT PA Supply 10ms 10ms 2.5 x VCON RF Power Figure 40. Timing Diagram for 3G/4G Transmitters © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 15 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Application Information Table 2. Recommended Inductors Follow these guidelines: Use a low noise source or a driver with good PSRR to generate VCON. The VCON driver must be referenced to AGND. VCON routing must be protected against PVIN, SW, PGND signals, and other noisy signals. Use AGND shielding for better isolation. Be sure the DAC output can drive the 470 pF capacitor on VCON. It may be necessary to insert a low value resistor to ensure DAC stability without slowing VCON fast transition times. Inductor No Floating Inputs Inductor Selection The FAN5903 is able to operate at 3 MHz or 6 MHz switching frequency, so 470 nH (or 540 nH) or 1.0 µH inductors can be used, respectively. To achieve optimum efficiency, it is recommended that the FAN5903 switch at 3 MHz (FSEL = HIGH), using a 1.0 µH inductor. For applications that require the smallest possible PCB area, the FAN5903 should be configured for 6 MHz operation (FSEL = LOW) to allow use of a 470 nH or 540 nH 2012 inductor. fSW Description The FAN5903 does not have internal pull-down resistors on its inputs. Therefore, unused inputs should not be left floating and should be pulled HIGH or LOW. 470 nH, ±20%, 1100 mA, 2012 (metric) Murata: LQM21PNR47MC0 L1 470 nH, ±30%, 1200 mA, 2012 6 MHz (metric) Panasonic: ELGTEAR47NA PCB Layout & Component Placement 540 nH, ±20%, 1300 mA, 2012 (metric) Murata: LQM21PNR54MG0 1.0 µH, ±20%, 2500 mA, 3030 3 MHz (metric) Coilcraft: XFL3010-102ME Capacitor Selection The minimum required output capacitor COUT is 4.7 µF, 6.3 V, X5R with an ESR of 10 m or lower and an ESL of 0.3 nH or lower. Larger case sizes result in increased loop parasitic inductance and higher noise. Make sure the FAN5903, CIN, and COUT are all tied to the same power ground (PGND). This minimizes the parasitic inductance of the switching loop paths. Place PGND on the top layer and connect it to the AGND ground plane next to COUT using several vias. Ensure that the routing loop, PVIN – PGND – VOUT is the shortest possible. Place the inductor away from the FB connection to prevent unpredictable loop behavior. Use the application circuit layout in Figure 41 whenever possible. The performance of this layout has been verified. Review the layout guidelines for the IC package. This is especially important for the WLCSP package. Refer to “Surface Mount Assembly of Amkor’s Eutectic and Lead-Free CSPnl™ WaferLevel Chip-Scale Package” available from the Amkor website. PVIN and PGND must be routed with the widest and shortest traces possible. It is acceptable for the traces connecting the inductor to be long rather than having long PVIN or PGND traces. The SW node is a source of electrical switching noise. Do not route it near sensitive analog signals. Two small vias are used to connect the SW node to the inductor L1. Use solder-filled vias if available. The connection from COUT to FB should be wide to minimize the Bypass mode voltage drop and the series inductance. Even if the current in Bypass Mode is small, keep this trace short and at least 5mm wide. The ground plane should be not be broken into pieces. Ground currents must have a direct, wide path from input to output. A 0.1 µF capacitor may be added in parallel with COUT to reduce the effect of the capacitor’s parasitic inductance. Table 3. Recommended Capacitor Values Capacitor Description CIN 10 µF, ±20%, X5R, 10 V COUT 4.7 µF, ±20%, X5R, 6.3 V C on VCON 470 pF, ±20%, X5R Filter VCON VCON is the analog control pin of the DC-DC and should be connected to an external Digital-to-Analog Converter (DAC). It is recommended to place up to 470 pF decoupling capacitance between VCON and AGND to filter the DAC noise. This capacitor also helps protect the DAC from the DC-DC high-frequency switching noise coupled through the VCON pin. Any noise on the VCON input is transferred to VOUT with a gain of two and a half (2.5). If the DAC output is noisy, a series resistor may be inserted between the DAC output and the capacitor to form an RC filter. © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 16 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Application Information Assembly Each capacitor should have at least two dedicated ground vias. Place vias within 0.1 mm of the capacitors. Ensure the traces are wide enough to handle the maximum current value, especially in Bypass Mode. Ensure the vias are able to handle the current density. Use metal-filled vias if available. Use metal-filled or solder-filled vias if available. Poor soldering can cause low DC-DC conversion efficiency. If the efficiency is low, X-ray the solder connections to verify their integrity. L1 COUT CIN Figure 41. Recommended PCB Layout © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 17 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs F 0.03 C A E 2X 0.40 B Ø0.20 Cu Pad A1 PIN A1 INDEX AREA 0.40 D Ø0.30 Solder Mask 0.03 C 2X LAND PATTERN RECOMMENDATION (NSMD PAD TYPE) TOP VIEW 0.06 C 0.05 C 0.539 0.461 C SEATING PLANE D 0.292±0.018 E 0.208±0.021 SIDE VIEWS NOTES: A. NO JEDEC REGISTRATION APPLIES. Ø0.260±0.020 9X 0.40 C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 1994. C B A 0.40 B. DIMENSIONS ARE IN MILLIMETERS. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. (Y)±0.018 E. PACKAGE NOMINAL HEIGHT IS 500 MICRONS ±39 MICRONS (461-539 MICRONS). F 1 2 3 (X)±0.018 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. BOTTOM VIEW G. DRAWING FILNAME: MKT-UC009AErev1 Product D E X Y Unit FAN5903UCX 1.292 ± 0.030 1.342 ± 0.030 0.271 0.246 mm Figure 42. 1.34 x 1.29 mm, 9-Bump, 0.4 mm-Pitch WLCSP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 18 FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs Physical Dimensions FAN5903 — Buck Converter with Bypass Mode for 3G / 3.5G / 4G PAs © 2008 Fairchild Semiconductor Corporation FAN5903 • Rev. 1.0.9 www.fairchildsemi.com 19