www.fairchildsemi.com AN-4151 Half-Bridge LLC Resonant Converter Design Using FSFR-Series Fairchild Power Switch (FPS™) Introduction The effort to obtain ever-increasing power density of switched-mode power supply has been limited by the size of passive components. Operation at higher frequencies considerably reduces the size of passive components, such as transformers and filters; however, switching losses have been an obstacle to high-frequency operation. To reduce switching losses and allow high-frequency operation, resonant switching techniques have been developed. These techniques process power in a sinusoidal manner and the switching devices are softly commutated. Therefore, the switching losses and noise can be dramatically reduced [1-7]. Among various kinds of resonant converters, the simplest and most popular resonant converter is the LC series resonant converter, where the rectifier-load network is placed in series with the L-C resonant network, as depicted in Figure 1 [2-4]. In this configuration, the resonant network and the load act as a voltage divider. By changing the frequency of driving voltage Vd, the impedance of the resonant network changes. The input voltage is split between this impedance and the reflected load. Since it is a voltage divider, the DC gain of a LC series resonant converter is always <1. At light-load condition, the impedance of the load is very large compared to the impedance of the resonant network; all the input voltage is imposed on the load. This makes it difficult to regulate the output at light load. Theoretically, frequency should be infinite to regulate the output at no load. Q1 Lr Vin n:1 Vd Ro Q2 + VO - Cr Figure 1. Half-Bridge LC Series Resonant Converter To overcome the limitation of series resonant converters, LLC resonant converter has been proposed [8-12]. LLC resonant converter is a modified LC series resonant converter implemented by placing a shunt inductor across the transformer primary winding as depicted in Figure 2. When this topology was first presented, it did not receive much attention due to the counterintuitive concept that © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 increasing the circulating current in the primary side with a shunt inductor can be beneficial to circuit operation. However, it can be very effective in improving efficiency for high-input voltage application where the switching loss is much more dominant than the conduction loss. In most of the practical design, this shunt inductor is realized using the magnetizing inductance of the transformer. The circuit diagram of LLC resonant converter looks much the same as the LC series resonant converter: The only difference is the value of the magnetizing inductor. While the series resonant converter has a magnetizing inductance much larger than the LC series resonant inductor (Lr), the magnetizing inductance in LLC resonant converter is just 3~8 times Lr, which is usually implemented by introducing an air gap in the transformer. Q1 Lr Vin n:1 Ro Q2 Lshunt + VO ( Lm ) Cr Figure 2. Half-bridge LLC Resonant Converter An LLC resonant converter has many advantages over a series resonant converter; it can regulate the output over wide line and load variations with a relatively small variation of switching frequency. It can achieve zero voltage switching (ZVS) over the entire operating range. All essential parasitic elements, including junction capacitances of all semi-conductor devices and the leakage inductance and magnetizing inductance of the transformer, are utilized to achieve soft-switching. This application note presents design considerations of an LLC resonant half-bridge converter employing FSFRseries FPS™. It includes explanation of LLC resonant converter operation principle, designing the transformer and resonant network, and selecting the components. The step-by-step design procedure explained with a design example helps design the LLC resonant converter. 1. LLC Resonant Converter and Fundamental Approximation www.fairchildsemi.com AN-4151 APPLICATION NOTE Figure 3 shows the simplified schematic of a half-bridge LLC resonant converter, where Lm is the magnetizing inductance that acts as a shunt inductor, Lr is the series resonant inductor, and Cr is the resonant capacitor. Figure 4 illustrates the typical waveforms of the LLC resonant converter. It is assumed that the operation frequency is same as the resonance frequency, determined by the resonance between Lr and Cr. Since the magnetizing inductor is relatively small, there exists considerable amount of magnetizing current (Im), which freewheels in the primary side without being involved in the power transfer. The primary-side current (Ip) is sum of the magnetizing current and the secondary-side current referred to the primary. Ip IDS1 ID Vin In general, the LLC resonant topology consists of three stages shown in Figure 3; square wave generator, resonant network, and rectifier network. Vd Vgs1 Im The square wave generator produces a square wave voltage, Vd, by driving switches Q1 and Q2 alternately with 50% duty cycle for each switch. A small dead time is usually introduced between the consecutive transitions. The square wave generator stage can be built as a full-bridge or half-bridge type. The resonant network consists of a capacitor, leakage inductances, and the magnetizing inductance of the transformer. The resonant network filters the higher harmonic currents. Essentially, only sinusoidal current is allowed to flow through the resonant network even though a square wave voltage is applied to the resonant network. The current (Ip) lags the voltage applied to the resonant network (that is, the fundamental component of the square wave voltage (Vd) applied to the half-bridge totem pole), which allows the MOSFETs to be turned on with zero voltage. As shown in Figure 4, the MOSFET turns on while the voltage across the MOSFET is zero by flowing current through the anti-parallel diode. The rectifier network produces DC voltage by rectifying the AC current with rectifier diodes and capacitor. The rectifier network can be implemented as a full-wave bridge or center-tapped configuration with capacitive output filter. Vgs2 Figure 4. Typical Waveforms of Half-bridge LLC Resonant Converter The filtering action of the resonant network allows use of the fundamental approximation to obtain the voltage gain of the resonant converter, which assumes that only the fundamental component of the square-wave voltage input to the resonant network contributes to the power transfer to the output. Because the rectifier circuit in the secondary side acts as an impedance transformer, the equivalent load resistance is different from actual load resistance. Figure 5 shows how this equivalent load resistance is derived. The primary-side circuit is replaced by a sinusoidal current source, Iac, and a square wave of voltage, VRI, appears at the input to the rectifier. Since the average of |Iac| is the output current, Io, Iac, is obtained as: I ac Square wave generator Io 2 sin(t ) and VRI is given as: VRI Vo if sin(t ) 0 VRI Vo if sin(t ) 0 (1) (2) where Vo is the output voltage. Q1 resonant network IDS1 Vin Q2 Ip + Lr Vd Im - Cr n:1 The fundamental component of VRI is given as: Rectifier network ID VRI F Io Ro Lm 4Vo sin(t ) Since harmonic components of VRI are not involved in the power transfer, AC equivalent load resistance can be calculated by dividing VRIF by Iac as: + VO - Rac Figure 3. Schematic of Half-bridge LLC Resonant Converter VRI F 8 V 8 2 o 2 Ro I ac Io (4) Considering the transformer turns ratio (n=N p/Ns), the equivalent load resistance shown in the primary side is obtained as: Rac © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 (3) 8n 2 2 Ro (5) www.fairchildsemi.com 2 AN-4151 APPLICATION NOTE By using the equivalent load resistance, the AC equivalent circuit is obtained, as illustrated in Figure 6, where VdF and VROF are the fundamental components of the driving voltage, Vd and reflected output voltage, VRO (nVRI), respectively. where: Lp Lm Lr , Rac Q + + VRI Ro M - I ac Iac VRIF Vo Io 2 VRI F VRI sin( wt ) 4Vo Lr sin( wt ) + + - - Np:Ns Rac 8n 2 2 1 , p Lr Cr Ro Ro VRoF Rac Lm (nVRIF) fp Figure 6. AC Equivalent Circuit for LLC Resonant Converter 2 2n Vo (m 1) p 1 at o (7) Vin o 2 p 2 1 2 L p Cr fo 1 2 Lr Cr 2.0 Q=0.25 Q 1.8 With the equivalent load resistance obtained in Equation 5, the characteristics of the LLC resonant converter can be derived. Using the AC equivalent circuit of Figure 6, the voltage gain, M, is obtained as: Lr / Cr Rac Q=1.0 1.6 Gain ( 2nVo / Vin ) Q=0.75 4n Vo M 1 L p Cr The operating range of the LLC resonant converter is limited by the peak gain (attainable maximum gain), which is indicated with „*‟ in Figure 7. It should be noted that the peak voltage gain does not occur at fo nor fp. The peak gain frequency where the peak gain is obtained exists between fp and fo, as shown in Figure 7. As Q decreases (as load decreases), the peak gain frequency moves to fp and higher peak gain is obtained. Meanwhile, as Q increases (as load increases), the peak gain frequency moves to fo and the peak gain drops; thus, the full load condition should be the worst case for the resonant network design. - Lr Cr VdF VO VRI Lm n=Np/Ns Lr The gain of Equation 6 is plotted in Figure 7 for different Q values with m=3, fo=100kHz, and fp=57kHz. As observed in Figure 7, the LLC resonant converter shows gain characteristics that are almost independent of the load when the switching frequency is around the resonant frequency, fo. This is a distinct advantage of LLC-type resonant converter over the conventional series resonant converter. Therefore, it is natural to operate the converter around the resonant frequency to minimize the switching frequency variation. Figure 5. Derivation of Equivalent Load Resistance Rac Vin Lp Equation 6 shows the gain is unity at resonant frequency (ωo), regardless of the load variation, which is given as: VO - Cr Ro , m As can be seen in Equation 6, there are two resonant frequencies. One is determined by Lr and Cr, while the other is determined by Lp and Cr. Io Vd + 2 pk I ac Iac Lr 1 , o Cr Rac 8n 2 sin(t ) VRO F n VRI F 2n Vo F F 4 Vin Vd Vd Vin sin(t ) (6) 2 1.4 Q=0.50 Q=0.25 1.2 1.0 2 ) (m 1) o 2 2 ( 2 1) j ( 2 1)(m 1)Q p o o Q=1.0 ( M @ fo 1 0.8 0.6 40 50 60 70 80 90 100 110 120 130 140 freq (kHz) Figure 7. Typical Gain Curves of LLC Resonant Converter (m=3) © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 3 AN-4151 APPLICATION NOTE 2. Consideration for Integrated Transformer 2n VO M Vin For practical design, it is common to implement the magnetic components (series inductor and shunt inductor) using an integrated transformer; where the leakage inductance is used as a series inductor, while the magnetizing inductor is used as a shunt inductor. When building the magnetizing components in this way, the equivalent circuit in Figure 6 should be modified as shown in Figure 8 because the leakage inductance exists, not only in the primary side, but also in the secondary side. Not considering the leakage inductance in the transformer secondary side generally results in an incorrect design. Cr Vd + Vin Llks Llkp where: L 8n 2 Ro , m p 2 MV 2 Lr Qe Lr 1 , o Cr Rac e M MV Ro n:1 Rac e 1 , p Lr Cr 1 LpCr The gain at the resonant frequency (ωo) is fixed regardless of the load variation, which is given as: + - - 2 ) m(m 1) o 2 2 2 ( 2 1) j ( ) ( 2 1) ( m 1) Q e p o o VRI Lm (9) ( VO + 2 ) (m 1) M V o 2 2 ( 2 1) j ( ) ( 2 1) ( m 1)Q e p o o ( Lp Lp Lr m m 1 at o (10) - Lr Llkp Lm //(n Llks ) 2 Llkp Lm // Llkp Lp Llkp Lm + Vin F Cr 1: M V Lr Lp-Lr (MV Lp Lp Lr ideal transformer Rac The gain at the resonant frequency (ωo) is unity when using individual core for series inductor, as shown in Equation 7. However, when implementing the magnetic components with integrated transformer, the gain at the resonant frequency (ωo) is larger than unity due to the virtual gain caused by the leakage inductance in the transformer secondary side. ) + VROF (nVRIF) - - The gain of Equation 9 is plotted in Figure 10 for different Qe values with m=3, fo=100kHz, and fp=57kHz. As observed in Figure 9, the LLC resonant converter shows gain characteristics almost independent of the load when the switching frequency is around the resonant frequency, fo. Figure 8. Modified Equivalent Circuit to Accommodate the Secondary-side Leakage Inductance In Figure 8, the effective series inductor (Lp) and shunt inductor (Lp-Lr) are obtained by assuming n2Llks=Llkp and referring the secondary-side leakage inductance to the primary side as: Lp Lm Llkp Lr Llkp Lm //(n 2 Llks ) Llkp Lm // Llkp fp 2.2 1 2 L p Cr fo 1 2 Lr Cr Qe=0.25 Qe 2.0 Lr / Cr Rac e (8) Qe=1.00 1.8 Gain ( 2nVo / Vin ) Qe=0.75 When handling an actual transformer, equivalent circuit with Lp and Lr is preferred since these values can be easily measured with a given transformer. In an actual transformer, Lp and Lr can be measured in the primary side with the secondary-side winding open circuited and short circuited, respectively. Qe=0.25 1.4 1.2 M @ fo M V Qe=1.0 In Figure 9, notice that a virtual gain MV is introduced, which is caused by the secondary-side leakage inductance. By adjusting the gain equation of Equation 6 using the modified equivalent circuit of Figure 9, the gain equation for integrated transformer is obtained: © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 Qe=0.50 1.6 1.0 0.8 40 50 60 70 80 90 100 110 120 130 140 freq (kHz) Figure 9. Typical Gain Curves of LLC Resonant Converter (m=3) Using an Integrated Transformer www.fairchildsemi.com 4 AN-4151 APPLICATION NOTE 3. Consideration of Operation Mode and Attainable Maximum Gain Operation Mode The LLC resonant converter can operate at frequency below or above the resonance frequency (fo), as illustrated in Figure 10. Figure 11 shows the waveforms of the currents in the transformer primary side and secondary side for each operation mode. Operation below the resonant frequency (case I) allows the soft commutation of the rectifier diodes in the secondary side, while the circulating current is relatively large. The circulating current increases more as the operation frequency moves downward from the resonant frequency. Meanwhile, operation above the resonant frequency (case II) allows the circulating current to be minimized, but the rectifier diodes are not softly commutated. Below resonance operation is preferred for high output voltage applications, such as Plasma Display Panel (PDP) TV where the reverse recovery loss in the rectifier diode is severe. Below resonance operation also has a narrow frequency range with respect to the load variation since the frequency is limited below the resonance frequency even at no load condition. Im (I) fs < fo 1 2 fS IDS1 IO ID (II) fs > fo Ip Im IDS1 ID IO Figure 11. Waveforms of Each Operation Mode Required Maximum Gain and Peak Gain Above the peak gain frequency, the input impedance of the resonant network is inductive and the input current of the resonant network (Ip) lags the voltage applied to the resonant network (Vd). This permits the MOSFETs to turn on with zero voltage (ZVS), as illustrated in Figure 12. Meanwhile, the input impedance of the resonant network becomes capacitive and Ip leads Vd below the peak gain frequency. When operating in capacitive region, the MOSFET body diode is reverse recovered during the switching transition, which results in severe noise. Another problem of entering into the capacitive region is that the output voltage becomes out of control since the slope of the gain is reversed. The minimum switching frequency should be well limited above the peak gain frequency. On the other hand, above resonance operation has less conduction loss than the below resonance operation. It can show better efficiency for low output voltage applications, such as Liquid Crystal Display (LCD) TV or laptop adaptor, where Schottky diodes are available for the secondary-side rectifiers and reverse recovery problems are insignificant. However, operation at above the resonant frequency may cause too much frequency increase at lightload condition. Above frequency operation requires frequency skipping to prevent too much increase of the switching frequency. Gain (M) 1 2 fo Ip B M A capacitive region Load increase peak gain inductive region I fs II Below resonance (fs<fo) Above resonance (fs>fo) fo fs Figure 10. Operation Modes According to the Operation Frequency Vd Vd Ip Ip IDS1 IDS1 reverse recovery ZVS Figure 12. Operation Waveforms for Capacitive and Inductive Regions © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 5 AN-4151 APPLICATION NOTE 2.2 The available input voltage range of the LLC resonant converter is determined by the peak voltage gain. Thus, the resonant network should be designed so that the gain curve has an enough peak gain to cover the input voltage range. However, ZVS condition is lost below the peak gain point, as depicted in Figure 12. Therefore, some margin is required when determining the maximum gain to guarantee stable ZVS operation during the load transient and start-up. Typically 10~20% of the maximum gain is used as a margin for practical design, as shown in Figure 13. 2.1 2 1.9 1.8 peak gain 1.7 Gain (M) peak gain 10~20% of Mmax 1.6 1.5 m=2.25 1.4 m=2.5 maximum operation gain (Mmax) 1.3 m=3.0 1.2 m=6.0 m=9.0 m=8.0 m=7.0 1.1 m=3.5 m=4.0 m=4.5 m=5.0 1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 Q fo fs Figure 14. Peak Gain (Attainable Maximum Gain) vs. Q for Different m Values Figure 13. Determining the Maximum Gain Even though the peak gain at a given condition can be obtained by using the gain in Equation 6, it is difficult to express the peak gain in explicit form. To simplify the analysis and design, the peak gains are obtained using simulation tools and depicted in Figure 14, which shows how the peak gain (attainable maximum gain) varies with Q for different m values. It appears that higher peak gain can be obtained by reducing m or Q values. With a given resonant frequency (fo) and Q value, decreasing m means reducing the magnetizing inductance, which results in increased circulating current. Accordingly, there is a tradeoff between the available gain range and conduction loss. © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 6 AN-4151 APPLICATION NOTE 4. Features of FSFR-Series Table 1. FSFR-series is an integrated Pulse Frequency Modulation (PFM) controller and MOSFETs specifically designed for Zero Voltage Switching (ZVS) half-bridge converters with minimal external components. The internal controller includes an under-voltage lockout, optimized high-side / low-side gate driver, temperature-compensated precise current controlled oscillator, and self-protection circuitry. Compared with discrete MOSFET and PWM controller solution, FSFR-series can reduce total cost, component count, size and weight, while simultaneously increasing efficiency, productivity, and system reliability. This pin is the drain of the high-side MOSFET, typically connected to the input DC link voltage. This pin is for enable/disable and protection. When the voltage of this pin is above 0.6V, the IC operation is enabled. Meanwhile, CON when the voltage of this pin drops below 0.4V, gate drive signals for both MOSFETs are disabled. When the voltage of this pin increases above 5V, protection is triggered. This pin is to program the switching frequency. Typically, opto-coupler and RT resistor are connected to this pin to regulate the output voltage. 1 VDL 2 3 4 CS This pin is to sense the current flowing through the low-side MOSFET. Typically negative voltage is applied on this pin. 5 SG This pin is the control ground. This pin is the power ground. This pin is connected to the source of the low-side MOSFET. This pin is the supply voltage of the control LVcc IC. 6 PG 7 1 2 VDL 3 4 5 6 7 8 RT SG LVcc CON CS PG 9 Pin Description No connection. 8 NC 9 HVcc 10 VCTR 10 VCTR HVcc This pin is the supply voltage of the highside drive circuit. This pin is the drain of the low-side MOSFET. Typically transformer is connected to this pin. Figure 15. Package Diagram LVcc VDL 7 1 ICTC + 2ICTC 3V - 1V + S Q R -Q 11.3 / 14.5 V Vref 8.7 / 9.2 V - HVcc good Internal Bias + ICTC VREF LVcc good - + F/F 9 HVcc 10 VCTR 8 NC 6 PG 5 SG - 2V + RT Time Delay High-Side Gate Drive Level-Shift - 350ns 3 Counter (1/4) LVcc Idelay CON 2 - Time Delay + 350ns 0.6V/0.4V Low-Side Gate Drive Balancing delay + 5V OLP - LVcc good LVcc S Q R -Q Shutdown without delay OVP Auto-restart protection - 23V -1 + + Q 50ns delay S -Q - 0.9V R VAOCP TSD Latch protection LVcc < 5V - delay 1.5 s VOCP 0.6V + 4 CS Figure 16. Functional Block Diagram of FSFR-series © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 7 AN-4151 APPLICATION NOTE Llks Cr Rdamp Dboot LVcc Vcc C LVcc Llkp Vin (From PFC output) CB Ns HVcc Lm Ns RSS CSS Co VDL RT Rmax Rmin Np D1 Rbias CHVcc CON Control IC VCTR Integrated Llks D2 transformer Vo Rd CF RF KA431 CS CDL CLPF SG PG RLPF Rsense Figure 17. Reference Circuit for Design Example of LLC Resonant Half-bridge Converter 5. Design Procedure In this section, a design procedure is presented using the schematic in Figure 17 as a reference. An integrated transformer with center tap, secondary side is used and input is supplied from power factor correction (PFC) preregulator. A DC/DC converter with 192W/24V output has been selected as a design example. The design specifications are as follows: Vin min VO.PFC 2 (Design Example) Assuming the efficiency is 92%, P 192 Pin o 209W E ff 0.92 Vin max VO.PFC 400V Vin min VO.PFC 2 [STEP-1] Define the system specifications 4002 As a first step, define the following specification. Estimated efficiency (Eff): The power conversion efficiency must be estimated to calculate the maximum input power with a given maximum output power. If no reference data is available, use Eff = 0.88~0.92 for lowvoltage output applications and Eff = 0.92~0.96 for highvoltage output applications. With the estimated efficiency, the maximum input power is given as: Po VO.PFC (11) As observed in Equation 10, the gain at fo is a function of m (m=Lp/Lr). The gain at fo is determined by choosing that value of m. While a higher peak gain can be obtained with a small m value, too small m value results in poor coupling of the transformer and deteriorates the efficiency. It is typical to set m to be 3~7, which results in a voltage gain of 1.1~1.2 at the resonant frequency (fo). (12) Even though the input voltage is regulated as constant by PFC pre-regulator, it drops during the hold-up time. The minimum input voltage considering the hold-up time requirement is given as: © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 2 209 20 103 349V 220 106 As discussed in the previous section, it is typical to operate the LLC resonant converter around the resonant frequency (fo) to minimize switching frequency variation. Since the input of the LLC resonant converter is supplied from PFC output voltage, the converter should be designed to operate at fo for the nominal PFC output voltage. Input voltage range (Vinmin and Vinmax): The maximum input voltage would be the nominal PFC output voltage as: Vin 2 PinTHU CDL [STEP-2] Determine the Maximum and Minimum Voltage Gains of the Resonant Network E ff max (13) where VO.PFC is the nominal PFC output voltage, THU is a hold-up time, and CDL is the DC link bulk capacitor. - Nominal input voltage: 400VDC (output of PFC stage) - Output: 24V/8A (192W) - Hold-up time requirement: 20ms (50Hz line freq.) - DC link capacitor of PFC output: 220µF Pin 2 PinTHU CDL www.fairchildsemi.com 8 AN-4151 APPLICATION NOTE [STEP-4] Calculate the Equivalent Load Resistance With the chosen m value, the voltage gain for the nominal PFC output voltage is obtained as: M min m @f=f o m 1 With the transformer turns ratio obtained from Equation 16, the equivalent load resistance is obtained as: (14) Rac which would be the minimum gain because the nominal PFC output voltage is the maximum input voltage (Vinmax). Vin max min M Vin min Rac (15) 8n2 Vo 2 8 9.02 242 197 2 Po 2 192 [STEP-5] Design the Resonant Network (Design Example) The ratio (m) between Lp and Lr is With m value chosen in STEP-2, read proper Q value from the peak gain curves in Figure 14 that allows enough peak gain. Considering the load transient and stable zerovoltage-switching (ZVS) operation, 10~20% margin should be introduced on the maximum gain when determining the peak gain. Once the Q value is determined, the resonant parameters are obtained as: chosen as 5. The minimum and maximum gains are obtained as: VRO m 5 M min max 1.12 Vin 2 m 1 5 1 M max Vin max min 400 M 1.12 1.28 Vin min 349 Peak gain (available maximum gain) M 1.28 1 2 Q f o Rac 1 Lr (2 f o ) 2 Cr (18) Lp m Lr (20) Cr Gain (M) max (17) (Design Example) The maximum voltage gain is given as: M max 8n 2 Vo 2 2 Po for Vinmin (19) (Design Example) 1.12 Mmin MV As calculated in STEP-2, the maximum voltage gain (M max) for the minimum input voltage (Vinmin) is 1.28. With 15% margin, a peak gain of 1.47 is required. m has been chosen as 5 in STEP-2 and Q is obtained as 0.4 from the peak gain curves in Figure 19. By selecting the resonant frequency as 100kHz, the resonant components are determined as: 1 1 Cr 20.2nF 2 Q fo Rac 2 0.4 100 103 197 1 1 Lr 126 H (2 f o )2 Cr (2 100 103 ) 2 20.2 109 for Vinmax ( VO.PFC ) m 1.12 m 1 fo fs Figure 18. Maximum Gain / Minimum Gain Lp m Lr 630 H [STEP-3] Determine the Transformer Turns Ratio (n=Np/Ns) 1.7 With the minimum gain (Mmin) obtained in STEP-2, the transformer turns ratio is given as: 1.6 Np Ns Vin M min 2(Vo VF ) (16) peak gain n 1.5 max where VF is the secondary-side rectifier diode voltage drop. Np Ns 1.3 1.2 (Design Example) assuming VF is 0.9V, n 1.4 Vin max 400 M min 1.12 9.00 2(Vo VF ) 2(24 0.9) m=6.0 m=9.0 m=8.0 m=7.0 1.1 m=4.0 m=4.5 m=5.0 1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 Q Figure 19. Resonant Network Design Using the Peak Gain (Attainable Maximum Gain) Curve for m=5 © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 9 AN-4151 APPLICATION NOTE [STEP-6] Design the Transformer 2.0 100% load The worst case for the transformer design is the minimum switching frequency condition, which occurs at the minimum input voltage and full-load condition. To obtain the minimum switching frequency, plot the gain curve using gain Equation 9 and read the minimum switching frequency. The minimum number of turns for the transformer primary-side is obtained as: N p min 80% load 1.8 60% load fs normal fs min 40% load 1.6 20% load 1.4 Mmax 1.2 n(Vo VF ) min 2 f s M V B Ae Mmin (21) 1.0 where Ae is the cross-sectional area of the transformer core in m2 and B is the maximum flux density swing in Tesla, as shown in Figure 20. If there is no reference data, use B =0.3~0.4 T. Notice that a virtual gain MV is introduced, which is caused by the secondary-side leakage inductance (Refer to Figure 8). 0.8 0.6 40 50 60 70 80 90 100 110 120 130 140 freq (kHz) Figure 21. Gain Curve n (Vo+VF)/MV VRI 1/(2fs) [STEP-7] Transformer Construction -n (Vo+VF)/MV B B Figure 20. Flux Density Swing Choose the proper number of turns for the secondary side that results in primary-side turns larger than Npmin as: N p n N s N p min Parameters Lp and Lr of the transformer were determined in STEP-5. Lp and Lr can be measured in the primary side with the secondary-side winding open circuited and short circuited, respectively. Since LLC converter design requires a relatively large Lr, a sectional bobbin is typically used, as shown in Figure 22, to obtain the desired Lr value. For a sectional bobbin, the number of turns and winding configuration are the major factors determining the value of Lr, while the gap length of the core does not affect Lr much. Lp can be easily controlled by adjusting the gap length. Table 2 shows measured Lp and Lr values with different gap lengths. A gap length of 0.10mm obtains values for Lp and Lr closest to the designed parameters. Np Ns2 (22) Ns1 2 (Design Example) EER3542 core (Ae=107mm ) is selected for the transformer. From the gain curve of Figure 21, the minimum switching frequency is obtained as 78kHz. The minimum primary-side turns of the transformer is given as N p min n(Vo VF ) 2 f s B 1.12 Ae Figure 22. Sectional Bobbin min 9.0 24.9 30.4 turns 2 77 103 0.4 1.12 107 106 Table 2. Measured Lp and Lr with Different Gap Lengths Choose Ns so that the resultant Np should be larger than Npmin: N p n N s 1 9.0 9 N p min N p n N s 2 9.0 18 N p min N p n N s 3 9.0 27 N p min Gap length Lp Lr 0.0mm 0.05mm 2,295μH 943μH 123μH 122μH 0.10mm 630μH 118μH 0.15mm 488μH 117μH 0.20mm 419μH 115μH 0.25mm 366μH 114μH N p n N s 4 9.0 36 N p min © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 10 AN-4151 APPLICATION NOTE (Design Example) VCr nom Final Resonant Network Design Even though the integrated transformer approach in LLC resonant converter design can implement the magnetic components in a single core and save one magnetic component, the value of Lr is not easy to control in real transformer design. Resonant network design sometimes requires iteration with a resultant Lr value after the transformer is built. The resonant capacitor value is also changed since it should be selected among off-the-shelf capacitors. The final resonant network design is summarized in Table 3 and the new gain curves are shown in Figure 23. Initial design 630µH 126H 20nF 100kHz 5 0.4 Final design 630µH 118µH 22nF 99kHz 5.34 0.36 [email protected] Minimum freq 1.12 78kHz 1.11 72kHz (24) However, the resonant capacitor voltage increases much higher than this at overload condition or load transient. Actual capacitor selection should be based on the OverCurrent Protection (OCP) trip point. With the OCP level, IOCP, the maximum resonant capacitor voltage is obtained as: VCr max Vin max I OCP 2 2 f S min Cr (25) The minimum switching frequency is used in the equation because the frequency is typically forced to the minimum value by the feedback loop when output is overloaded. Table 3. Final Resonant Network Design Parameters Parameters Lp Lr Cr fo m Q Vin max 2 I Cr RMS 2 2 f o Cr (Design Example) I Cr RMS 1 E ff [ Io 2 n(Vo VF ) ] [ ]2 2 2n 4 2 f o M V ( Lp Lr ) 1 8 2 9.0 (24 0.9) [ ] [ ]2 0.92 2 2 9.0 4 2 99 103 1.11 512 106 1.32 A The peak current in the primary side in normal operation is: 2.0 ICr peak 2 ICr rms 1.86 A 100% load 1.8 f f min 80% load normal OCP level is set to 3.0A with 50% margin on ICrpeak: 60% load 40% load 1.6 20% load VCr nom 1.4 M max M min 1.2 400 2 1.32 336V 2 2 99 103 22 109 V max I OCP in 2 2 f S min Cr 1.0 VCr max 0.8 0.6 40 50 60 70 80 90 100 110 120 Vin max 2 I Cr RMS 2 2 f o Cr 130 140 400 3 502V 2 2 72 103 22 109 freq (kHz) Figure 23. Gain Curve of the Final Resonant Network Design [STEP-8] Select the Resonant Capacitor When choosing the resonant capacitor, the current rating should be considered because a considerable amount of current flows through the capacitor. The RMS current through the resonant capacitor is given as: I Cr RMS 1 E ff [ Io 2 2n ]2 [ n(Vo VF ) ]2 (23) 4 2 f o M V ( Lp Lr ) 630V rated low-ESR film capacitor is selected for the resonant capacitor. [STEP-9] Rectifier Network Design When the center tap winding is used in the transformer secondary side, the diode voltage stress is twice the output voltage expressed as: VD 2(Vo VF ) The RMS value of the current flowing through each rectifier diode is given as: The nominal voltage of the resonant capacitor in normal operation is given as: © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 (26) I D RMS 4 Io (27) www.fairchildsemi.com 11 AN-4151 APPLICATION NOTE Meanwhile, the ripple current flowing through output capacitor is given as: I Co RMS ( Io 2 2 )2 I o 2 2 8 8 LVcc RT (28) Io Rmax 2 I o RC stress of the rectifier diode are: VD 2(Vo VF ) 2(24 0.9) 49.8 I o 6.28 A The 100V/20A Schottky diode is selected for the rectifier considering the voltage overshoot caused by the stray inductance. The RMS current of the output capacitor is: I Co RMS ( Io 2 2 )2 I o 2 2 8 8 I o 3.857 A When two electrolytic capacitors with ESR of 80mΩ are used in parallel, the output voltage ripple is given as: Vo 2 I o RC 2 External S/S SG PG (30) (Design Example) The voltage stress and current 4 Control IC Figure 24. Typical Circuit Configuration for RT Pin PLoss.Co ( ICo RMS )2 RC CSS (29) where RC is the effective series resistance (ESR) of the output capacitor and the power dissipation is the output capacitor is: I D RMS RSS Rmin The voltage ripple of the output capacitor is: Vo VDL 8 ( 0.08 ) 0.50V 2 Soft-start: To prevent excessive inrush current and overshoot of output voltage during start-up, increase the voltage gain of the resonant converter progressively. Since the voltage gain of the resonant converter is reversely proportional to the switching frequency, the soft-start is implemented by sweeping down the switching frequency from an initial high frequency (f ISS) until the output voltage is established as illustrated in Figure 25. The softstart circuit is made by connecting RC series network on the RT pin as shown in Figure 24. FSFR-series also has an internal soft-start for 3ms to reduce the current overshoot during the initial cycles, which adds 40kHz to the initial frequency of the external soft-start circuit, as shown in Figure 25. The actual initial frequency of the soft-start is given as: f ISS ( 5.2k 5.2k ) 100 40 (kHz ) (33) Rmin RSS It is typical to set the initial frequency of soft-start (f ISS) as 2~3 times of the resonant frequency (fo). The soft-start time is determined by the RC time constant: The loss in electrolytic capacitors is: TSS 3 ~ 4 times of RSS CSS PLoss.Co ( ICo RMS )2 RC 3.8572 0.04 0.60W (34) fs f ISS [STEP-10] Control Circuit Configuration Figure 24 shows the typical circuit configuration for RT pin of FSFR-series, where the opto-coupler transistor is connected to the RT pin to control the switching frequency. The minimum switching frequency occurs when the optocoupler transistor is fully tuned off, which is given as: Control loop take over 3ms 5.2k (31) 100(kHz ) Rmin Assuming the saturation voltage of opto-coupler transistor is 0.2V, the maximum switching frequency is determined as: f min f max ( 5.2k 4.68k ) 100(kHz ) Rmin Rmax © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 40kHz 3~4 times of RC time constant time Figure 25. Frequency Sweep of the Soft-start (32) www.fairchildsemi.com 12 AN-4151 APPLICATION NOTE Figure 26. Half-wave Sensing (Design Example) The minimum frequency is 72kHz in STEP-6. Rmin is determined as: Rmin I DS 100 kHz 5.2k 7.2k f min VCS Considering the output voltage overshoot during transient (10%) and the controllability of the feedback loop, the maximum frequency is set as 140kHz. Rmax is determined as: Rmax Cr 4.68k f o 1.40 5.2k ( ) 100 kHz Rmin VCS PG SG Rsense Ns Ns IDS Figure 27. Full-wave Sensing Setting the initial frequency of soft-start as 250kHz (2.5 times of the resonant frequency), the soft-start resistor RSS is given as: Np CS 4.68k 7.1k 99kHz 1.4 5.2k ( ) 100 kHz 7.2k RSS Control IC (Design Example) Since the OCP level is determined as 3A in STEP-8 and the OCP threshold voltage is -0.6V, a sensing resistor of 0.2Ω is used. The RC time constant is set to 100ns (1/100 of switching period) with 1kΩ resistor and 100pF capacitor. 5.2k f ISS 40kHz 5.2k ( ) 100kHz Rmin 5.2k 3.8k 250kHz 40kHz 5.2k ( ) 100kHz 7.2k [STEP-11] Current Sensing and Protection FSFR-series senses low-side MOSFET drain current as a negative voltage, as shown in Figure 26 and Figure 27. Half-wave sensing allows low-power dissipation in the sensing resistor, while full-wave sensing has less switching noise in the sensing signal. Typically, RC low-pass filter is used to filter out the switching noise in the sensing signal. The RC time constant of the low-pass filter should be 1/100~1/20 of the switching period. Cr Np Ns Ns Control IC VCS I DS CS SG PG Rsense IDS VCS © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 13 AN-4151 APPLICATION NOTE Design Summary Figure 28 shows the final schematic of the LLC resonant half-bridge converter design example. EER3542 core with sectional bobbin is used for the transformer. The efficiency at full load condition is around 94%. D211 FYP2010DN C102 22nF/ 630V JP1 10 Vcc R106 27 D101 1N4937 LVcc C105 22μF/ 50V Np Ns C107 6.8μF R201 10k C106 150nF CON C108 12nF R107 3.9k Control IC R202 1k VCTR SG R204 62k R206 2k U3 KA431 C102 100pF R102 1kΩ C204 12nF D212 FYP2010DN CS C101 220μF/ 450V Vo Ns HVcc RT R104 7.2k C202 2200μF/ 35V VDL Vin=400Vdc R105 7.2k C201 2200μF/ 35V C203 47nF R203 33k R205 7k PG R101 0.2Ω Figure 28. Final Schematic of Half-bridge LLC Resonant Converter - Core: EER3542 (Ae=107 mm2) - Bobbin: EER3542 (Horizontal/section type) EER3542 1 16 Np Np Ns1 Ns2 1 3 1 2 Ns1 Ns2 8 9 Figure 29. Transformer Structure Pin(S → F) Wire Turns Winding Method Np 8→1 0.12φ×30 (Litz wire) 36 Section winding Ns1 16 → 13 0.1φ×100 (Litz wire) 4 Section winding Ns2 12 → 9 0.1φ×100 (Litz wire) 4 Section winding Pin Specification Remark Primary-side Inductance (Lp) 1－8 630H ± 5% Secondary windings open 100kHz, 1V Equivalent Leakage Inductance (Lr) 1－8 118H Max. Short one of the secondary windings 100kHz, 1V © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 14 AN-4151 APPLICATION NOTE 6. Experimental Verification To show the validity of the design procedure presented in this application note, the converter of the design example has been built and tested. All the circuit components are used as designed in the design example. Figure 30 and Figure 31 show the operation waveforms at full-load and no-load conditions for nominal input voltage. As observed, the MOSFET drain-to-source voltage (VDS) drops to zero by resonance before the MOSFET is turned on and zero voltage switching is achieved. Figure 32 shows the waveforms of the resonant capacitor voltage and primary-side current at full load condition. The peak values of the resonant capacitor voltage and primaryside current are 325V and 1.93A, respectively, which are well matched with the calculated values in STEP-8 of design procedure section. Figure 33 shows the waveforms of the resonant capacitor voltage and primary-side current at output short condition. For output short condition, over current protection (OCP) is triggered when the primaryside current exceeds 3A. The maximum voltage of the resonant capacitor is a little bit higher than the calculated value of 419V because the OCP trips at a level little bit higher than 3A, due to the shutdown delay time of 1.5µs (refer to the FSFR2100 datasheet). Figure 31. Operation Waveforms at No-load Condition Figure 34 shows the rectifier diode voltage and current waveforms at full-load and no-load conditions. Due to the voltage overshoot caused by stray inductance, the voltage stress is a little bit higher than the value calculated in STEP-9. Figure 35 shows the output voltage ripple at fullload and no-load conditions. The output voltage ripple is well matched with the designed value in STEP-9. Figure 32. Resonant Capacitor Voltage and Primaryside Current Waveforms at Full-load Condition Figure 36 shows the measured efficiency for different load conditions. Efficiency at full-load condition is about 94%. Figure 33. Resonant Capacitor Voltage and Primaryside Current Waveforms for Output Short Protection Figure 30. Operation Waveforms at Full-load Condition Figure 34. Rectifier Diode Voltage and Current Waveforms at Full-load Condition © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 15 AN-4151 APPLICATION NOTE Figure 35. Output Voltage Ripple and Primary-Side Current Waveforms at Full-Load Condition Figure 37. Measured Efficiency Figure 36. Soft-start Waveforms © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 www.fairchildsemi.com 16 AN-4151 APPLICATION NOTE 7. References [1] Robert L. Steigerwald, “A Comparison of Half-bridge resonant converter topologies,” IEEE Transactions on Power Electronics, Vol. 3, No. 2, April 1988. [2] A. F. Witulski and R. W. Erickson, “Design of the series resonant converter for minimum stress,” IEEE Transactions on Aerosp. Electron. Syst., Vol. AES-22, pp. 356-363, July 1986. [3] R. Oruganti, J. Yang, and F.C. Lee, “Implementation of Optimal Trajectory Control of Series Resonant Converters,” Proc. IEEE PESC ‟87, 1987. [4] V. Vorperian and S. Cuk, “A Complete DC Analysis of the Series Resonant Converter,” Proc. IEEE PESC‟82, 1982. [5] Y. G. Kang, A. K. Upadhyay, D. L. Stephens, “Analysis and design of a half-bridge parallel resonant converter operating above resonance,” IEEE Transactions on Industry Applications Vol. 27, March-April 1991, pp. 386 – 395. [6] R. Oruganti, J. Yang, and F.C. Lee, “State Plane Analysis of Parallel Resonant Converters,” Proc. IEEE PESC ‟85, 1985. [7] M. Emsermann, “An Approximate Steady State and Small Signal Analysis of the Parallel Resonant Converter Running Above Resonance,” Proc. Power Electronics and Variable Speed Drives ‟91, 1991, pp. 9-14. [8] Yan Liang, Wenduo Liu, Bing Lu, van Wyk, J.D, " Design of integrated passive component for a 1 MHz 1 kW halfbridge LLC resonant converter", IAS 2005, pp. 2223-2228. [9] B. Yang, F.C. Lee, M. Concannon, "Over current protection methods for LLC resonant converter" APEC 2003, pp. 605 - 609. [10] Yilei Gu, Zhengyu Lu, Lijun Hang, Zhaoming Qian, Guisong Huang, "Three-level LLC series resonant DC/DC converter" IEEE Transactions on Power Electronics Vol.20, July 2005, pp.781 – 789. [11] Bo Yang, Lee, F.C, A.J Zhang, Guisong Huang, "LLC resonant converter for front end DC/DC conversion" APEC 2002. pp.1108 – 1112. [12] Bing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D. Van Wyk, “Optimal design methodology for LLC Resonant Converter,” APEC 2006. pp.533-538. Author Hangseok Choi, Ph. D Strategic R&D / Fairchild Semiconductor Email: [email protected] Related Product Information FSFR2100 for 450W - Fairchild Power Switch (FPS) for Half-Bridge Resonant Converters Important Notice DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 17 AN-4151 © 2007 Fairchild Semiconductor Corporation Rev. 1.0.2 • 10/22/14 APPLICATION NOTE www.fairchildsemi.com 18

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