AN-4149 - Fairchild Semiconductor

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Application Note AN4149
Design Guidelines for Quasi-Resonant Converters
Using KA5Q-series Fairchild Power Switch (FPSTM)
Abstract
In general, a Quasi-Resonant Converter (QRC) shows lower
EMI and higher power conversion efficiency compared to
the conventional hard switched converter with a fixed
switching frequency. Therefore, it is well suited for color TV
applications that are noise sensitive. This application note
presents practical design considerations of Quasi-Resonant
Converters for color TV applications employing KA5Qseries FPSTM (Fairchild Power Switch). It includes
designing the transformer, output filter and sync network,
selecting the components and closing the feedback loop. The
step-by-step design procedure described in this application
note will help engineers design quasi-resonant converter
easily.
DR(n)
LP(n)
VO(n)
NS(n)
CO(n)
Np
DR1
CP(n)
LP1
VO1 (B+)
NS1
AC
IN
CO1
KA5Q-series
Sync
CP1
Drain
PWM
LP2
DR2
Cr
VO2 (Sound)
GND
NS2
VFB
CB
Vcc
Ra
Ca
Da
DSY
CP2
CO2
Linear
regulator
Rd
RSY1
Rstr
CSY
MCU
Na
H11A817A
RSY2
KA431
R3
Rbias
R1
RF
CF
R2
R1
Q
Picture ON
Figure 1. Basic Quasi Resonant Converter Using KA5Q-series (Color TV Application)
1. Introduction
system reliability and productivity.
The KA5Q-series FPSTM (Fairchild Power Switch) is an
integrated Pulse Width Modulation (PWM) controller and a
Sense FET specifically designed for quasi-resonant off-line
Switch Mode Power Supplies (SMPS) with minimal external
components. Compared with a discrete MOSFET and PWM
controller solution, it can reduce total cost, component count,
size and weight while simultaneously increasing efficiency,
Figure 1 shows the basic schematic of a quasi-resonant
converter using KA5Q-series for the color TV application,
which also serves as the reference circuit for the design
process described in this paper. Vo1 is the output voltage that
powers horizontal deflection circuit while Vo2 is the output
voltage that supplies power to the Micro Controller Unit
(MCU) through a linear regulator.
Rev. 1.0.0
©2005 Fairchild Semiconductor Corporation
AN4149
APPLICATION NOTE
2. Step-by-step Design Procedure
1. Define the system specifications
(Vlinemin, Vlinemax, fL , Po , Eff )
In this section, a design procedure is presented using the
schematic of Figure 1 as a reference. Figure 2 illustrates the
design flow chart. The detailed design procedures are as
follows:
[STEP-1] Define the system specifications
2. Determine DC link capacitor (CDC)
and DC link voltage range
- Line voltage range (Vlinemin and Vlinemax).
- Line frequency (fL).
3. Determine the reflected output voltage
(VRO)
- Maximum output power (Po).
- Estimated efficiency (Eff) : The power conversion
efficiency must be estimated to calculate the maximum input
power. If no reference data is available, set Eff = 0.7~0.75 for
low voltage output applications and Eff = 0.8~0.85 for high
voltage output applications. In the case of Color TV
applications, the typical efficiency is 80~83%.
4. Determine the transformer primary side
inductance (Lm)
5. Choose proper FPS considering input
power and Idspeak
6. Determine the proper core and the
minimum primary turns (Npmin)
With the estimated efficiency, the maximum input power is
given by
P
P in = ------oE ff
7. Determine the number of turns for each
output
For multiple output SMPS, the load occupying factor for
each output is defined as
8. Determine the startup resistor
Po ( n )
K L ( n ) = -----------Po
9. Determine the wire diameter for each
winding
Is the winding window
area (Aw) enough ?
(1)
Y
(2)
where Po(n) is the maximum output power for the n-th
output. For single output SMPS, KL(1)=1. It is assumed that
Vo1 is the reference output that is regulated by the feedback
control in normal operation.
N
Y
Is it possible to change the core ?
[STEP-2] Determine DC link capacitor (CDC) and the
DC link voltage range.
N
10. Choose the secondary side rectifier diodes
It is typical to select the DC link capacitor as 2-3uF per watt
of input power for universal input range (85-265Vrms) and
1uF per watt of input power for European input range (195V265Vrms). With the DC link capacitor chosen, the minimum
DC link voltage is obtained as
11. Determine the output capacitors
V DC
min
=
2 ⋅ ( V line
12. Design the synchronization network
13. Design the voltage drop circuit for burst
operation
P in ⋅ ( 1 – D ch )
) – -----------------------------------C DC ⋅ f L
min 2
(3)
where CDC is the DC link capacitor and Dch is the duty cycle
ratio for CDC to be charged as defined in Figure 3, which is
typically about 0.2. Pin, Vlinemin and fL are specified in
STEP-1.
14. Design the feedback control circuit
The maximum DC link voltage is given as
Design finished
Figure 2. Flow Chart of Design Procedure
2
V DC
max
=
2V line
max
(4)
where Vlinemax is specified in STEP-1.
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
[STEP-4] Determine the transformer primary side
inductance (Lm)
Figure 5 shows the typical waveforms of MOSFET drain
current, secondary diode current and the MOSFET drain
voltage of a Quasi Resonant Converter. During TOFF, the
current flows through the secondary side rectifier diode and
the MOSFET drain voltage is clamped at (VDC+VRO). When
the secondary side current reduces to zero, the drain voltage
begins to drop by the resonance between the effective output
capacitor of the MOSFET and the primary side inductance
(Lm). In order to minimize the switching loss, the KA5Qseries is designed to turn on the MOSFET when the drain
voltage reaches its minimum voltage (VDC -VRO).
Minimum DC link voltage
DC link voltage
T1
Dch = T1 / T2
= 0.2
T2
Figure 3. DC Link Voltage Waveform
[STEP-3] Determine the reflected output voltage (VRO)
Figure 4 shows the typical waveforms of the drain voltage of
quasi-resonant flyback converter. When the MOSFET is
turned off, the DC link voltage (VDC) together with the
output voltage reflected to the primary (VRO) are imposed on
the MOSFET. The maximum nominal voltage across the
MOSFET (Vdsnom) is
V ds
nom
= V DC
max
+ V RO
Ids
ID
(5)
where VDCmax is as specified in equation (4). By increasing
VRO, the capacitive switching loss and conduction loss of the
MOSFET are reduced. However, this increases the voltage
stress on the MOSFET as shown in Figure 4. Therefore,
determine VRO by a trade-off between the voltage margin of
the MOSFET and the efficiency. Typically, VRO is set as
120~180V so that Vdsnorm is 490~550V (75~85% of
MOSFET rated voltage).
V ds
V DC +V RO
V RO
V RO
V DC
V DC -V RO
T ON
-
+
+
VDC
Lm
-
FPS
Drain
GND
+
Cr
To determine the primary side inductance (Lm), the
following variables should be determined beforehand :
+
Vds
-
VRO
VRO
Vdsnom
VDC max
VRO
Vdsnom
VRO
0V
Figure 4. The Typical Waveform of MOSFET Drain
Voltage for Quasi Resonant Converter
©2005 Fairchild Semiconductor Corporation
TF
Figure 5. Typical Waveforms of Quasi-Resonant
Converter
VO
VRO
-
T OFF
TS
• The minimum switching frequency (fsmin) : The
minimum switching frequency occurs at the minimum
input voltage and full load condition and should be higher
than the minimum switching frequency of FPS (20kHz).
By increasing fsmin, the transformer size can be reduced.
However, this results in increased switching losses.
Therefore, determine fsmin by a trade-off between
switching losses and transformer size. It is typical to set
fsmin to be around 25kHz.
• The falling time of the MOSFET drain voltage (TF) :
As shown in Figure 5, the MOSFET drain voltage fall
time is half of the resonant period of the MOSFET’s
effective output capacitance and primary side inductance.
By increasing TF, EMI can be reduced. However, this
forces an increase of the resonant capacitor (Cr) resulting
in increased switching losses. The typical value for TF is
2-2.5us.
3
AN4149
APPLICATION NOTE
After determining fsmin and TF, the maximum duty cycle is
calculated as
V RO
min
D max = ------------------------------------⋅ ( 1 – fs
× TF )
min
V RO + V DC
(6)
where VDCmin is specified in equation (3) and VRO is
determined in STEP-3.
Then, the primary side inductance is obtained as
min
Lm
2
( V DC
⋅ D max )
= --------------------------------------------min
2 ⋅ fs
⋅ P in
(7)
where Pin, VDCmin and Dmax are specified in equations (1),
(3), and (6), respectively and fsmin is the minimum switching
frequency.
Once Lm is determined, the maximum peak current and RMS
current of the MOSFET in normal operation are obtained as
min
I ds
peak
I ds
rms
V DC
D max
= ----------------------------------min
Lm fs
=
(8)
D max
peak
-------------- ⋅ I ds
3
(9)
where VDCmin, Dmax and Lm are specified in equations (3),
(6) and (7), respectively and fsmin is the minimum switching
frequency.
[STEP-5] Choose the proper FPS considering input
power and peak drain current.
With the resulting maximum peak drain current of the
MOSFET (Idspeak) from equation (8), choose the proper FPS
whose pulse-by-pulse current limit level (ILIM) is higher than
Idspeak. Since FPS has ± 12% tolerance of ILIM, there should
be some margin for ILIM when choosing the proper FPS
device. Table 1 shows the lineups of KA5Q-series with rated
output power and pulse-by-pulse current limit.
Maximum Output Power
PRODUCT
230Vac
±15%
85~
265Vac
KA5Q0740RT 90 W (85~170Vac)
KA5Q0565RT
ILIM
Min
Typ
Max
4.4A
5A
5.6A
75 W
60 W
3.08A
3.5A
3.92A
KA5Q0765RT 100 W
85 W
4.4A
5A
5.6A
KA5Q1265RT 150 W
120 W
5.28A
6A
6.72A
KA5Q1265RF 210 W
170 W
7.04A
8A
8.96A
KA5Q1565RF 250 W
210 W
10.12A 11.5A 12.88A
[STEP-6] Determine the proper core and the minimum
primary turns.
Table 2 shows the commonly used cores for C-TV
application for different output powers. When designing the
transformer, consider the maximum flux density swing in
normal operation (∆B) as well as the maximum flux density
in transient (Bmax). The the maximum flux density swing in
normal operation is related to the hysteresis loss in the core
while the maximum flux density in transient is related to the
core saturation.
With the chosen core, the minimum number of turns for the
transformer primary side to avoid the over temperature in the
core is given by
peak
NP
min
L m I ds
6
= -------------------------- × 10
∆ BA e
(10)
where Lm is specified in equation (7), Idspeak is the peak
drain current specified in equation (8), Ae is the crosssectional area of the transformer core in mm2 as shown in
Figure 6 and ∆B is the maximum flux density swing in tesla.
If there is no reference data, use ∆B =0.25~0.30 T.
Since the MOSFET drain current exceeds Idspeak and reaches
ILIM in a transient or fault condition, the transformer should
be designed not to be saturated when the MOSFET drain
current reaches ILIM . Therefore, the maximum flux density
(Bmax) when drain current reaches ILIM should be also
considered as
NP
min
L m I LIM
6
= -------------------- × 10
B max A e
(11)
where Lm is specified in equation (7), ILM is the pulse-bypulse current limit, Ae is the cross-sectional area of the core
in mm2 as shown in Figure 6 and Bmax is the maximum flux
density in tesla. Figure 7 shows the typical characteristics of
ferrite core from TDK (PC40). Since the core is saturated at
low flux density as the temperature goes high, consider the
high temperature characteristics. If there is no reference data,
use Bmax =0.35~0.4 T.
The primary turns should be determined as less than Npmin
values obtained from equation (10) and (11).
Aw
(mm2)
Table 1. FPS Lineups with Rated Output Power
Ae
(mm2)
Figure 6. Window Area and Cross Sectional Area
4
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
where n is obtained in equation (12) and Np and Ns1 are the
number of turns for the primary side and the reference
output, respectively.
M agnetization Curves (typical)
M aterial :PC40
25 ℃
The number of turns for the other output (n-th output) is
determined as
500
60 ℃
Flux density B (mT)
Vo ( n ) + VF ( n )
N s ( n ) = --------------------------------⋅ N s1
V o1 + V F1
100 ℃
400
( 14 )
where Vo(n) is the output voltage and VF(n) is the diode
(DR(n)) forward voltage drop of the n-th output.
300
200
NS(n)
+ VF(n) DR(n)
+
VO(n)
100
-
0
0
800
M agnetic field H (A/m)
1600
Np
NS2
-
Figure 7. Typical B-H Characteristics of Ferrite Core
(TDK/PC40)
+ VF2 DR2 VO2
+
VRO
-
+
Output Power
Core
70-100W
EER35
100-150W
EER40
EER42
150-200W
EER49
Ra
Vcc
+
- VFa + N
a
Linear
Regulator
NS1
+ VF1 -
Da
DR1
+
VO1
-
Table 2. Commonly Used Cores for C-TV Applications
Figure 8. Simplified Diagram of the Transformer
[STEP-7] Determine the number of turns for each output
Figure 8 shows the simplified diagram of the transformer. It
is assumed that Vo1 is the reference output which is regulated
by the feedback control in normal operation. It is also
assumed that the linear regulator is connected to Vo2 to supply a stable voltage for MCU.
First, calculate the turns ratio (n) between the primary
winding and reference output (Vo1) winding as a reference
V R0
n = ------------------------V o1 + V F1
- Vcc winding design : KA5Q-series drops all the outputs
including the Vcc voltage in standby mode in order to
minimize the power consumption. Once KA5Q-series enters
into standby mode, Vcc voltage is hysteresis controlled
between 11V and 12V as shown in Figure 9. The sync
threshold voltage is also reduced from 2.6V to 1.3V in burst
mode. Therefore, design the Vcc voltage to be around 24V in
normal operation for proper quasi-resonant switching in
standby mode as can be observed by
(12)
where VRO is determined in STEP-3 and Vo1 is the reference
output voltage and VF1 is the forward voltage drop of diode
(DR1).
( 11 + 12 ) ⁄ 2- 1.3
------------------------------≅ -------24
2.6
(15)
Then, determine the proper integer for Ns1 so that the
resulting Np is larger than Npmin as
N p = n ⋅ N s1 > N p
©2005 Fairchild Semiconductor Corporation
min
(13)
5
AN4149
APPLICATION NOTE
Vcc
C DC
12V
11V
Normal mode
Standby mode
AC line
Vsync
I sup
R str
Ra
Vcc
Da
KA5Q-series
4.6V
2.6V
Ca
3.6V
1.3V
Figure 9. Burst operation in standby mode
In general, switched mode power supply employs an error
amplifier and an opto-coupler to regulate the output voltage.
However, Primary Side Regulation (PSR) can be used for a
low cost design if output regulation requirements are not
very tight. PSR scheme regulates the output voltage
indirectly by controlling the Vcc voltage without an optocoupler. KA5Q-series has an internal error amplifier with a
fixed reference voltage of 32.5V for PSR applications. If
PSR is used, set Vcc to 32.5V.
After determining Vcc voltage in normal operation, the
number of turns for the Vcc auxiliary winding (Na) is
obtained as
V cc + V Fa
- ⋅ N s1
N a = ------------------------V o1 + V F1
( turns )
( 16 )
where VFa is the forward voltage drop of Da as defined in
Figure 8.
[STEP-8] Determine the startup resistor
Figure 10 shows the typical startup circuit for KA5Q-series.
Because some protections are implemented as latch mode,
AC startup is typically used to provide a fast reset. Initially,
FPS consumes only startup current (max 200uA) before it
begins switching. Therefore, the current supplied through the
startup resistor (Rstr) can charge the capacitors Ca1 and Ca2
while supplying startup current to FPS. When Vcc reaches a
start voltage of 15V (VSTART), FPS begins switching, and the
current consumed by FPS increases. Then, the current
required by FPS is supplied from the transformer’s auxiliary
winding.
6
Figure. 10 Startup Resistor and Vcc Auxiliary Circuit
- Startup resistor (Rstr) : The average of the minimum
current supplied through the startup resistor is given by
I sup
avg
min
⎛ 2⋅V
⎞
V
line
start
1
⎜
= ------------------------------------- – -----------------⎟ ⋅ -----------⎜
π
2 ⎟ R
str
⎝
⎠
( 17 )
where Vlinemin is the minimum input voltage, Vstart is the
start voltage (15V) of FPS and Rstr is the startup resistor. The
startup resistor should be chosen so that Isupavg is larger than
the maximum startup current (200uA). If not, Vcc can not be
charged up to the start voltage and FPS will fail to start up.
The maximum startup time is determined as
T str
max
V start
= C a ⋅ -------------------------------------------------avg
max
( I sup
– I start
)
( 18 )
Where Ca is the Vcc capacitor and Istartmax is the maximum
startup current (200uA) of FPS.
Once the startup resistor (Rstr) is determined, the maximum
approximate power dissipation in Rstr is obtained as
max⎞ 2
2
max⎞
⎛ ⎛V
+V
⋅V
2 2⋅V
⎜ ⎝ line
⎟
⎠
start
1
start line
P
= ------------ ⋅ ⎜ ---------------------------------------------------------------- – -----------------------------------------------------------------⎟
str R str ⎜
π
2
⎟
⎝
⎠
( 19 )
where Vlinemax is the maximum input voltage, which is
specified in STEP-1. The startup resistor should have a
proper dissipation rating based on the value of Pstr.
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
[STEP-9] Determine the wire diameter for each
winding based on the RMS current of each output.
voltage and current margins for the rectifier diode are as
follows
V RRM > 1.3 ⋅ V D ( n )
The RMS current of the n-th secondary winding is obtained
as
I sec ( n )
rms
= I ds
V RO ⋅ K L ( n )
1 – D max
----------------------- ⋅ -------------------------------------( Vo ( n ) + VF ( n ) )
D max
rms
( 20 )
where Dmax and Idsrms are specified in equations (6) and (9),
Vo(n) is the output voltage of the n-th output, VF(n) is the
diode (DR(n)) forward voltage drop, VRO is specified in
STEP-3 and KL(n) is the load occupying factor for n-th
output defined in equation (2).
The current density is typically 5A/mm2 when the wire is
long (>1m). When the wire is short with a small number of
turns, a current density of 6-10 A/mm2 is also acceptable. Do
not use wire with a diameter larger than 1 mm to avoid
severe eddy current losses as well as to make winding easier.
For high current output, it is recommended using parallel
windings with multiple strands of thinner wire to minimize
skin effect.
Check if the winding window area of the core, Aw (refer to
Figure 6) is enough to accommodate the wires. The required
winding window area (Awr) is given by
A wr = A c ⁄ K F
(21)
where Ac is the actual conductor area and KF is the fill factor.
Typically the fill factor is 0.2~0.25 for single output
applications and 0.15~0.2 for multiple output applications.
If the required window (Awr) is larger than the actual window
area (Aw), go back to the STEP-6 and change the core to a
bigger one. Sometimes it is impossible to change the core
due to cost or size constraints. In that case, reduce VRO in
STEP-3 or increase fsmin, which reduces the primary side
inductance (Lm) and the minimum number of turns for the
primary (Npmin) as can be seen in equation (7) and (10).
[STEP-10] Choose the proper rectifier diodes in the
secondary side based on the voltage and current ratings.
The maximum reverse voltage and the rms current of the
rectifier diode (DR(n)) of the n-th output are obtained as
max
V DC
⋅ ( Vo ( n ) + VF ( n ) )
V D ( n ) = V o ( n ) + --------------------------------------------------------------V RO
( 22 )
V RO K L ( n )
1 – D max
----------------------- ⋅ -------------------------------------( Vo ( n ) + VF ( n ) )
D max
( 23 )
ID ( n )
rms
= I ds
rms
I F > 1.5 ⋅ I D ( n )
(24)
rms
(25)
where VRRM is the maximum reverse voltage and IF is the
average forward current of the diode.
A quick selection guide for the Fairchild Semiconductor
rectifier diodes is given in Table 3. In this table, trr is the
maximum reverse recovery time.
Ultra Fast Recovery Diode
Products
VRRM
IF
trr
Package
EGP10B
100 V
1A
50 ns
DO-41
UF4002
100 V
1A
50 ns
DO-41
EGP20B
100 V
2A
50 ns
DO-15
EGP30B
100 V
3A
50 ns
DO-210AD
FES16BT
100 V
16 A
35 ns
TO-220AC
EGP10C
150 V
1A
50 ns
DO-41
EGP20C
150 V
2A
50 ns
DO-15
EGP30C
150 V
3A
50 ns
DO-210AD
FES16CT
150 V
16 A
35 ns
TO-220AC
EGP10D
200 V
1A
50 ns
DO-41
UF4003
200 V
1A
50 ns
DO-41
EGP20D
200 V
2A
50 ns
DO-15
EGP30D
200 V
3A
50 ns
DO-210AD
FES16DT
200 V
16 A
35 ns
TO-220AC
EGP10F
300 V
1A
50 ns
DO-41
EGP20F
300 V
2A
50 ns
DO-15
EGP30F
300 V
3A
50 ns
DO-210AD
EGP10G
400 V
1A
50 ns
DO-41
UF4004
400 V
1A
50 ns
DO-41
EGP20G
400 V
2A
50 ns
DO-15
EGP30G
400 V
3A
50 ns
DO-210AD
UF4005
600 V
1A
75 ns
DO-41
EGP10J
600 V
1A
75 ns
DO-41
EGP20J
600 V
2A
75 ns
DO-15
EGP30J
600 V
3A
75 ns
DO-210AD
UF4006
800 V
1A
75 ns
TO-41
UF4007
1000 V
1A
75 ns
TO-41
Table 3. Fairchild Diode Quick Selection Table
max,
rms
where KL(n), VDC
Dmax and Ids
are specified in
equations (2), (4), (6) and (9), respectively, VRO is specified
in STEP-3, Vo(n) is the output voltage of the n-th output and
VF(n) is the diode (DR(n)) forward voltage drop. The typical
©2005 Fairchild Semiconductor Corporation
7
AN4149
APPLICATION NOTE
[STEP-11] Determine the output capacitors considering
the voltage and current ripple.
The ripple current of the n-th output capacitor (Co(n)) is
obtained as
Np
rms
( ID ( n )
=
+
rms 2
) – Io ( n )
2
Drain
(26)
where Io(n) is the load current of the n-th output and ID(n)rms
is specified in equation (23). The ripple current should be
smaller than the maximum ripple current specification of the
capacitor. The voltage ripple on the n-th output is given by
CO
Cr
Ids
4.6/2.6V
Sync
Vcc
D
I
peak
V R
K
( Vo ( n ) + VF ( n ) )
Na
Co (n ) fs
min
D SY
V sync
where Co(n) is the capacitance, Rc(n) is the effective series
resistance (ESR) of the n-th output capacitor, KL(n), Dmax and
Idspeak are specified in equations (2), (6) and (8) respectively,
VRO is specified in STEP-3, Io(n) and Vo(n) are the load
current and output voltage of the n-th output, respectively
and VF(n) is the diode (DR(n)) forward voltage drop.
Sometimes it is impossible to meet the ripple specification
with a single output capacitor due to the high ESR of the
electrolytic capacitor. In those cases, additional L-C filter
stages (post filter) can be used to reduce the ripple on the
output.
Da
Ca
o ( n ) max
ds
RO C ( n ) L ( n )
∆ V o ( n ) = -------------------------+ ---------------------------------------------------------- (27)
+
V ds
-
GND
R cc
I
V o1
Lm
Sync comparator
I cap ( n )
N s1
KA5Q-series
C SY
R SY1
R SY2
Figure. 11 Synchronization Circuit
The peak value of the sync signal is determined by the
voltage divider network RSY1 and RSY2 as
V sync
pk
R SY2
= ---------------------------------- ⋅ V cc
R SY1 + R SY2
( 28 )
[STEP-12] Design the synchronization network.
KA5Q-series employs a quasi resonant switching technique
to minimize the switching noise as well as switching loss. In
this technique, a capacitor (Cr) is added between the
MOSFET drain and source as shown in Figure 11. The basic
waveforms of a quasi-resonant converter are shown in Figure
12. The external capacitor lowers the rising slope of drain
voltage, which reduces the EMI caused by the MOSFET
turn-off. To minimize the MOSFET switching loss, the
MOSFET should be turned on when the drain voltage
reaches its minimum value as shown in Figure 12.
The optimum MOSFET turn-on time is indirectly detected
by monitoring the Vcc winding voltage as shown in Figure
11 and 12. The output of the sync detect comparator (CO)
becomes high when the sync voltage (Vsync) exceeds 4.6V
and low when the Vsync reduces below 2.6V. The MOSFET is
turned on at the falling edge of the sync detect comparator
output (CO).
Choose the voltage divider RSY1 and RSY2 so that the peak
value of sync voltage (Vsyncpk) is lower than the OVP
threshold voltage (12V) in order to avoid triggering OVP in
normal operation. Typically, Vsyncpk is set to 8~10V.
To synchronize the Vsync with the MOSFET drain voltage,
choose the sync capacitor (CSY) so that TF is same as TQ as
shown in Figure 12. TF and TQ are given, respectively, as
T F = π ⋅ L m ⋅ C eo
R SY2
V cc
T Q = R SY2 ⋅ C SY ⋅ ln ⎛ --------- ⋅ ----------------------------------⎞
⎝ 2.6 R SY1 + R SY2⎠
(29)
(30)
where Lm is the primary side inductance of the transformer,
Ns and Na are the number of turns for the output winding and
Vcc winding, respectively and Ceo is the effective MOSFET
output capacitance (Coss+Cr).
©2003 Fairchild Semiconductor Corporation
8
APPLICATION NOTE
AN4149
Assuming that both Vo1 and Vo2 drop to half of their normal
values, the maximum value of R3 for proper burst operation
is given by
Vds
VRO
( V 02 ⁄ 2 – 0.7 – 2.5 ) ⋅ R 1 ⋅ R 2
R 3 = -----------------------------------------------------------------------------2.5 ⋅ ( R 1 + R 2 ) – ( R 2 ⋅ V 01 ⁄ 2 )
VRO
VDC
(32)
TF
Vsync
VFB
Vovp (12V)
1V
Vsyncpk
Ids
4.6V
2.6V
Ibpk
TQ
CO
Vcc
MOSFET Gate
12V
ON
ON
11V
Figure. 12 Synchronization Waveforms
Normal Mode
Figure 13. Burst Operation Waveforms
[STEP-13] Design voltage drop circuit for the burst
operation.
To minimize the power consumption in the standby mode,
KA5Q-series employs burst operation. Once FPS enters into
burst mode, all the output voltages as well as effective
switching frequencies are reduced as shown in Figure 13.
Figure 14 shows the typical output voltage drop circuit for
C-TV applications. Under normal operation, the picture on
signal is applied and the transistor Q1 is turned on, which decouples R3 and D1 from the feedback network. Therefore,
only Vo1 is regulated by the feedback circuit in normal
operation and is determined as
V o1
R1 + R2
= 2.5 ⋅ ⎛ --------------------⎞
⎝ R2 ⎠
VO2
(31)
Linear
Regulator
VO1 (B+)
M icom
RD
Rbias
R1
CF
C
KA431
In standby mode, the picture on signal is disabled and the
transistor Q1 is turned off, which couples R3 and D1 to the
reference pin of KA431. If R3 is small enough to make the
reference pin voltage of KA431 higher than 2.5V, the current
through the opto LED pulls down the feedback voltage (VFB)
of FPS and forces FPS to stop switching. Once FPS stops
switching, Vcc decreases, and when Vcc reaches 11V, it
resumes switching with a predetermined peak drain current
until Vcc reaches 12V. When Vcc reaches 12V, the switching
operation is terminated again until Vcc reduces to 11V. In
this way, Vcc is hysteresis controlled between 11V and 12V
in the burst mode operation.
©2005 Fairchild Semiconductor Corporation
Standby Mode
A
RF
D1
R3
Q1
Picture ON
R
R2
Figure 14. Typical Feedback Circuit to Drop Output
Voltage in Standby Mode
[STEP-14] Design the feedback control circuit.
Since the KA5Q-series employs current mode control as
shown in Figure 15, the feedback loop can be easily
implemented with a one-pole and one-zero compensation
circuit. The current control factor of FPS, K is defined as
9
AN4149
APPLICATION NOTE
I pk
I LIM
K = --------- = ----------------V FB
V FBsat
(33)
where Ipk is the peak drain current and VFB is the feedback
voltage for a given operating condition, ILIM is the current
limit of the FPS and VFBsat is the internal feedback saturation
voltage, which is typically 2.5V.
In order to express the small signal AC transfer functions,
the small signal variations of feedback voltage (vFB) and
controlled output voltage (vo1) are introduced as vˆFB and vˆo1.
vo1
vbias
FPS
vFB
RB
CB
RD
ibias
Rbias
iD
CTR :1
CF
RF
R1
When the converter has more than one output, the low
frequency control-to-output transfer function is proportional
to the parallel combination of all load resistance, adjusted by
the square of the turns ratio. Therefore, the effective load
resistance is used in equation (34) instead of the actual load
resistance of Vo1. Notice that there is a right half plane
(RHP) zero (wrz) in the control-to-output transfer function of
equation (34). Because the RHP zero reduces the phase by
90 degrees, the crossover frequency should be placed below
the RHP zero.
The Figure 16 shows the variation of a quasi-resonant
flyback converter’s control-to-output transfer function for
different input voltages. This figure shows the system poles
and zeros together with the DC gain change for different
input voltages. The gain is highest at the high input voltage
condition and the RHP zero is lowest at the low input voltage
condition.
Figure 17 shows the variation of a quasi-resonant flyback
converter’s control-to-output transfer function for different
loads. This figure shows that the gain between fp and fz does
not change for different loads and the RHP zero is lowest at
the full load condition.
The feedback compensation network transfer function of
Figure 15 is obtained as
KA431
R2
ˆ
w i 1 + s ⁄ w zc
v FB
----- --------------------------------ˆ - = - s ⋅ 1 + s ⁄ w pc
v o1
Ipk
( 35 )
R B ⋅ CTR
1
1
where w i = ------------------------ , w zc = --------------- , w pc = --------------R1 RD CF
RF CF
RB CB
MOSFET
current
Figure 15. Control Block Diagram
For quasi-resonant flyback converters, the control-to-output
transfer function using current mode control is given by
vˆ o1
G vc = -------vˆ
and RB is the internal feedback bias resistor of FPS, which is
typically 2.8kΩ, CTR is the current transfer ratio of opto
coupler and R1, RD, RF, CF and CB are shown in Figure 15.
40 dB
FB
K ⋅ R L V DC ( N p ⁄ N s1 ) ( 1 + s ⁄ w z ) ( 1 – s ⁄ w rz )
= ----------------------------------------------------- ⋅ ---------------------------------------------------------1 + s ⁄ wp
2 ( 2V RO + v DC )
fp
( 34 )
where VDC is the DC input voltage, RL is the effective total
load resistance of the controlled output, which is defined as
Vo12/Po. Additionally, Np and Ns1 are specified in STEP-7,
VRO is specified in STEP-3, Vo1 is the reference output
voltage, Po is specified in STEP-1 and K is specified in
equation (33). The pole and zeros of equation (34) are
defined as
20 dB
fp
Low input voltage
2
fz
-20 dB
frz
fz
frz
-40 dB
1Hz
RL ( 1 – D )
1
(1 + D)
w z = -------------------- , w rz = ---------------------------------------- and w p = ------------------2
R c1 C o1
R L C o1
DL m ( N s1 ⁄ N p )
High input voltage
0dB
10Hz
100Hz
1kHz
10kHz
100kHz
Figure 16. QR Flyback Converter Control-to Output
Transfer Function Variation for Different Input Voltages
where Lm is specified in equation (7), D is the duty cycle of
the FPS, Co1 is the output capacitor of Vo1 and RC1 is the
ESR of Co1.
10
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
When determining the feedback circuit component, there are
some restrictions as described below:
40 dB
fp
(a) Design the voltage divider network of R1 and R2 to
provide 2.5V to the reference pin of the KA431. The
relationship between R1 and R2 is given as
Light load
20 dB
fp
2.5 ⋅ R 1
R 2 = -----------------------V o1 – 2.5
0dB
Heavy load
-20 dB
frz
frz
fz
-40 dB
1Hz
10Hz
100Hz
1kHz
10kHz
100kHz
where Vo1 is the reference output voltage.
(b) The capacitor connected to feedback pin (CB) is related
to the shutdown delay time in an overload condition by
Figure 17. QR Flyback Converter Control-to Output
Transfer Function Variation for Different Loads
When the input voltage and the load current vary over a wide
range, determining the worst case for the feedback loop
design is difficult. The gain together with zeros and poles
varies according to the operating conditions.
One simple and practical solution to this problem is
designing the feedback loop for low input voltage and full
load condition with enough phase and gain margin. The RHP
zero is lowest at low input voltage and full load condition.
The gain increases only about 6dB as the operating condition
is changed from the lowest input voltage to the highest input
voltage condition under universal input condition.
The procedure to design the feedback loop is as follows
(a) Set the crossover frequency (fc) below 1/3 of RHP zero to
minimize the effect of the RHP zero. Set the crossover
frequency below half of the minimum switching frequency
(fsmin).
(36)
T delay = ( V SD – 2.5 ) ⋅ C B ⁄ I delay
(37)
where VSD is the shutdown feedback voltage and Idelay is the
shutdown delay current. Typical values for VSD and Idelay
are 7.5V and 5uA, respectively. In general, a delay of 20 ~
50 ms is typical for most applications. Because CB also
determines the high frequency pole (wpc) of the compensator
transfer function as shown in equation (35), too large a CB
can limit the control bandwidth by placing wpc at too low a
frequency. Typical value for CB is 10-50nF. Application
circuit to extend the shutdown time without limiting the
control bandwidth is shown in Figure 19. By setting the
zener breakdown voltage (Vz) slightly higher than 2.7V, the
additional delay capacitor (Cz) is de-coupled from the
feedback circuit in normal operation. When the feedback
voltage exceeds the zener breakdown voltage (Vz), Cz and
CB determine the shutdown time.
(b) Determine the DC gain of the compensator (wi/wzc) to
cancel the control-to-output gain at fc.
FPS
(c) Place a compensator zero (fzc) around fc/3.
IFB
(d) Place a compensator pole (fpc) around 3fc.
Idelay
vFB
CB
Loop gain T
Cz
40 dB
Vz
fzc
20 dB
Compensator
fpc
fp
0 dB
Control to output
fc
V SD
frz
-20 dB
VZ
2.7V
fz
-40 dB
1Hz
10Hz
100Hz
1kHz
10kHz
Figure 18. Compensator Design
100kHz
T delay
Figure 19. Delayed Shutdown
©2005 Fairchild Semiconductor Corporation
11
AN4149
APPLICATION NOTE
(c) The resistors Rbias and RD used together with the optocoupler H11A817A and the shunt regulator KA431 should
be designed to provide proper operating current for the
KA431 and to guarantee the full swing of the feedback
voltage for the FPS device chosen. In general, the minimum
values of cathode voltage and current for the KA431 are
2.5V and 1mA, respectively. Therefore, Rbias and RD should
be designed to satisfy the following conditions:
V bias – V OP – 2.5
--------------------------------------------- > I FB
RD
V OP
------------- > 1mA
R bias
( 38 )
(39)
where Vbias is the KA431 bias voltage as shown in Figure 16
and VOP is opto-diode forward voltage drop, which is
typically 1V. IFB is the feedback current of FPS, which is
typically 1mA.
12
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
Design Example I (KA5Q0765RT)
Application
Device
Input Voltage
Output Power
Output Voltage
(Rated Current)
Color TV
KA5Q0765RT
85-265Vac
82W
125V (0.4A)
(60Hz)
20V (0.5A)
16V (1.0A)
12V (0.5A)
Schematic
D201
EGP20D
T1
EER3540
RT101
5D-9
C102
220uF
400V
R103
68kΩ
0.5W
BD101
10
1
3
11
4
13
L101
BEAD
R104
68kΩ
0.5W
D105
1N4937
1
Drain
3 Vcc IC101 SYNC 5
KA5Q0765RT
GND
2
C104
47uF
50V
FB
4
C109
47nF
50V
C107
1nF
1kV
ZD101
4.7V
0.5W
C103
100nF
50V
12
6
D106 R106 D103 R107
1N4148 680Ω 1N4937 5.1Ω
0.25W
0.25W
R105
470Ω
0.25W
14
15
16
C105
3.9nF
50V
C206
470pF
1kV
17
7
PC301
817A
©2005 Fairchild Semiconductor Corporation
12V, 0.5A
L203
C208 BEAD
1000uF
35V
L202
C214 BEAD
100uF
160V
125V, 0.4A
C215
47uF
160V
D202
EGP20D
18
F101
FUSE
250V
3.0A
C207
470pF
1kV
20V, 0.5A
L204
C210 BEAD
1000uF
35V
D203
EGP20J
LF101
C101
330nF
275VAC
C212
470pF
1kV
D205
EGP20D
C205
470pF
1kV
VR201
30kΩ
R201
1kΩ
0.25W
R203
1kΩ R204
0.25W 39kΩ
0.25W
C108
2.2nF
16V, 1A
L201
C202 BEAD
1000uF
35V
C203
22nF
50V
R206
220kΩ
0.25W
VR202
30kΩ
D201
Q201
KA431
R205
4.7kΩ
0.25W
Q202
KSC945
SW 201
R207
5.1kΩ
0.25W
R208
5.1kΩ
0.25W
13
AN4149
APPLICATION NOTE
Transformer Specifications
EER 3540
N p1 1
18
2
17
3
16
Na
N p2
N20V
N125V/2
15 N
1 2 5V/2
4
Na
N 16 V
Np2
5
14
6
13
7
12
N125V/2
8
11
Np1
9
10
N 12 5 V /2
N12V
N 12 V
N16V
N 20 V
Transformer Schematic Diagram
Winding Specifications
No
Pin (s→f)
Wire
φ
0.6 × 1
Turns
Winding Method
35
Center Winding
Np1
1-3
N125V/2
16 - 15
0.6 × 1
28
Center Winding
N16V
18 - 17
0.4φ
×2
8
Center Winding
N12V
12 - 13
0.5 × 1
6
Center Winding
Np2
3-4
0.6 × 1
35
Center Winding
N125V/2
15 - 14
0.5φ
×1
28
Center Winding
N20V
11 - 10
0.5 × 1
10
Center Winding
Na
7-6
11
Center Winding
φ
φ
φ
φ
φ
0.3 × 1
Electrical Characteristics
Inductance
Leakage Inductance
Pin
Specification
1-4
565uH ± 5%
1-4
10uH Max
Remarks
1kHz, 1V
2
nd
all short
Core & Bobbin
Core : EER 3540
Bobbin : EER3540
Ae : 109 mm2
14
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
Design Example II (KA5Q1265RF)
Application
Device
Input Voltage
Output Power
Output Voltage
(Rated Current)
Color TV
KA5Q1265RF
85-265Vac
154W
125V (0.8A)
(60Hz)
20V (0.5A)
16V (2.0A)
12V (1.0A)
Schematic
D201
EGP20D
T1
EER4242
RT101
10D-9
10
1
3
C102
470uF
400V
R103
68kΩ
0.5W
BD101
11
L101
BEAD
R104
68kΩ
0.5W
4
3 Vcc IC101 SYNC 5
KA5Q1265RF
GND
2
C104
47uF
50V
FB
4
C109
47nF
50V
ZD101
4.7V
0.5W
C103
100nF
50V
13
C107
1.5nF
1kV
D105
1N4937
1
Drain
12
6
D106 R106 D103 R107
1N4148 680Ω 1N4937 5.1Ω
0.25W
0.25W
R105
470Ω
0.25W
14
15
16
C105
2.7nF
50V
17
7
PC301
817A
©2005 Fairchild Semiconductor Corporation
C206
470pF
1kV
L202
C214 BEAD
220uF
200V
125V, 0.8A
C215
100uF
200V
D202
EGP30D
18
F101
FUSE
250V
5.0A
C207
470pF
1kV
12V, 1A
L203
C208 BEAD
2200uF
35V
D203
EGP30J
LF101
C101
330nF
275VAC
C212
470pF
1kV
D205
EGP20D
20V, 0.5A
L204
C210 BEAD
1000uF
35V
C205
470pF
1kV
VR201
30kΩ
R201
1kΩ
0.25W
R203
1kΩ R204
0.25W 39kΩ
0.25W
C108
2.2nF
16V, 2A
L201
C202 BEAD
2200uF
35V
C203
22nF
50V
R206
220kΩ
0.25W
VR202
30kΩ
D201
Q201
KA431
R205
4.7kΩ
0.25W
Q202
KSC945
SW201
R207
5.1kΩ
0.25W
R208
5.1kΩ
0.25W
15
AN4149
APPLICATION NOTE
Transformer Specifications
EER4242
18
N p1 1
Na
17 N
2
N p2
Na
N 20V
16V
3
16
4
15 N
125V/2
N p2
5
14
N 12V
6
13
7
12
8
11
9
10
N 125V/2
N 125V /2
N 16V
N 12 V
N 125V/2
N p1
N 20 V
Transformer Schematic Diagram
Winding Specifications
No
Pin (s→f)
Wire
φ
0.5 × 2
Turns
Winding Method
22
Center Winding
Np1
1-3
N125V/2
16 - 15
0.5 × 2
18
Center Winding
N16V
18 - 17
0.5φ
×2
5
Center Winding
N12V
12 - 13
0.4 × 2
4
Center Winding
Np2
3-4
0.5 × 2
22
Center Winding
N125V/2
15 - 14
0.5φ
×2
18
Center Winding
N20V
11 - 10
0.5 × 1
6
Center Winding
Na
7-6
7
Center Winding
φ
φ
φ
φ
φ
0.3 × 1
Electrical Characteristics
Inductance
Leakage Inductance
Pin
Specification
1-4
385uH ± 5%
1-4
10uH Max
Remarks
1kHz, 1V
2
nd
all short
Core & Bobbin
Core : EER 4242
Bobbin : EER4242
Ae : 234 mm2
16
©2005 Fairchild Semiconductor Corporation
APPLICATION NOTE
AN4149
Design Example III (KA5Q1565RF)
Application
Device
Input Voltage
Output Power
Output Voltage
(Rated Current)
Color TV
KA5Q1565RF
85-265Vac
217W
125V (1.0A)
(60Hz)
20V (1.0A)
16V (3.0A)
12V (2.0A)
Schematic
D201
EGP20D
T1
EER5345
RT101
10D-9
10
1
3
C102
470uF
400V
R103
68kΩ
0.5W
BD101
11
4
Drain
3 Vcc IC101 SYNC 5
KA5Q1565RF
GND
2
C104
47uF
50V
FB
4
C109
47nF
50V
ZD101
4.7V
0.5W
C103
100nF
50V
13
C107
2nF
1kV
D105
1N4937
1
12
6
D106 R106 D103 R107
1N4148 680Ω 1N4937 5.1Ω
0.25W
0.25W
R105
470Ω
0.25W
14
15
16
C105
2.7nF
50V
17
7
PC301
817A
©2005 Fairchild Semiconductor Corporation
C206
470pF
1kV
L202
C214 BEAD
330uF
200V
125V, 1A
C215
220uF
200V
D202
FFPF05U20S
18
F101
FUSE
250V
5.0A
C207
470pF
1kV
12V, 2A
L203
C208 BEAD
2200uF
35V
D203
FFPF05U60S
LF101
C101
330nF
275VAC
20V, 1A
L204
C210 BEAD
1000uF
35V
D205
EGP30D
L101
BEAD
R104
68kΩ
0.5W
C212
470pF
1kV
C205
470pF
1kV
VR201
30kΩ
R201
1kΩ
0.25W
R203
1kΩ R204
0.25W 39kΩ
0.25W
C108
2.2nF
16V, 3A
L201
C202 BEAD
2200uF
35V
C203
22nF
50V
R206
220kΩ
0.25W
VR202
30kΩ
D201
Q201
KA431
R205
4.7kΩ
0.25W
Q202
KSC945
SW 201
R207
5.1kΩ
0.25W
R208
5.1kΩ
0.25W
17
AN4149
APPLICATION NOTE
Transformer Specifications
EER5345
Np1 1
18
2
17
3
16
4
15
5
14
6
13
7
12
N p2
Na
N20V
N16V
N125V/2
Np2
N125V/2
N12V
N125V /2
N16V
Na
N12 V
N125V/2
Np1
8
11
9
10
N20 V
Transformer Schematic Diagram
Winding Specifications
No
Pin (s→f)
Wire
φ
0.6 × 2
Turns
Winding Method
21
Center Winding
Np1
1-3
N125V/2
16 - 15
0.6 × 2
17
Center Winding
N16V
18 - 17
0.6φ
×3
5
Center Winding
N12V
12 - 13
0.6 × 2
4
Center Winding
Np2
3-4
0.6 × 2
21
Center Winding
N125V/2
15 - 14
0.6φ
×2
17
Center Winding
N20V
11 - 10
0.5 × 1
6
Center Winding
Na
7-6
7
Center Winding
φ
φ
φ
φ
φ
0.3 × 1
Electrical Characteristics
Inductance
Leakage Inductance
Pin
Specification
1-4
325uH ± 5%
1-4
10uH Max
Remarks
1kHz, 1V
2
nd
all short
Core & Bobbin
Core : EER 5345
Bobbin : EER5345
Ae : 318 mm2
18
©2005 Fairchild Semiconductor Corporation
AN4149
APPLICATION NOTE
Hangseok Choi, Ph.D
Power Conversion Team / Fairchild Semiconductor
Phone : +82-32-680-1383 Facsimile : +82-32-680-1317
E-mail : hangseok.choi@fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPROATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/20/05 0.0m 002
© 2005 Fairchild Semiconductor Corporation