www.fairchildsemi.com AN-4159 Green Mode Fairchild Buck Switch FSL336LR Introduction This application note describes a detailed design method and procedure for a buck offline converter. Design consideration and formula are presented. The FSL336LR is designed for non-isolated topologies; such as buck, buckboost converter, and non-isolated flyback converter. This device is an integrated current-mode Pulse Width Modulation (PWM) controller and SenseFET. The integrated PWM controller includes: 10 V regulator for no external bias circuit, Under-Voltage Lockout (UVLO), Leading-Edge Blanking (LEB), optimized gate turn-on /turn-off driver, EMI attenuator, Thermal Shutdown (TSD), temperature-compensated precision current sources for optimized loop compensation, and fault-protection circuitry. Protections include: Overload Protection (OLP), OverVoltage Protection (OVP), and Feedback Open-Loop Protection (FB_OLP). FSL336LR offers stable soft-start performance during startup. The internal high-voltage startup switch and the Burst-Mode operation for extremely low operating current reduce the power loss in Standby Mode. As the result, this device is able to achieve power loss less than 25 mW with external bias and 120 mW without external bias at 230 VAC. When compared to a linear power supply, the FSL336LR reduces total size and weight; while increasing efficiency, productivity, and system reliability. Application of the FSL336LR is suitable for cost-effective platform designs. DVcc FSL336LR RA Vcomp VFB CF1 RF Bridge Rectifier ILIMIT CF2 Drain VCC Drain GND CVcc RPEAK RB L DF CDC DFB CFB COUT RDUMMY VO AC Line Figure 1. © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 Typical Application www.fairchildsemi.com AN-4159 APPLICATION NOTE Device Block Description Startup Circuit and Soft-Start Feedback Control During startup, an internal high-voltage current source (ICH) of the high-voltage regulator supplies the internal bias current (ISTART) and charges the external capacitor (CA) connected to the VCC pin, as illustrated in Figure 2. This internal high-voltage current source is enabled until VCC reaches 10 V. During steady-state operation, this internal high-voltage regulator (HVREG) maintains VCC with 10 V and provides operating current (IOP) for all internal circuits. Therefore, FSL336LR needs no external bias circuit. The high-voltage regulator is disabled when the external bias is higher than 10 V. The FSL336LR employs current-mode control with a transconductance amplifier for feedback control, as shown in Figure 4. Two resistors are typically used on the V FB pin to sense output voltage. An external compensation circuit is recommended on the VCOMP pin to control output voltage. A built-in transconductance amplifier accurately controls output voltage without external components, such as Zener diode and transistor. Drain VOUT VDC.link VBIAS Transconductance Amplifier VFB Greenmode Controller IPK 3R 4 VREF 6,7 OSC D1 D2 PWM LEB R Gate driver Drain VCOMP 6,7 VCC ICH CC1 CC2 10V HVREG 3 RC1 Figure 4. ISTART (during startup) Iop (during steady-state operation) CA RSENSE 5 Pulse-Width Modulation (PWM) Circuit Transconductance Amplifier (gm Amplifier) VBIAS Figure 2. UVLO The output of the transconductance amplifier sources and sinks the current to and from the compensation circuit connected on the VCOMP pin (see Figure 5). This compensated VCOMP pin voltage controls the switching duty cycle by comparing it with the voltage across the RSENSE. When the feedback pin voltage exceeds the internal reference voltage (VREF) of 2.5 V; the transconductance amplifier sinks the current from the compensation circuit, VCOMP is pulled down, and the duty cycle is reduced. This typically occurs when input voltage is increased or output load is decreased. A two-pole and one-zero compensation network is recommended for optimal output voltage control and AC dynamics. Startup Block The internal soft-start circuit slowly increases the SenseFET current after it starts. The typical soft-start time is 10 ms, as shown in Figure 3, where progressive increments of the SenseFET current are allowed during startup. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is gradually increased to smoothly establish the required output voltage. Soft-start also helps prevent transformer saturation and reduces the stress on the secondary diode. IEA [A] 1.25ms Sinking current 12µA at 2.525V +24µA -24µA ILIM Sourcing current 12µA at 2.475V Soft-Start Envelope 0.2ILIM GM [µmho] 960µmho Drain Current 8-Steps Figure 3. 480µmho t Soft-Start Function VFB 2.45V Figure 5. © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 VREF (2.5V) 2.55V VFB Characteristics of gm Amplifier www.fairchildsemi.com 2 AN-4159 APPLICATION NOTE Pulse-by-pulse Current Limit (40 ms) circuit determines whether it is a transient situation or a true overload situation (see Figure 6). The currentmode feedback path limits the maximum power current and, when the output consumes more than this maximum power, the output voltage (VO) decreases below its rated voltage. This reduces feedback pin voltage, which increases the output current of the internal transconductance amplifier. Eventually VCOMP is increased. When VCOMP reaches 3 V, the fixed OLP delay (40 ms) is activated. After this delay, switching operation is terminated, as shown in Figure 7. Because current-mode control is employed, the peak current flowing through the SenseFET is limited by the inverting input of PWM comparator, as shown in Figure 4. Assuming 50 µA current source flows only through the internal resistors (3R + R = 46 kΩ), the cathode voltage of diode D2 is about 2.4 V. Since D1 is blocked when VCOMP exceeds 2.4 V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current of the SenseFET is limited. OSC Leading-Edge Blanking (LEB) At the instant the internal SenseFET is turned on; primaryside capacitance and the secondary-side rectifier diode reverse recovery of the flyback application, the freewheeling diode reverse recovery, and other parasitic capacitance of the buck application typically cause a highcurrent spike through the SenseFET. Excessive voltage across the sensing resistor (RSENSE) leads to incorrect feedback operation in the current-mode control. To counter this effect, a Leading-Edge Blanking (LEB) circuit (see Figure 4) inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on. 3R LEB Q R Q Gate driver VCOMP RSENSE 40ms delay OLP VOLP Figure 6. Overload Protection Internal Circuit Vcc HVREG VSTART VSTOP Protection Functions The protective functions include Overload Protection (OLP), Over-Voltage Protection (OVP), Under-Voltage Lockout (UVLO), Feedback Open-Loop Protection (FB_OLP), and Thermal Shutdown (TSD). All of the protections operate in Auto-Restart Mode. Since these protection circuits are fully integrated in the IC without external components, reliability is improved without increasing cost and PCB space. If a fault condition occurs, switching is terminated and the SenseFET remains off. At the same time, internal protection timing control is activated to decrease power consumption and stress on passive and active components during auto restart. When internal protection timing control is activated, VCC is regulated with 10 V through the internal high-voltage regulator until switching is terminated. This internal protection timing control continues until restart time (650 ms) is counted. After counting to 650 ms, the internal high-voltage regulator is disabled and VCC is decreased. When VCC reaches the UVLO stop voltage, VSTOP (7 V); the protection is reset and the internal high-voltage current source charges the VCC capacitor via the drain pin. When VCC reaches the UVLO start voltage, VSTART (8 V); normal operation resumes. In this manner, auto restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. 20ms Ids Power on 40ms 650ms SS 40ms 650ms Normal with SS Overloading Overloading Overloading Disappear Overloading Disappear Figure 7. Overload Protection (OLP) Waveform Over-Voltage Protection (OVP) If any feedback loop components fail due to a soldering defect, VCOMP climbs up in manner similar to the overload situation, forcing the maximum current to be supplied to the SMPS until OLP is triggered. In this case, excessive energy is provided to the output and the output voltage may exceed the rated voltage before OLP is activated. To prevent this situation, an Over-Voltage Protection (OVP) circuit is employed. In general, output voltage can be monitored through VCC and, when VCC exceeds 24.5 V, OVP is triggered, resulting in switching termination. To avoid undesired activation of OVP during normal operation, V CC should be designed below 24.5 V (see Figure 8). OSC 3R Overload Protection (OLP) Overload is defined as the load current exceeding a set level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS operates normally, the OLP circuit can be enabled during the load transition or startup. To avoid this undesired operation, an internal fixed-delay © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 PWM R 5 OLP S PWM LEB R 2 VCC OVP S Q R Q Gate driver RSENSE OVP VOVP Figure 8. Over-Voltage Protection Circuit www.fairchildsemi.com 3 AN-4159 APPLICATION NOTE Feedback Open-Loop Protection (FB_OLP) In the event of a feedback loop failure, especially a shorted lower-side resistor of the feedback pin; not only does VCOMP rise in a similar manner to the overload situation, but V FB starts to drop to IC ground level. Although OLP and OVP also can protect the SMPS in this situation, FB_OLP can reduce stress on the SenseFET. If there is no FB_OLP, the output voltage is much higher than the rated voltage before OLP or OVP trigger. When VFB drops below 0.5 V, FB_OLP is activated, switching off. To avoid activation during startup, FB_OLP is disabled during soft-start. OSC 3R VOUT As output load condition is reduced, the switching loss becomes the largest power loss factor. FSL306LR uses the VCOMP pin voltage to monitor output load condition. As output load decreases, VCOMP decreases and switching frequency declines, as shown in Figure 11. Once VCOMP falls to 0.8 V, the switching frequency varies between 21 kHz and 23 kHz before Burst Mode operation. At Burst Mode operation, random frequency fluctuation still functions. FB_OLP S PWM LEB R RH Green Mode Operation R Random Frequency modulation range Switching frequency Q Gate driver Q VFB 53 kHz RSENSE 4 47 kHz FB_OLP RL VFB_OLP Figure 9. Feedback Open-Loop Protection Circuit Thermal Shutdown (TSD) The SenseFET and control IC integrated on the same package makes it easier to detect the temperature of the SenseFET. When the junction temperature exceeds 135°C, thermal shutdown is activated. FSL336LR is restarted after the temperature decreases to 60°C. 23 kHz 21 kHz 1.9V VBURL VBURH 0.8V VCOMP Figure 11. Green Mode Operation Adjusting Current Limit As shown in Figure 12, a combined 46 kΩ internal resistance (3R + R) is connected to the inverting lead on the PWM comparator. An external resistance of RX on the ILIMIT pin forms a parallel resistance with the 46 kΩ when the internal diodes are biased by the main current source of 50 µA. For example, FSL336LR has a typical SenseFET peak current limit of 1.8 A. Current limit can be adjusted to 1 A by inserting RX between the ILIMIT pin and the ground. The value of the RX can be estimated by Equation (1): Burst Operation To minimize power dissipation in Standby Mode, FSL336LR enters Burst Mode. As the load decreases, the compensation voltage (VCOMP) decreases. As shown in Figure 10, the device automatically enters Burst Mode when the feedback voltage drops below VBURL. At this point, switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes VCOMP to rise. Once it passes VBURH, switching resumes. VCOMP then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET and reduces switching loss in Standby Mode. 1.8 A: 1 A = (46 kΩ + RX): RX VO VFB (1) Transconductance Amplifier 4 Voset VBIAS VREF VCOMP VBURH VCOMP VBURL IPK 3R PWM 5 R ILIMIT IDS 3 VSENSE RX Figure 12. Current Limit Adjustment VDS time t1 Switching disabled t2 t3 Switching disabled t4 Figure 10. Burst Mode Operation © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 www.fairchildsemi.com 4 AN-4159 APPLICATION NOTE Detail Design Procedure VDC.min 2VAC.min 2 System Specifications Line voltage range (VAC.min and VAC.max): standard worldwide input line voltage ranges are 85-264 VAC for universal input, 195-264 VAC for European input range Line frequency (fL): 50 or 60 Hz Output voltage (VO) Estimated efficiency: η (3) VDC.max 2VAC.max (4) where DCH is the DC link capacitor charging duty ratio defined, as shown in Figure 13; which is typically about 0.15 for full-wave rectification and about 0.3 for halfwave rectification. Equations (2) and (3) are minimum link voltage of full-wave and half-wave rectification, respectively, and Equation (4) is maximum link voltage. Determining AC Input Rectification Type The typical AC-DC SMPS solution rectifies AC input with full-wave rectification. However, half-wave rectification can be selected for under 3 W designs with buck and buck-boost topology to reduce cost. For designs >3 W, full-wave rectification is typically selected to reduce the size of the input capacitor with small ripple voltage. Determining Operation Mode Before selecting the inductor, freewheeling diode, and output capacitor; the operating mode should be determined: Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM). DCM has smaller inductor size, lower freewheeling diode cost, and higher efficiency due to lower switching loss in low-power buck applications. However, DCM requires a higher current limit and increases output voltage ripple. Therefore, compromised selection is needed according to the system requirements. Determining DC Link Capacitor (CDC) and DC Link Voltage Range The DC link capacitor is selected by rectification type and input voltage range. For full-wave rectification, it is typical to select the DC link capacitor as 2-3 µF per watt of input power for universal input range (85-264 VAC) and 1 µF per watt of input power for European input range (195264 VAC). DC link capacitance of half-wave rectification is twice full-wave rectification: 4-6 µF per watt of input power for universal input range (85-264 VAC) and 2 µF per watt of input power for European input range (195-264 VAC). Figure 13 shows the input voltage waveform of full-wave and half-wave rectification. Table 1. Brief Comparison of CCM and DCM CCM DCM Larger Smaller Efficiency (Switching Loss) Lower (Larger) Higher (Smaller) Output Voltage Ripple Smaller Larger Lower Higher Output Inductor Size Current Limit Higher current limit means that, potentially, a highercurrent-rated device may be needed to deliver maximum output power. VIN,min TCH Selecting Freewheeling Diode DCH = TCH / TL Although a transformer for buck topology doesn’t exist, other leakage inductance and capacitance creates a voltage spike on the freewheeling diode when the SenseFET is turned off. Since this voltage spike must be considered, typically 30% voltage derating of maximum DC input is required, as described Equation (5). TL VIN,min TCH 2 PO ( 1-DCH ) η CDC f L VRRM 1.3 VDC,max DCH = TCH / TL The diode is one of the components generating high temperature in the SMPS. To decide the current rating of freewheeling diode, consider thermal performance of 150% design margin of the output full load current, as recommended in Equation (6): TL Figure 13. Bridge Rectifier and Bulk Capacitor Voltage Waveform Selecting AC rectification, the link voltages are obtained as: VDC.min 2VAC.min 2 2 PO ( 1/ 2-DCH ) η CDC f L © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 (5) I F(AV) 2.5 I O (2) (6) where VRRM is peak repetitive reverse voltage and IF(AV) denotes average rectified forward current. www.fairchildsemi.com 5 AN-4159 APPLICATION NOTE Reverse recovery time is also an important factor to choose the freewheeling diode. The smaller the reverse-recovery time, the lower the switching loss. where: Table 2. Quick Selection Guide for Freewheeling Diode for Universal Input Range Part # VRRM IF(AV) trr Package Type ES1J 600 V 1A 35 ns DO-204AC UF4005 600 V 1A 75 ns DO-204AL EGP10J 600 V 1A 75 ns DO-204AL EGP20J 600 V 2A 75 ns DO-204AC ES3J 600 V 3A 45 ns DO-214AB EGP30J 600 V 3A 75 ns DO201-AD β PO ηV DC. min I LIMIT Normally, the buck converter designed for CCM at the minimum input voltage and full-load condition can enter DCM as the input voltage increases. The maximum input voltage guaranteeing CCM operation in full-load condition is obtained as: VDC .CCM (7) I IL (8) I2 I ds. peak P IL O VOUT I IL IL I1 I 2 DCM Operation : L < LBoundary Figure 14. MOSFET Drain Current Maximum drain current peak (Ids.peak) at full-load condition is determined by the selected output inductor. If the maximum drain current peak is larger than the pulse-bypulse current limit, larger output inductance or higher current rating of the device is needed. Equations (13) and (14) show the maximum drain current peak of CCM and DCM operation, respectively. If this maximum drain current peak is smaller than pulse-by-pulse current limit, the output inductor size is optimized through connecting a resistor between the ILIMIT pin and the IC ground pin. (9) f S ( I ds. peak 0.8V ) 22kHz © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 I 2 CCM Operation : L > LBoundary f S ( I ds. peak 0.8V ) 22kHz 2VDC . min VO Lf S I ds. peak IL I1 Since FSL336LR has a Green Mode, the practical operating switching frequency at full load can be smaller than f S.HIGH. By two simultaneous equations representing the relationship between switching frequency and peak drain current, the operating switching frequency is calculated. Each equation, (9) and (10), includes two simultaneous equations. These are for CCM operation and DCM operation, respectively: I ds. peak (12) I2 where VOUT is the sum of target output voltage (VO) and freewheeling diode forward-voltage drop (VF), as determined by Equation (7), and fS.HIGH is maximum switching frequency in Green Mode operation, as illustrated on Figure 11. VDC . min VDC . min VO VOUT / VDC . min VOUT 2 Lf S VO 2 PO f S L 1 2 η VOUT where, fS is the operating switching frequency considering Green Mode. The inductance operating with Boundary Conduction Mode (BCM) at minimum input DC voltage is represented in Equation (8). Smaller inductance than LBoundary can be selected for DCM operation and larger for CCM operation. I ds. peak (11) 2.4V V VO SL t CLD DC. min t CLD L where ILIMIT is the peak current limit; SL is the test slope (di/dt) of ILIMIT; and tCLD is the current limit delay. Typically α, ILIMIT, SL, and tCLD are 25.5 kHz/V, 1.8 A, 1.2 A/µs, and 200 ns, respectively. Selecting Output Inductor V 2 η 1- O VOUT V LBoundary DC.min 2 PO f S .HIGH f S.HIGH f S.LOW VGREEN.HIGH VGREEN.LOW γ The forward voltage drop (VF) of the selected freewheeling diode is an important factor for other equations. Especially when the equations are related to output voltage, the output voltage must include forward-voltage drop for more exact calculation, as shown in Equation (7): VOUT VO VF α (10) www.fairchildsemi.com 6 AN-4159 APPLICATION NOTE I ds.peak PO ηVOUT I ds.peak VO 1 VDC.min 2 Lf S VO 21 VDC.min ηLf S VOUT The IC ground is pulsed between input DC voltage and the ground of output voltage when the SenseFET is turned on and freewheeling diode is conducted. Output voltage is sensed through a feedback diode (DFB) during the conduction time of the freewheeling diode. The feedback diode is typically selected to remove the difference of forward-voltage drop between the feedback diode and the freewheeling diode. As this voltage difference is increased, the output voltage regulation can degrade. (13) PO (14) For an application needs multi-output buck converter with coupled inductor, refer to the step-by-step design guideline in Appendix A. Since the output voltage is sensed only during freewheeling diode conduction time, a feedback capacitor helps maintain sensed output voltage, especially for Burst Mode operation. A value larger than 1 µF is typically recommended. Larger feedback capacitance results in better output voltage regulation performance. Adjusting Pulse-by-Pulse Current Limit The resistor is determined by Equation (15) and this adjusted pulse-by-pulse current limit must be higher than the maximum drain current peak defined by Equations (13) and (14). This function is disabled by letting ILIMIT pin be open-circuited, such as: Two feedback resistors determine output voltage, as in Equation (18), and, by reducing the voltage difference between sensed output voltage (VO) and feedback capacitor voltage (VFB*), more accurate output control is possible: RX I ds. peak (15) 46kΩ R X where ILIMIT is pulse-by-pulse current limit of the FPS, typically it is 1.8 A. For better noise immunity at ILIMIT pin, a small capacitor (1 nF~100 nF) is recommended. I LIMIT.adj I LIMIT RA RB (18) RB where KREG is regulation factor regarding mismatched voltage between output voltage (VO) and feedback capacitor voltage (VFB*). It is typically 2 [V/A]. VFB * VO K REG I O 2.5V Selecting the Output Capacitor Determining Compensation Network The maximum output voltage ripple is determined by the output capacitance and the Equivalent Series Resistance (ESR) of the output capacitor. Since the output voltage ripple by capacitance is negligibly small when over than 100 µF is selected, the output ripple is mostly determined by the ESR of output capacitor: CO.recommend Because the FSL336LR employs current-mode control and a transconductance amplifier (gm amp) internally, a compensation network can be implemented simply. As illustrated on Figure 16, a two-pole and one-zero circuit can secure enough phase margin and bandwidth. FSL336LR 5 8 ESR f S (16) Vcomp VFB 1 ESR) ΔI ESR ΔI (17) 8CO f S where CO.recommend is the recommended output capacitance, typically is larger than 100 µF. Ripple ( The feedback network is comprised of one diode for sensing output voltage, one capacitor to maintain sensed output voltage during the SenseFET turn-on period, and two resistors to determine output voltage, as shown in Figure 15. ILIMIT GND VCC Drain GND The current control factor, K, is defined as: DFB RA Vcomp VFB Drain Drain Figure 16. Compensation Network FSL3xx VCC CF2 RF Designing the Feedback Network Drain ILIMIT CF1 RB CFB Sensed VO VFB K * VCOMP I LIMIT VCOMP.sat (19) where Ids.peak is the peak drain current and VCOMP denotes the compensation voltage, respectively, for a given fullload condition, ILIMIT is the current limit of the FSL336LR; and VCOMP.sat is the compensation saturation voltage, which is typically 2.4 V. Figure 15. Feedback Network © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 I ds. peak www.fairchildsemi.com 7 AN-4159 APPLICATION NOTE To express the small-signal AC transfer functions, the small-signal variations of compensation voltage (νCOMP) and output voltage (νO) are introduced as and vˆCOMP and vˆO . For 40 dB fp 20 dB CCM operation, the control-to-output function of the buck converter applying current-mode control is given by: 0 dB 1 s / z Gvc ( s) Gvc 0 (20) vˆcomp 1 s / p where K is specified in Equation (19) and RL is the load resistance of the output port, defined as VO/IO. The pole and zero of Equation (20) are expressed as: fz vˆo Low input voltage -20 dB fz -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 18. DCM Control-to-Output Transfer Function Variation for Different Input Voltages Gvc 0 K RL (21) 1 1 & p ESR CO ( ESR RL ) CO where ESR is equivalent series resistance of the output capacitor and CO is the output capacitance. z Figure 19 shows the variation of the converter control-tooutput transfer function for variation in the output load current. Both CCM and DCM operation have similar variation, where gain is increased and pole is decreased as output load is decreased. For DCM operation, the control-to-output transfer function of the buck converter adopting current-mode control is given by: 1 s / z Gvc ( s) Gvc 0 1 s / p Gvc 0 K VO z High input voltage fp 40 dB fp fp 20 dB (22) Heavy load 0 dB 2 L f s V PO 1 O V DC VDC / VO 1 2 VDC / VO 3 Light load (23) 1 ESR CO -20 dB fz -40 dB fz 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 19. Control-to-Output Transfer Function Variation for Different Output Loads 2 3 VO / VDC C O 2 ESR RL (3 ESR RL ) VO / VDC where η is the efficiency of the converter and VDC is the input DC voltage. p The transfer function of the compensation network is obtained as: Gvc ( s) Figure 17 shows the variation of a CCM converter control-tooutput transfer function for various input voltages. DC gain, pole, and zero do not change for different input voltages. pc1 1 s / zc ( s / pc1 ) /(1 s / pc2 ) (24) g m RB , (CF 1 CF 2 ) ( RA RB ) (25) 1 1 1 & zc pc2 RF CF 1 CF1 CF 2 where RA and RB are defined in Figure 15 and RF, CF1 and CF2 are shown in Figure 16. 40 dB 1 RF 20 dB fp Fixed by input voltage variation 0 dB 40 dB -20 dB fz 20 dB fzc fpc2 -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 0 dB Figure 17. CCM Control-to-Output Transfer Function Variation for Different Input Voltages fpc1 -20 dB Figure 18 shows the variation of a DCM converter controlto-output transfer function for various input voltages. It has the lowest DC gain at low-line input condition. -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 20. Compensation Network Transfer Function © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 www.fairchildsemi.com 8 AN-4159 APPLICATION NOTE Design Tips for Compensation Network a) To secure enough phase margin compensation, the second pole (fpc2) and zero (fzc) should be separated as much as possible. Large CF1 and small CF2 are recommended. Selecting Dummy Load Resistor Since the feedback capacitor voltage sensed from output voltage is not accurately matched with output voltage, the output voltage regulation can be poor at light-load condition. The dummy load resistor increases output load and this small load helps output voltage regulation at light-load condition. A 5~20 kΩ resistor is typically selected. b) For wide bandwidth of transfer function, compensation zero (fzc) should be as small as possible. c) The recommended minimum capacitance of CF2 is 100~470 pF to avoid noise. Based on design tips; typically 220 pF, 220 nF, and 75 kΩ are recommended for CF2, CF1, and RF, respectively. Design Example Application Output Power Input Voltage Range Output Voltage / Maximum Current Home Appliance and Industrial Auxiliary Power 7.08 W 85-265 VAC 15 V / 0.45 A and 3.3 V / 0.1 A Description of Schematic Full-wave rectification is selected for AC line rectification. For better EMI performance, X-cap (CX1), two fixed inductors instead of line filter (LF001), and Pi-type filter (C1, C2, L1, L2, and R1) are selected. For small standby power consumption, VCC is externally supplied from output voltage through D5 and R2. C8 is used on the ILIMIT pin for better noise immunity. Small SMD type (1 µF) is used for VCC capacitor. Coupled inductor is used for 3.3 V output without much loss on positive voltage regulator (U2). D5 1N4148 R6 75kΩ 0805 C9 220nF 0805 5.Vcomp R10 3.3kΩ 1206 LF001 330µH // 330µH BR1 MB6S C1 10µF 400V R1 4.7kΩ 1206 L2 Short R11 3.3kΩ 1206 C10 220pF 0805 C2 10µF 400V D6 ES1J Sensed output VCC U1 FSL336LR L1 330µH R2 10Ω 0805 R3 120kΩ 0805 D4 ES1J C4 47µF/25V 4.VFB C5 2.2µF 0805 3.ILIMIT 7.D 2.VCC 8.D 1.GND R4 23.2kΩ 0805 VCC C7 1µF 0805 C6 NC C8 1nF 0805 R0 NC 1206 R5 NC 0805 C11 47µF/25V U2 KA78RH33 3.3V output 100mA 12 2 6 10 L3 EFD20 192µH C3 220µF/25V v R7 10k 0805 Sensed output 15V output 450mA D3 ES1J CX1 100nF R8 NC 1206 R9 NC 1206 VZ1 471KD07 F1 1A/250V AC Universal range Figure 21. Design Example Schematic © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 www.fairchildsemi.com 9 AN-4159 APPLICATION NOTE Table 3. Bill of Materials for Evaluation Board Part # Value Note Part# Value U1 FSL336LRN Fairchild Buck Switch C1 10 µF 400 V Electrolytic Capacitor U2 KA78RH33 Fairchild Voltage Regulator C2 10 µF 400 V Electrolytic Capacitor C3 220 µF 25 V Electrolytic Capacitor R0 NC 5% 1206 SMD C4 47 µF 25 V Electrolytic Capacitor R1 4.7 kΩ 1% 1206 SMD C5 2.2 µF 0805 SMD R2 10R 5% 0805 SMD C6 NC 50 V Electrolytic Capacitor R3 120 kΩ 1% 0805 SMD C7 1 µF 0805 SMD R4 23.2 kΩ 1% 0805 SMD C8 1 nF 0805 SMD R5 NC 1% 0805 SMD C9 220 nF 0805 SMD R6 75 kΩ 5% 0805 SMD C10 220 pF 0805 SMD R7 10 kΩ 5% 0805 SMD C11 47 µF 25 V Electrolytic Capacitor R8 NC 5% 1206 SMD CX1 100 nF X-Cap 250 VAC R9 NC 5% 1206 SMD R10 3.3 kΩ 5% 1206 SMD D3 ES1J Fairchild Super-Fast Diode R11 3.3 kΩ 5% 1206 SMD D4 ES1J Fairchild Super-Fast Diode D5 1N4148 Fairchild Signal Diode IC Note Capacitor Resistor Diode Inductor LF001 330 µH *2 Axial Type D6 ES1J Fairchild Super-Fast Diode L1 330 µH Axial Type BR1 MB6S 0.5 A 600 V Bridge Diode L2 Jumper Wire Axial Type L3 749196521 Flexible Transformer EFD20 F1 1A Varistor VZ1 471KD07 Varistor 7Φ 470 V Fuse © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 250 V Radial Type www.fairchildsemi.com 10 AN-4159 APPLICATION NOTE Experimental Results Table 4. No-Load Input Wattage, Full-Load Efficiency, IC Temperature, Experimental Result Input Voltage Input Wattage (No Load) Efficiency (Full Load) IC Temperature (Full Load) 85 V / 60 Hz 0.083 W 77.38% 58°C 110 V / 60 Hz 0.083 W 78.35% 54°C 230 V / 60 Hz 0.094 W 77.68% 61°C 265 V / 60 Hz 0.099 W 76.79% 65°C Experimental Waveforms CH2:VCC [5V/div] CH2:VCC [5V/div] CH1:VDS [100V/div] CH1:VDS [100V/div] Figure 22. Normal Operation at Input Voltage 85 VAC (CH1: VDS, CH2: VCC) Figure 23. Normal Operation at Input Voltage 265 VAC (CH1: VDS, CH2: VCC) CH2:VCC [5V/div] CH2:VCC [5V/div] CH1:VDS [100V/div] CH1:VDS [100V/div] Figure 24. Burst Operation at Input Voltage 85 VAC and No Load (CH1: VDS, CH2: VCC) © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 Figure 25. Burst Operation at Input Voltage 265 VAC and No Load (CH1: VDS, CH2: VCC) www.fairchildsemi.com 11 AN-4159 APPLICATION NOTE Output Voltage Regulation, Experimental Results Figure 26. 15 V Output Voltage Regulation Conduction Electromagnetic Interference (EMI) Performance Att dBµV 1 100 10 dB RBW 9 MT 10 PREAMP OFF kHz ms MHz 10 MHz 90 1 PK MAXH 2 80 AV MAXH TDF 70 EN55022Q 60 PRN EN55022A 50 6DB 40 30 20 10 0 150 Comment: Date: kHz 30 MHz 2-230N 21.JUN.2013 14:27:15 Figure 27. 110 VAC with Full Load Condition Att dBµV 1 100 10 dB MHz RBW 9 MT 10 PREAMP OFF kHz ms 10 MHz 90 1 PK MAXH 2 80 AV MAXH TDF 70 EN55022Q 60 PRN EN55022A 50 6DB 40 30 20 10 0 150 Comment: Date: kHz 30 MHz 2-230N 21.JUN.2013 14:25:33 Figure 28. 230 VAC with Full Load Condition © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 www.fairchildsemi.com 12 AN-4159 APPLICATION NOTE Appendix A — Design Guideline of Coupled Inductor An LDO, which is directly connected to for multi-output as illustrated on the Figure 29, has poor efficiency and temperature performance on the LDO itself. To avoid these problems, a coupled inductor is typically selected (see Figure 30). An advantage of coupled inductor is achieving isolation between the two outputs through different ground connections. This appendix describes step-by-step design guideline as well as basic operation of a coupled inductor. FSL336LR Rectified AC input The applied voltage on slave side (VNs): VNs (VOm VFm ) N s / N m . where VDC is DC input voltage. The number of windings of master and slave output are represented by Nm and Ns. VOm and VFm denote the output voltage and the forwardvoltage drop of the freewheeling diode, respectively. OUT GND VNs VOs 7.Drain 8.Drain - LDO IN The description of coupled inductor operation when the freewheeling diode is conducted: - The applied voltage on master side (VNm): VNm (VOm VFm ) . VOs 1.GND t VOm Freewheeling diode for master output Figure 29. Circuit Diagram of Multi-Output Buck Converter with LDO Output diode for slave output FSL336LR tON VOs Coupled inductor 7.Drain 8.Drain VNs v Rectified AC input 1.GND Freewheeling diode for master output where VFs is forward-voltage drop of the slave output diode. Rdummy Figure 30. Typical Circuit Diagram of Buck Converter Adopting Coupled Inductor Step 1: Calculate Inductance and Maximum Drain Current Peak Step 0: Describe Operation of Buck Converter Adopting Coupled Inductor The inductance operating with Boundary Conduction Mode (BCM) at minimum input DC voltage is represented in Equation (8) and the inductance is selected as below. When the internal SenseFET is turned on, the freewheeling diode is blocked and the VDC-VOm is applied to the master side of the coupled inductor. According to the winding notation, the applied voltage on the slave side (VNs) is the applied voltage to the master side, divided by turn ratio. Since this VNs is negative, the output diode for slave output is blocked. During this period, the energy is not delivered to the slave output. L > LBoundary for CCM operation L < LBoundary for DCM operation. V 2 η 1- Om VOm VFm where LBoundary VDC.min 2 PO f s When the freewheeling diode is conducted, the applied voltage on the master side of the coupled inductor (V Nm) is the sum of the master output voltage (VOm) and the forwardvoltage drop of the freewheeling diode (V Fm). Since VNm is negative, VNs is positive and the output diode for the slave output is conducted. The slave output voltage (VOs) is determined when the freewheeling diode is conducted. Based on the operation mode, the maximum drain current peak is decided as below: V 1 Om VOm VFm V PO DC.min I ds.peak ηVOm VFm 2 Lf S for CCM operation. The description of coupled inductor operation when the gate of FSL336LR turns on: - The applied voltage on master side (VNm): VNm VDC VOm . I ds.peak The applied voltage on slave side (VNs): VNs (VDC VOm ) N s / N m . © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 tS VOs (VOm VFm ) N s / N m VFs VOm - tON The slave output voltage is described as: VNm tS Figure 31. Waveforms of the Applied Voltage on Slave Side of Coupled Inductor and Slave Output Voltage V 21 Om V DC.min ηLf S PO for DCM operation. where VDC.min is the minimum DC input voltage. www.fairchildsemi.com 13 AN-4159 APPLICATION NOTE is Step 2: Determine Core Size of Coupled Inductor Is.pk ΔIs Before selecting the coupled inductor size, the current limit is able to be adjusted to optimize the core size as below. IOs RX I ds. peak. max 46kΩ R X where ILIMIT.min denotes the minimum pulse-by-pulse current limit and RX is the external resistor on the ILIMIT pin. Since the couple inductor of buck converter operates similar to the transformer of a flyback converter, as illustrated in Step 0; typical cores, such as EI, EE, and EF type can be selected from Table 5. I LIMIT.adj. min I LIMIT . min t ton Figure 33. Waveform of Slave Output Diode Current in CCM Operation 2 V 1 Om VDC . min PO 1 I L.rms (VOm VFm ) Lf s 12 VOm VFm RMS value of master side inductor current in CCM. V VFm 3 (VOs VFs ) 2 (1 Om ) 2 I Os VDC . min I s.rms 2 V VFm 12Lf s ( N s / N m ) 1 Om VDC . min RMS value of slave output diode current in CCM. 2 Table 5. Core Selection Table (for Universal Input Range, fS=50 kHz and PO=5~10 W) EI Core EE Core 2 EF Core 2 2 Size Ae (mm ) Size Ae (mm ) Size Ae (mm ) EI12.5 14.4 EE16 19.0 EF12.6 13.0 EI16 19.8 EE19 23.0 EF16.0 20.1 EI19 24.0 EE20 31.0 EF20.0 33.5 toff iL Step 3: Calculate Minimum Primary Turns With the chosen core, the minimum number of turns for the master side to avoid the core saturation is given by: N m. min Lmax I LIMIT .adj. max Bsat Ae t tON RX I LIMIT.adj. max I LIMIT . max 46 kΩ RX ; L where max is the maximum value of the inductance, Bsat is the saturation flux density; and Ae denotes the cross-sectional area of the core. toff Figure 34. Waveform of Inductor Current of Master Side in DCM Operation is Step 4: Determine the Number of Turns for Master and Slave Outputs The numbers of turns for master and slave side are determined as below: t N m N m. min Ns ton toff Figure 35. Waveform of Slave Output Diode Current in DCM Operation VOs VFs Nm VOm VFm VOm VFm V 1 81 Om PO 3 VDC.min VDC.min VDC .min 9 Lf S η3 Step 5: Determine Wire Diameter for Each Winding Based on RMS Current I L.rms The rms currents of each winding are obtained as below. RMS value of master side inductor current in DCM. iL I s.rms I Os toff Figure 32. Waveform of Inductor Current of Master Side in CCM Operation © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 RMS value of slave output diode current in DCM. where IOs is the slave output load. Current density of 6~10 A/mm2 is typically recommended. To avoid severe eddy current losses, avoid diameter >0.5 mm. t ton V 8η1 Om V DC.min (VOm VFm ) 9 PO f s L www.fairchildsemi.com 14 AN-4159 APPLICATION NOTE Appendix B — Equation Details Equation A:VDC.min V AC.min 2 Equation 2: Minimum DC Input Voltage The voltage ripple at the DC link capacitor can be calculated with the power delivered to converter system. PO η C DC V AC.min 2 t AC_dis 1 AC_F) 2 fL where AC_F is 0 for half-wave rectification and 1 for full-wave rectification. Equation B:VDC.min V AC.min 2 cos 2πf L(t AC_dis ( 1-DCH ) 1 2 2 CDC( 2VAC.min VDC.min ) Pin 2 fL for half-wave rectification. Equation 7: Inductance at Boundary Conduction Mode ( 1/ 2-DCH ) 1 2 2 CDC( 2VAC.min VDC.min ) Pin 2 fL To be operated in BCM, the average value of inductor current should be identical to the half of the ripple of inductor current, as shown below. for full-wave rectification. Therefore, the calculation methods for minimum DC input voltage are: VDC,min 2VAC.min 2 IL 2 PO ( 1-DCH ) η CDC f L IL I IL for half-wave rectification. VDC,min 2VAC.min 2 I 2 2 PO ( 1/ 2-DCH ) η CDC f L for full-wave rectification. t Since DCH in the above equations is difficult to estimate exactly, calculating VDC.min through the below two simultaneous equations is an alternative. Equation A is about the input voltage discharging waveform by input power. Equation B is about AC input voltage waveform. Through these equations, a more exact minimum input voltage can be calculated without the estimation of DCH. Figure 38. Inductor Current at BCM IL IL I I 2 IL Vin,min t Figure 39. Inductor Current at CCM tCH 1 ΔiL 2 I (V VO )D in DC . min D 2 Lboundaryf S . HIGH IL DCH = tCH / tL tL Figure 36. Full-Wave Rectification The inductance to be operated in BCM is: Vin,min tCH VOUT I in (V VO )VOUT / VDC . min DC . min / VDC . min 2 Lboundaryf S . HIGH η( 1 DCH = tCH / tL Lboundary tL Figure 37. Half-Wave Rectification © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 VO )VOUT 2 VDC . min 2 f S .HIGH PO www.fairchildsemi.com 15 AN-4159 APPLICATION NOTE Equation 8, 11: Operating Switching Frequency and Drain Peak Current at CCM Equation 9, 12: Operating Switching Frequency and Drain Peak Current at DCM By Green Mode levels (refer to Figure 11): As above CCM calculation: fS f S .HIGH f S .LOW (VCOMP 0.8V ) 22kHz VGREEN .HIGH VGREEN .LOW fS The relationship between VCOMP and Ids.peak is: VCOMP I LIMIT VCOMP 2.4V I ds. peak VDC . min VO SL t CLD t CLD L I LIMIT I in I L PO (V VO )VOUT / VDC . min DC . min D 2 VOUT 2 Lf S For simplicity, some of constants are substituted as: f S .HIGH f S .LOW PO , , VGREEN .HIGH VGREEN .LOW VDC . min I LIMIT V Vo 1 I ds.peakD1 & I ds.peak DC . min D1 2 Lfs 1 Lfs 2 I in I ds.peak 2 VDC . min Vo I in 2.4V V VO SL t CLD DC . min tCLD L Po ηVDC . min I ds.peak There are two simultaneous equations having two variables, Ids.peak and fs: Equation A:f S α(γ I ds.peak 0.8V) 22kHz Equation B:I ds.peak β 2.4V I ds. pk VDC . min VO SL t CLD t CLD L However, the calculation method of Ids.peak for DCM operation is: The calculation method of Ids.peak for CCM operation is: I ds. peak f S .HIGH f S .LOW (VCOMP 0.8V ) 22kHz VGREEN .HIGH VGREEN .LOW VDC.min VDC.min VO VOUT /V DC.min VOUT 2 Lf S 1 Lfs 2 I ds.peak 2 VDC . min Vo 2(VDC . min Vo ) Po Lfs ηVDC . min For simplicity, some of constants are substituted with the same as for CCM operation: f S . HIGH f S . LOW PO , , VGREEN . HIGH VGREEN .LOW VDC . min I LIMIT 2.4V V VO SL tCLD DC . min tCLD L There are two simultaneous equations having two variables, Ids.peak and fs: Equation A : f S ( I ds. peak 0.8V ) 22kHz Equation B : I ds. peak 2VDC . min VO Lf S Related Datasheets FSL336LRN − Green Mode Fairchild Buck Switch DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2013 Fairchild Semiconductor Corporation Rev. 1.1 • 12/30/14 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness www.fairchildsemi.com 16

- Similar pages
- FAIRCHILD AN-6075
- FAIRCHILD FSDM07652RE
- FAIRCHILD DM0465RE
- FAIRCHILD FSDM0465RS
- FAIRCHILD AN-9719
- 25W quasi-resonant flyback converter for set
- How to Generate a Negative Voltage Using Buck Converters?
- AN-5844 - Fairchild Semiconductor
- STANDARD PRODUCTS GUIDE - Fairchild Semiconductor
- PDFDownload - Fairchild Semiconductor
- INTERSIL ISL61863GCRZ
- FAIRCHILD FAN9611
- MAXIM MAX1897EGP
- MAXIM MAX1980
- SUNTAN TSV
- FAIRCHILD AN-6861
- LINER LT1306