www.fairchildsemi.com AN-6920MR Integrated Critical-Mode PFC / Quasi-Resonant Current-Mode PWM Controller FAN6920 1. Introduction This application note presents practical step-by-step design considerations for a power supply system employing Fairchild’s FAN6920 PFC / PWM combination controller, an integrated Boundary Conduction Mode (BCM) Power Factor Correction (PFC) controller and Quasi-Resonant (QR) PWM controller. Figure 1 shows the typical application circuit, where the BCM PFC converter is in the front end and the dual-switch quasi-resonant flyback converter is in the back end. FAN6920 achieves high efficiency with relatively low cost for 75~200 W applications where BCM and QR operation with a two-switch flyback provides best performance. A BCM boost PFC converter can achieve better efficiency with lower cost than continuous conduction mode (CCM) boost PFC converter. These benefits result from the elimination of the reverse-recovery losses of the boost diode and zero-voltage switching (ZVS) or near ZVS (also called valley switching) of boost switch. The dual-switch QR flyback converter for the DC-DC conversion achieves higher efficiency than the conventional flyback converter with leakage inductor energy recycles. The FAN7382, a monolithic high- and low-side gate-driver IC, can drive MOSFETs that operate up to +600 V. Efficiency can be further improved by using synchronous rectification in the secondary side instead of a conventional rectifier diode. BCM Boost PFC Dual-Switch Quasi-Resonant Flyback NBOOST RHV NCZD RPFC1 CINF2 CO.PFC NB RG1 RPFC2 RCS1 FAN7382 FAN6920 CCOMP CINF1 1 RANGE HV 16 2 NC 15 COMP 3 INV RVIN1 RCZD RRT VIN 13 5 CSPWM RT 12 6 OPFC FB 11 7 VDD DET 10 8 OPWM GND 9 VB 8 2 HIN HO 7 3 LIN VS 6 4 COM LO 5 VO + NS - NP CRT ZCD 14 4 CSPFC 1 VCC RCS2 NTC RBIAS RO1 CFB VAC RF RVIN2 NA CVIN RDET1 CDD CF KA431 RO2 RDET2 Figure 1. Typical Application Circuit © 2010 Fairchild Semiconductor Corporation Rev. 1.0. 1 • 2/22/13 www.fairchildsemi.com AN-6920 APPLICATION NOTE 2. Operation Principles of BCM Boost PFC Converters The most widely used operation modes for the boost converter are continuous conduction mode (CCM) and boundary conduction mode (BCM). These refer to the current flowing through the energy storage inductor of the boost converter, as depicted in Figure 2. As the names indicate, the inductor current in CCM is continuous; while in BCM, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. Even though the BCM operation has higher RMS current in the inductor and switching devices, it allows better switching condition for the MOSFET and the diode. As shown in Figure 2, the diode reverse recovery is eliminated and a fast silicon carbide (SiC) diode is not needed. MOSFET is also turned on with zero current, which reduces switching loss. IL source. This behavior makes the boost converter in BCM operation an ideal candidate for power factor correction. A by-product of the BCM is that the boost converter runs with variable switching frequency that depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output power delivered to the load. The operating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown in Figure 3. The lowest frequency occurs at the peak of sinusoidal line voltage. VIN,PK VIN t Average of Input Current IL ID VO.PFC L VLINE VIN IDS VGS Line Filter CCM IL tON t t fSW t IDS ID Figure 3. Operation Waveforms of BCM PFC Reverse Recovery tON The voltage-second balance equation for the inductor is: tOFF VIN (t ) tON (VO.PFC VIN (t )) tOFF BCM IL (1) where VIN(t) is the rectified line voltage. IDS The switching frequency of BCM boost PFC converter is obtained as: ID f SW tON tOFF Figure 2. CCM vs. BCM Control The fundamental idea of BCM PFC is that the inductor current starts from zero in each switching period, as shown in Figure 3. When the power transistor of the boost converter is turned on for a fixed time, the peak inductor current is proportional to the input voltage. Since the current waveform is triangular, the average value in each switching period is also proportional to the input voltage. In the case of a sinusoidal input voltage, the input current of the converter follows the input voltage waveform with a very high accuracy and draws a sinusoidal input current from the © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 1 1 VO.PFC VIN (t ) tON tOFF tON VOUT 1 VO.PFC VIN , PK | sin(2 f LINE t ) | tON VO.PFC (2) where VIN,PK is the amplitude of the line voltage and fLINE is the line frequency. Figure 4 shows how the MOSFET on time and switching frequency change as output power decreases. When the load decreases, as shown in the right side of Figure 4, the peak inductor current diminishes with reduced MOSFET on time and the switching frequency increases. www.fairchildsemi.com 2 AN-6920 APPLICATION NOTE 3. Operation Principle of DualSwitch Quasi-Resonant (QR) Flyback Converter Average of Input Current IL The dual-switch QR flyback converter is derived from the conventional pulse-width modulated (PWM) flyback converter. With the recycling loop of the residual energy stored in leakage inductance, the primary-side snubber and its loss can be removed. This is especially suitable for highpower (up to 200 W) and slim-type applications. Figure 6 and Figure 7 show the simplified circuit diagrams of a dualswitch quasi-resonant flyback converter and its typical waveforms. The basic operation principles are: t VGS t fSW When primary power switches turn on, input voltage (VIN) is applied across the primary-side inductor (Lm). MOSFET current (IDS) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. When the primary MOSFETs turn off, the leakage inductance energy generates voltage spikes on the drain-to-source voltage (VDS) of MOSFETs. As soon as VDS reaches VIN, recycling diodes D1 and D2 are conducted and the residual energy is released to the input capacitor. As VDS is lower than VIN, the energy stored in the primary inductor forces the output rectifier (D3) to conduct. During the diode on time (tD), the output voltage (Vo) is applied across the secondary-side inductor and the diode current (ID) decreases linearly from the peak value to zero. At the end of tD, all the energy stored in the inductor has been delivered to the output. During this period, the output voltage is reflected to the primary side as Vo NP/NS. The sum of input voltage (V IN) and reflected output voltage (V o Np/Ns) is imposed across the MOSFETs. t Figure 4. Frequency Variation of BCM PFC Since the design of line filter and inductor for a BCM PFC converter with variable switching frequency should be at minimum frequency condition, it is worthwhile to examine how the minimum frequency of BCM PFC converter changes with operating conditions. Figure 5 shows the minimum switching frequency, which occurs at the peak of line voltage, as a function of the RMS line voltage for different output voltage settings. For universal line application, the minimum switching frequency occurs at high line (265 VAC) as long as the output voltage is lower than about 405 V. 80 VOUT =405V 70 V OUT =385V fSW (kHz) 60 The voltage on the primary-side winding is clamped to VIN. If the voltage of input is too low, the voltage of secondary side could be lower than output voltage target (VIN < NP/NS×VO), and the output voltage would follow input voltage drop. 50 V OUT =370V 40 30 20 10 85 130 175 220 265 RMS Line Voltage (V rms) Figure 5. Minimum Switching Frequency vs. RMS Line Voltage (L = 780 µH, POUT = 100 W) © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 When the inductor current reaches zero, the drain-tosource voltage (VDS) begins to resonate by the resonance between the primary-side inductor (Lm) and the MOSFET output capacitor (Coss1, Coss2) with an amplitude of Vo Np/Ns on the offset of VIN, as depicted in Figure 7. Quasi-resonant switching is achieved by turning on the MOSFET when VDS reaches its minimum value. This reduces the MOSFET turn-on switching loss caused by the capacitance loading between the drain and source of the MOSFET. www.fairchildsemi.com 3 AN-6920 APPLICATION NOTE IDS + VIN side VS goes below the IC supply voltage VDD or is pulled down to ground (the low-side switch is turned on and the high-side switch is turned off), the bootstrap capacitor, CBOOT, charges through the transformer primary-side, from the VDD power supply, as shown in Figure 8. This is provided by VBS when high-side VS is pulled to a higher voltage by the high-side switch. The VBS supply floats and the bootstrap diode reverses bias and blocks the rail voltage (the low-side switch is turned off and high-side switch is turned on) from the IC supply voltage, VDD. However, the dual-switch flyback high-side and low-side MOSFET turn on and off at the same time. Therefore, once the high-side MOSFET turns on, high-side VS equals PFC VO, the VDD can’t charge the CBOOT, even though the high-side VS is pulled down to ground at leakage energy recycle period, but the period is too short to charge CBOOT. Np:Ns Coss1 + VDS1 - D1 - Lm ID + D VO - + VDS2 - D2 Coss2 Figure 6. Schematic of Dual-Switch Flyback Converter Ids (MOSFET Drain-to-Source Current) Figure 8 shows the high-side gate-driver circuit with the auxiliary power supply. If VCBOOT is less than the HV IC under-voltage threshold, the high-side gate output (VHO) maintains turned-off state, then the low-side MOSFET turns on and charges the CBOOT for one cycle, high-side driver restarts at the next PWM cycle. Finally, the voltage of auxiliary power supply follows the output voltage rise and continues to supply energy to the high-side circuit. Ipk ID (Diode Current) Ipk×Np/Ns Bootstrap charge current path Auxiliary power charge current path VDD + VAUX.H - HV IC Vds PFC Vo VBOOT CBOOT Vo/2×Np/Ns High-Side VS VIN High-Side VGate VIN /2 Vo/2×Np/Ns Low-Side VGate GND tON VHO NS + VLO RCS2 - tD tS High-Side Bootstrap Charge Figure 7. Typical Waveforms of Dual-Switch QR Flyback Converter Under-Voltage Threshold 4. NP + VDD VCBOOT è Auxiliary Power Supply High-Side Gate-Drive Circuit Figure 8 and Figure 9 show the high/low-side gate driver circuit. The high-side gate drive IC achieves highperformance, is simple and inexpensive, but has a limitation for dual-switch flyback application. VHO VLO One of the most widely used methods to supply power to the high-side gate driver circuitry of the high-voltage gatedrive IC is the bootstrap power supply. This bootstrap power supply technique has the advantage of being simple and low cost. The bootstrap circuit is useful in a highvoltage gate driver and operates as follows. When the high© 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 Figure 8. High-Side Driver Circuit and Start Waveform www.fairchildsemi.com 4 AN-6920 APPLICATION NOTE Figure 9 shows the high-side driver circuit with standby power supply. This circuit uses the independent power supply for HV IC to keep the high-side driver operating. This circuit is used for applications with standby power, like the PC power. VDD (For PWM Controller) The MOSFET conduction time with a given line voltage at a nominal output power is given as: tON Standby Power VO.HIGH_SIDE - HV IC Using Equation (4), the minimum switching frequency of Equation (3) can be expressed as: PFC Vo VBOOT f SW , MIN CBOOT High-Side VS High-Side VGate Low-Side VGate Input Signal GND VHO NP NS RCS2 Figure 9. High-Side Driver Circuit with Standby Power Supply (5) VO.PFC (VLINE .MAX )2 VO.PFC 2VLINE .MAX 2 POUT f SW , MIN Line Voltage Range: 90~264 VAC (60 Hz) (6) Once the inductance value is decided, the maximum peak inductor current at the nominal output power is obtained at low-line condition as: Output of DC-DC Converter: 19 V/4.7 A (90 W) PFC Output Voltage: 400 V Minimum PFC Switching Frequency: > 50 kHz I L. PK Brownout Protection Line Voltage: 70 VAC Output Over-Voltage Protection Trip Point: 22.5 V 2 2 POUT VLINE , MIN (7) where VLINE,MIN is the minimum line voltage. Overall Efficiency: 90% (PFC Stage: 95%, DC-DC Stage: 95%) Since the maximum on time is internally limited at 20 µs, it should be smaller than 20 µs such as: Part A. PFC Section tON MAX [STEP-A1] Boost Inductor Design The boost inductor value is determined by the output power and the minimum switching frequency. From Equation (2), the minimum frequency with a given line voltage and MOSFET on time is obtained as: 2 POUT L 20 s VLINE.MIN 2 (8) The number of turns of boost inductor should be determined considering the core saturation. The minimum number is given as: N BOOST (3) I L, PK L (9) Ae B where Ae is the cross-sectional area of core and B is the maximum flux swing of the core in Tesla. where: VLINE is RMS line voltage; tON is the MOSFET conduction time; and VO.PFC is the PFC output voltage. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 VO.PFC As the minimum frequency decreases, the switching loss is reduced, while the inductor size and line filter size increase. Thus, the minimum switching frequency should be determined by the trade-off between efficiency and the size of magnetic components. The minimum switching frequency must be above 20 kHz to prevent audible noise. This design procedure uses the schematic in Figure 1 as a reference. A 90 W PFC application with universal input range is selected as a design example. The design specifications are: 1 VO.PFC 2VLINE tON VO.PFC where VLINE,MAX is the maximum line voltage. 5. Design Considerations f SW , MIN 2 POUT L - L VLINE 2 VO.PFC 2VLINE Since the minimum frequency occurs at high line as long as the PFC output voltage is lower than 405 V (as observed in Figure 5); once the output voltage and minimum switching frequency are set, the inductor value is given as: + + VLO (4) where: is the overall efficiency; L is the boost inductance; and POUT is the nominal output power. VO.LOW_SIDE + 2 PO.PFC L VLINE 2 B should be set below the saturation flux density. www.fairchildsemi.com 5 AN-6920 APPLICATION NOTE (Design Example) Since the output voltage is 400 V, the minimum frequency occurs at high-line (264 VAC) and fullload condition. Assuming the overall efficiency is 90% and selecting the minimum frequency as 50 kHz, the inductor value is obtained as: VLINE ,MAX 2 VO.PFC .H 2 VLINE ,MAX L 2 POUT f SW ,MIN NZCD VGS RZCD VO. PFC 1.5mA max. 0.9 264 2 400 2 264 464 H 2 90 50 103 400 + MAX ZCD 5 2 POUT L VLINE .MIN 2 11.1s 20s 2 90 450 10 0.9 90 2 I L ,PK L Ae B TRIG - PFC Gate ON 2.1V/1.75V Figure 10. Internal Block for ZCD 6 VGS Assuming QP2512 core (3C96, Ae=110 mm2) is used and setting B as 0.30T, the primary winding should be: N BOOST + 10V 2 2 POUT 2 2 90 3.14 A VLINE , MIN 0.9 90 0.45V - The maximum peak inductor current at nominal output power is calculated as: I L, PK VO.PFC NBOOST VAW The inductance of boot inductor is determined as 450 µH. tON IL VIN IL 3.14 450 106 42.82turns 110 106 0.30 N ZCD (VO.PFC VIN ) N BOOST VAW Thus, the number of turns (NBOOST) of boost inductor is determined as 44. N ZCD VIN N BOOST [STEP-A2] Auxiliary Winding Design 2.1V Figure 11 shows the internal block for zero-current detection (ZCD) for the PFC. FAN6920 indirectly detects the inductor zero current instant using an auxiliary winding of the boost inductor. ZCD The auxiliary winding should be designed such that the voltage of the ZCD pin rises above 2.1 V when the boost switch is turned off to trigger internal comparator as: N ZCD (VO.PFC .H 2VLINE .MAX ) 2.1V N BOOST (Design Example) The number of turns for the auxiliary (10) ZCD winding is obtained as: N ZCD The ZCD pin has upper and lower voltage clamping at 10 V and 0.45 V, respectively. When ZCD pin voltage is clamped at 0.45 V, the maximum sourcing current is 1.5 mA and, therefore, the resistor RZCD should be designed to limit the current of the ZCD pin below 1.5 mA in the worst case as: VIN N AUX 1.5mA N BOOST 2VLINE .MAX N AUX 1.5mA N BOOST © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 1.75V Figure 11. ZCD Waveforms where VO.PFC.H is the PFC output voltage for high line condition. RZCD 0.45V 2.1N BOOST (VO.PFC .H 2VLINE .MAX ) 3.5 turns With a margin, NAUX is determined as 8 turns. Then RZCD is selected from: RZCD (11) 2VLINE MAX N ZCD 2 264 8 45.248k 1.5mA N BOOST 1.5 10 3 44 as 47.5 k. www.fairchildsemi.com 6 AN-6920 APPLICATION NOTE [STEP-A3] Design VIN Sense Circuit (Design Example) Choosing the margin factor as 35%, FAN6920 senses the line voltage by using the averaging circuit shown in Figure 12, where the VIN pin is connected to the AC line through a voltage divider and low-pass filter capacitor. When VIN drops below 1 V, the COMP pin is clamped at 1.6 V to limit the energy delivered to output. VO.PFC decreases with the INV pin voltage. When the INV pin voltage drops below 1 V, brownout protection is triggered, stopping gate drive signals of PFC and DC-DC. This protection is reset when VDD drops below the turn-off threshold (UVLO threshold). When VDD rises to the turn-on voltage after dropping below the turn-off threshold, FAN6920 resumes normal operation (if VIN is above 1.2 V). the sensing resistor is selected as: [STEP-A6] Design Compensation Network The feedback loop bandwidth must be lower than 20 Hz for the PFC application. If the bandwidth is higher than 20 Hz, the control loop may try to reduce the 120 Hz ripple of the output voltage and the line current is distorted, decreasing power factor. A capacitor is connected between COMP and GND to attenuate the line frequency ripple voltage by 40 dB. If a capacitor is connected between the output of the error amplifier and the GND, the error amplifier works as an integrator and the error amplifier compensation capacitor can be calculated by: The brownout protection level can be determined as: VLINE .BO RVIN 1 RVIN 2 RVIN 2 2 2 (12) The minimum line voltage for PFC startup is given as: VLINE.STR 1.2 VLINE.BO AC Line (Design Example) Brownout comparator RVIN1 VIN 1V/1.2V 100 g M 2.5 2 2 f LINE VO.PFC .H CCOMP 13 2.3V VINV (15) To improve the power factor, CCOMP must be higher than the calculated value. However, if the value is too high, the output voltage control loop may become slow. FAN6920 Brownin/out Startup 100 g M 2.5 2 2 f LINE VO.PFC .H CCOMP (13) Brownout Protection 0.82 0.82 0.19 I L.PK (1 K MARGIN ) 3.14(1 0.35) RCS1 CVIN RVIN2 100 125 106 2.5 103nF 2 2 60 400 470 nF is selected for better power factor. Figure 12. VIN Sensing Internal Block Part B. DC-DC Section (Design Example) Setting the brownout protection trip point as 69 VAC: [STEP-B1] Determine the Secondary-Side Rectifier Voltage (VDnom) Figure 13 shows the typical operation waveforms of a dualswitch quasi-resonant flyback converter. When the MOSFET is turned off, the input voltage (PFC output voltage), together with the output voltage reflected to the primary (VRO), are imposed on the MOSFET. When the MOSFET is turned on, the sum of input voltage reflected to the secondary side and the output voltage is applied across the secondary-side rectifier. Thus, the maximum nominal voltage across the MOSFET (Vdsnom) and diode are given as: RVIN 1 RVIN 2 2 2 VLINE .BO 62 RVIN 2 Determining RVIN2 as 154 kΩ, RVIN1 is determined as 9.4 MΩ. The line voltage to startup the PFC is obtained as: VLINE.STR 1.2 VLINE.BO 83VAC [STEP-A4] Current Sensing Resistor for PFC FAN6920 has pulse-by-pulse current limit function. It is typical to set the pulse-by-current limit level at 20~30% higher than the maximum inductor current: 0.82 RCS1 I L.PK (1 K MARGIN ) VDS VO.PFC n(VO VF ) VO.PFC VRO 2 2 (16) where: (14) n where KMARGIN is the margin factor and 0.82 V is the pulse-by-pulse current limit threshold. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 nom VD VRO NP N S VO VF nom VO VO.PFC n (17) www.fairchildsemi.com 7 AN-6920 APPLICATION NOTE By increasing VRO (i.e. the turns ratio, n), the capacitive switching loss and conduction loss of the MOSFET are reduced. This also reduces the voltage stress of the secondary-side rectifier. VRO should be determined by a trade-off between the hold-up time and voltage stresses of the secondary-side rectifier diode. IDS Lower PFC output voltage can improve system efficiency at low AC line voltage condition, but the energy of the PFC output capacitor effects the hold-up time. The minimum PFC output voltage for required hold-up time is obtained as: VO.PFC 2 t HOLD POUT 2 VO.PFC .HLD CO.PFC (18) Coss + VDS - + VIN - Lm where: tHOLD is the required holdup time; POUT is total nominal output power; VO.PFC.L is the minimum PFC output voltage for required hold-up time; and VO.PFC.HLD is the allowable minimum PFC output voltage during the hold-up time. ID + D VO - Np:Ns + VDS Coss ID IDS min The voltage of transformer primary-side winding is clamped to VO,PFC, so the minimum PFC output voltage during the hold-up time is obtained as: ID IDS VO.PFC .HLD n (VO VF ) VRO 2 VO.PFC VO.PFC 2 VDnom VRO 2 VDSnom VO.PFC 2 VO.PFC /n VO VDnom where VF is the body diode forward voltage of the synchronous rectification MOSFET, which is around 1 V. VRO 2 VO.PFC VDSnom VRO 2 (Design Example) Because the PFC response is very slow, the hold-up time needs to be more than 12 ms to avoid PFC output voltage drop affecting the output voltage at dynamic-load condition. Assuming hold-up time is 12 ms, the VO.PFCmin as: VO.PFC /n VO (19) VO VO.PFC VO Figure 13. Typical Waveforms of QR Flyback Converter Example) Assuming 75 V MOSFET (synchronous rectification) is used for secondary side, with 70% voltage margin: min 2 t HOLD POUT [n (VO VF )]2 CO.PFC 2 12 10 3 90 [12 (19 1)]2 286V 0.9 100 10 6 (Design [STEP-B3] Transformer Design Figure 14 shows the typical switching timing of a quasiresonant converter. The sum of MOSFET conduction time (tON), diode conduction time (tD), and drain voltage falling time (tF) is the switching period (tS). To determine the primary-side inductance (Lm), the following parameters should be determined first. VO. PFC n VO.PFC 400 n 11.94 0.7 75 VO 0.7 75 19 0.7 75 V D nom VO Minimum Switching Frequency (fS.QRmin) Thus, n is determined as 12. The minimum switching frequency occurs at the minimum input voltage and full-load condition, which should be higher than 20 kHz to avoid audible noise. By increasing fS.QRmin, the transformer size can be reduced. However, this results in increased switching losses. Determine fS.QRmin by a trade-off between switching losses and transformer size. Typically fS.QRmin is set around 70 kHz. [STEP-B2] Calculate the Minimum PFC Output Voltage (VO.PFC.L) for Hold-up Time For the PFC output capacitor, it is typical to use 0.5~1 µF per 1 W output power for 400 V PFC output. Meanwhile, it is reasonable to use ~1 µF per 1 W output power for variable output PFC due to the larger voltage drop during the hold-up time than 400 V output. In this example, 100 µF capacitors is selected for the output capacitors (CO.PFC). © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 Falling Time of the MOSFET Drain Voltage (tF) As shown in Figure 14, the MOSFET drain voltage fall time is half of the resonant period of the MOSFET’s effective output capacitance and primary-side inductance. The typical value for tF is 0.6~1.2 µs. www.fairchildsemi.com 8 AN-6920 APPLICATION NOTE Non-Conduction Time of the MOSFET (tOFF) When designing the transformer, the maximum flux density swing in normal operation (B) as well as the maximum flux density in transient (Bmax) should be considered. The maximum flux density swing in normal operation is related to the hysteresis loss in the core, while the maximum flux density in transient is related to the core saturation. FAN6920 has a minimum non-conduction time of MOSFET (5 µs), during which turning on the MOSFET is prohibited. To maximize the efficiency, it is necessary to turn on the MOSFET at the first valley of MOSFET drain-to-source voltage at heavy-load condition. Therefore, the MOSFET non-conduction time at heavy load condition should be larger than 5 µs. The minimum number of turns for the transformer primary side to avoid over temperature in the core is given by: After determining fS.QRmin and tF, the maximum duty cycle is calculated as: Dmax VRO (1 f S .QR min t F ) VRO VO.PFC .L N P min (20) Lm If there is no reference data, use B =0.25~0.30 T. Once the minimum number of turns for the primary side is determined, calculate the proper integer for NS so that the resulting NP is larger than Npmin as: (21) 2 f S .QR min POUT N P n N S N P min Once Lm is determined, the maximum peak current and RMS current of the MOSFET in normal operation are obtained as: I DS PK VO.PFC .L Dmax Lm f S .QR min (22) Dmax 3 (23) I DS RMS I DS PK (1 Dmax ) f S .QR min Once the number of turns of the primary winding is determined, the maximum flux density when the drain current reaches its pulse-by-pulse current limit level should be checked to guarantee the transformer is not saturated during transient or fault condition. The maximum flux density (Bmax) when drain current reaches ILIM is given as: Bmax (25) To guarantee the first valley switching at high line and heavy-load condition, tOFF.H should be larger than 5 µs. Lm I LIM Bsat Ae N P (29) Bmax should be smaller than the saturation flux density. If there is no reference data, use Bsat =0.35~0.40 T. ID Ids (28) where VDDnom is the nominal VDD voltage, the range about 12~20 V, and the VFA is forward-voltage drop of VDD diode, about 1 V. (24) VO.PFC .L VO.PFC .H VRO VO.PFC .H VO.PFC .L VRO VDD VFA NS (VO VF ) nom N AUX The MOSFET non-conduction time at heavy load and higher voltage of PFC output (VO.PFC.H) is obtained as: tOFF .H tOFF .L (27) The number of turns of the auxiliary winding for VDD is given as: The MOSFET non-conduction time at heavy load and low line is obtained as: tOFF .L (26) where B is the maximum flux density swing in Tesla. Then, the primary-side inductance is obtained as: QR (VO.PFC .L Dmax )2 Lm I DS PK Ae B (Design Example) Setting the minimum frequency is 65 kHz and the falling time is 1 µs, and assuming VO.PFC.L=300 V: Vds Dmax tD tOFF tON VRO VRO min (1 f S .QR t F ) VO. PFC .L 240 (1 70 10 3 1 10 6 ) 0.413 240 300 tF ts Figure 14. Switching Timing Sequence of QR Flyback Converter © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 www.fairchildsemi.com 9 AN-6920 (VO.PFC .L Dmax ) 2 Lm 2 f s.QR min [STEP-B3] Design the Valley Detection Circuit PO The valley of MOSFET voltage is detected by monitoring the current flowing out of the DET pin. The typical application circuit is shown as Figure 15 and typical waveforms are shown in Figure 16. The DET pin has upper and lower voltage clamping at 5 V and 0.7 V, respectively. The valley detection circuit is blanked for 5 µs after the MOSFET is turned off. When VAUX drops below zero, VDET is clamped at 0.7 V and current flows out of the DET pin. MOSFET is turned on with 200 ns delay once the current flowing out of DET pin exceeds 30 µA. To guarantee that valley detection circuit is triggered when the DET pin is clamped at 0.7 V, the current flowing through RDET2 should be larger than 30 µA as: 0.95 (300 0.413) 1160H 2 70 103 90 2 I DS APPLICATION NOTE PK VO. PFC .L Dmax min Lm f S .QR 300 0.413 1.53 A 1160 10 6 70 103 tOFF .L (1 Dmax ) 1 0.413 8.39s min 70 103 f S .QR tOFF .H tOFF . L 8.39 10 6 VO. PFC .L VO. PFC . H VRO VO. PFC .H VO. PFC . L VRO 0.7 30 A RDET 2 300 400 240 7.46s 5s 400 300 240 (30) Assuming QP2912 (Ae=144 mm2) core is used and the flux swing is 0.28 T S R L I 1160 10 6 1.53 m DS 44 Ae B 144 106 0.28 SET NP N P n N S 12 3 36 N P 12 4 48 N P Valley Detector IDET DRV 8 Q 17.5V CLR PK min VO.PFC FAN6920 DET Pin Function Block Q OPWM t OFF- MIN (5µs/20.5µs/2.2ms) RCS2 min VDET OVP min DET OVP NP is determined as 48, NS is 4. t OFF Blanking (2.5µs) 2.5V DET IDET 5V IDET 12 1 20 1 4 N AUX 4 20 20 2.6 N AUX 4.2 VAUX NA RDET2 Figure 15. Typical Application Circuit of DET Pin OPWM Thus, NAUX is determined as 3. The number of turns of the high-side driver auxiliary is given as: tOFF-min NAUX.H ≦ NAUX t VAUX N VO A NS NAUX.H is determined as 2. Assuming the pulse-by-pulse current limit for low PFC output voltage is 140% of peak drain current at heavy load: t L I 1160 106 2.14 m LIM 0.36T Ae N P 144 106 48 NA NP VDET N RA VO A N S RDET RA V O . PFC 0.7V Figure 16. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 RDET1 10 VDET 0.7V 12 VFA 20 VFA N S N AUX NS (VO VF ) (VO VF ) Bmax NS NP VFB VO OVP Detection Valley Detection t Waveforms of Valley Detection and VO OVP Detection www.fairchildsemi.com 10 AN-6920 APPLICATION NOTE The output is indirectly monitored for over-voltage protection using the DET pin voltage while the MOSFET is turned off. The ratio of RDET1 and RDET2 should be determined as: 2.5 RDET 2 NA NA 1 VOVP VOVP RDET 1 RDET 2 N S K DET 1 N S (31) where the ratio between RDET1 and RDET2 is obtained as: K DET RDET 1 N A VOVP 1 RDET 2 N S 2.5 (32) For a quasi-resonant flyback converter, the peak-drain current with a given output power decreases as input voltage increases. Thus, constant power limit cannot be achieved by using pulse-by-pulse current limit with constant threshold. FAN6920 has high/low line over-power compensation that reduces the pulse-by-pulse current limit level as input voltage increases. FAN6920 senses the input voltage using the current flowing out of the DET pin while the MOSFET is turned on. The pulse-by-pulse current limit level vs. DET current is depicted in Figure 18. Figure 18. IDET-VLIMIT Curve The relationship between IDET and VLIMIT in the linear region (IDET=100~500 µA) can be approximated as: VLIMIT 877 I DET 0.882 The DET pin current for low-line and high-line PFC output voltages are given as: VO. PFC. L I DET .L NA 0.7 NP RDET 1 VO.PFC .H I DET . H NA 0.7 NP RDET 1 0.7 RDET 2 0.7 RDET 2 Switching Frequency VO.PFC.L NA NP Assuming two-level voltage PFC output: for a given output power, the ratio between drain-peak currents at low line and high line is obtained as: (33) RDET 1 VO.PFC .H NA NP I DS PK .L VO.PFC .H VO.PFC .L VRO I DS PK .H VO.PFC .L VO.PFC .H VRO (34) (36) For a given output power, the ratio between pulse-by-pulse current limit levels at low line and high line is obtained as: RDET 1 N 994 VO.PFC .L A RDET 1 VLIMIT .L NP NA VLIMIT .H 994 V RDET 1 O . PFC . H NP Peak-Drain Current (37) To get a constant power limit, RDET1 should be determined such that Equations (38) and (39) are equal. However, for actual design, it is typical to use 108~115% of Equation (38), considering the pulse-by-pulse turn-off delay and increased PFC output voltage ripple at low line. VIN IDS (35) Once the current-limit threshold voltage is determined with RDET1, the current-sensing resistor value is obtained as: IDS VO.PFC .L Figure 17. Switching Frequency and Peak-Drain Current Change as Input Voltage Increases VLIMIT 877 ( NA 0.7 NP RDET 1 0.7 ) 0.882 RDET 2 (38) The current-sensing resistor value can be obtained from: RCS 2 © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 VLIMIT I DS LIM (39) www.fairchildsemi.com 11 AN-6920 APPLICATION NOTE where VOPD is the drop voltage of photodiode, about 1.2 V; VKA is the minimum cathode to anode voltage of shunt regulator (2.5 V); and CTR is the current transfer rate of the opto-coupler. (Design Example) 0.7 30 A , RDET 2 23.3k RDET 2 Setting the OVP trip point at 22.5 V, K DET PFC Vo RDET 1 N AUX VOVP 3 22.5 1 1 5.75 RDET 2 NS 2.5 4 2.5 FAN6920 Feedback Control Then RDET 1 K DET R RDET 2 134k NS Vo 5 CSPWM I DS V V VRO O. PFC .H O. PFC . L PK . K VO.PFC . L VO. PFC . H VRO I DS PK . L NP RCS2 RBIAS 2R Reset OPWM 400 300 240 1.125 300 400 240 RFB 11 FB R RO1 CF RF CFB RO2 Using 113% of 1.125, 994 VO.PFC . L VLIMIT .L 1.27 VLIMIT .H 994 VO. PFC . H NA RDET 1 NP NA RDET 1 NP Figure 19. Feedback Circuit (Design Example) Assuming CTR is 100%; VO VOPD VKA CTR 1.2 103 RBIAS 3 994 300 RDET 1 18637.5 RDET 1 48 3 24850 RDET 1 994 400 RDET 1 48 RBIAS 330 resistor is selected for RBIAS. The voltage divider resistors for VO sensing are selected as 66.5 k and 10 k. Then, RDET1 = 47.5 k and REDT2=8.25 k. RDET1 and RDET2 are selected from the off-the-shelf components as 150 kΩ and 18 kΩ, respectively. [STEP-B5] Design the Over-Temperature Protection Circuit Then, the pulse by pulse current limit threshold voltage is obtained as: VO.PFC . L VLIMIT 877 ( NA 0.7 NP RDET 1 VO VOPD VKA 19 1.2 2.5 12.75k 1.2 103 1.2 103 The adjustable Over-Temperature Protection (OTP) circuit is shown in Figure 20. As can be seen, a constant sourcing current source (IRT) is connected to the RT pin. Once VRT is lower than 0.8 V for longer than 10 ms debounce time, FAN6920 is latched off. RRT can be determined by: 0.7 ) 0.882 RDET 2 0.474V 0.8V ( RRT RNTC @OT ) 100 A To set current limit level at low line as 115% of IDSPK 0.63 0.27 1.53 A 1.15 (41) FAN6920 Adjustable Over-Temperature Protection & External Protection Triggering IRT=100µA [STEP-B4] Design the Feedback Circuit 12 Figure 19 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R01 and R02 form a voltage divider for output voltage regulation. RF and CF are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB = 100 , CFB = 1 nF) placed from the FB pin to GND can increase stability substantially. The maximum source current of the FB pin is about 1.2 mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of the biasing resistor, RBIAS, is determined as: VO VOPD VKA CTR 1.2 103 RBIAS © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 NTC RRT RT 0.8V 0.5V Debounce Time Latched 100µs 10ms Figure 20. Adjustable Over-Temperature Protection and External Latched-off Function (Design Example) Assuming the resistance of NTC at over- temperature protection point is 4.3 k; 0.8V RRT - 4.3k 3.7k 100 A (40) www.fairchildsemi.com 12 AN-6920 APPLICATION NOTE Final Schematic of Design Example Table 2. This section summaries the final design example. The key system specifications are summarized in Table 1 and the key design parameters are summarized in Table 2. The final schematic is in Figure 21. To have enough hold-up time for VDD during startup, a two-stage circuit is used for VDD. To maximize the efficiency, the synchronous rectification using Fairchild’s FAN6204 is used for the secondary rectifier. PFC Stage PFC Inductor (LBOOST) Turns of PFC Inductor (NBOOST) Turns of ZCD Auxiliary Winding (NZCD) Minimum Switching Frequency (fS.PFCmin) PWM Stage Turns of Primary Inductor of PWM Transformer (NP) Turns of Auxiliary Winding of PWM Transformer (NAUX) Turns of Auxiliary Winding of High-Side Driver Transformer (NAUX.H) Turns Ratio of PWM Transformer (n) Primary Inductor (LP) Minimum Switching Frequency (fs.QRmin) Table 1. System Specifications Input Input Voltage Range Line Frequency Range 90~264 VAC 47~63 Hz Output Output Voltage (Vo) Output Power (Po) 19 V 90 W NBOOST 44T DPFC NCZD 8T CINF2 Q1 RPFC1 9.4MΩ DBOOST CO.PFC 100µF CBOOT 0.1µF NAUX.H 3T DAUX.H RG1 RPFC3 249kΩ 1 VCC IC1: FAN6920 D1 CINF1 1 RANGE HV 16 2 NC 15 COMP 3 INV D2 330nF RCIN1 RCIN2 1.5MΩ 1.5MΩ VIN 13 5 CSPWM RT 12 6 OPFC RVIN1 9.4MΩ VAC RRT 3.7kΩ HO 7 3 LIN VS 6 12 1160 µH 70 kHz LOUT 47nH COUT1 820µF/25V NS 4T COUT2 820µF/25V + VOUT 19V 4 COM LO 5 Q4 10Ω RLPC1 220kΩ DR1 NP 48T RLPC1 8.8kΩ Q3 FB 11 DET 10 RG3 8 OPWM GND 9 10Ω GND 4 RDET2 8.25kΩ RES2 12kΩ RO1 66.5kΩ NA 3T RDET1 47.5kΩ Figure 21. RES 7 AGND 1 2 6 IC4: PC817 DAUX RES1 47.5kΩ RBIAS 330Ω RVIN2 154kΩ CDD 68µF VDD IC3: FAN6204 RCS2 0.27Ω CVIN 2.2µF 5 8 LPC NTC CFB 47nF 3 GATE FAN6204 DR2 7 VDD © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 3T RG2 VB 8 2 HIN CRT 1nF ZCD 14 4 CSPFC 4T Q2 IC2: FAN7382 RCZD 47.5kΩ CCOMP 470nF 48 T RSN CSN 16Ω 2.2nF RPFC2 78.7kΩ RCS1 0.2Ω 450 µH 44 T 8T 40 kHz RHV 150kΩ 10Ω 470nF Key Design Parameters RF CF 1.2kΩ 10nF IC5: KA431 RO2 10kΩ Final Schematic of Design Example www.fairchildsemi.com 13 AN-6920 APPLICATION NOTE Table 3. Bill of Materials Part RPFC1 R PFC2 R PFC3 RVIN1 RVIN2 RZCD RHV RRT RCS1 RCS2 RG1 RG2 RG3 RDET1 RDET2 RCIN1 RCIN2 RLPC1 RLPC2 RRES1 RRES2 RSN RO1 RO2 RBIAS RF CINF1 CINF2 CVIN CCOMP CDD CRT Value Resistor 9.4 M 78.7 k 249 k 9.4 M 154 k 47.5 k 150 k 3.7 k 0.2 027 10 10 10 47.5 k 8.25 k 1.5 M 1.5 M 220 k 8.8 k 47.5 k 12 k 16 66.5 k 10 k 330 1.2 k Capacitor 330 nF 470 nF 2.2 µF 470 nF 68 µF 1 nF Note 1/4 W 1/8 W 1/8 W 1/4 W 1/8 W 1/4 W 1W 1/8 W 2W 2W 1/4 W 1/4 W 1/4 W 1/4 W 1/8 W 1/4 W 1/4 W 1/8 W 1/8 W 1/8 W 1/8 W 1W 1/8 W 1/8 W 1/4 W 1/8 W Part Value CFB CO.PFC CSN CF COUT1 COUT2 CBOOT 47 nF 100 µF 2.2 nF 10 nF 820 µF 820 µF 0.1 µF Diode S1J S1J ES3J ES1H RS1D RS1D ES1H ES1H MOSFET FCB11N60 FCB11N60 FCB11N60 FDB031N08 IC FAN6921MR FAN7382 FAN6204 PC817 KA431 Other TTC104 47 nH D1 D2 DPFC DBOOST DAUX DAUX.H DR1 DR2 Q1 Q2 Q3 Q4 IC1 IC2 IC3 IC4 IC5 XCAP NTC LOUT Note 450 V 25 V 25 V Ultra-Fast Diode Fast Diode Fast Diode Ultra-Fast Diode Ultra-Fast Diode 50 V Lab Note Before modifying or soldering / desoldering the power supply, discharge the primary capacitors through the external bleeding resistor. Otherwise, the PWM IC may be damaged by external high-voltage. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 This device is sensitive to electrostatic discharge (ESD). To improve the production yield, the production line should be ESD protected as required by ANSI ESD S1.1, ESD S1.4, ESD S7.1, ESD STM 12.1, and EOS/ESD S6.1 standards. www.fairchildsemi.com 14 AN-6920 APPLICATION NOTE Printed Circuit Board Layout Printed circuit board layout and design are very important for switching power supplies where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes EMI and prevents the power supply from being disrupted during surge/ESD tests. External driver circuit can shorten MOSFET gate discharge current loop and improve the surge/ESD capability. Current loop constructed by the PFC choke, PFC diode, PFC MOSFET, CBulk, and C2 should be as short as possible. IC Side PWM Stage Reference ground of the INV, COMP, CSPFC, CSPWM, and VDD pins are connected together and then connected to the IC’s GND directly. Reference ground of ZCD, VIN, RT, FB, and DET pins are connected to IC’s GND directly. Small capacitors around the IC should be connected to the IC directly. The trace line of CSPWM, OPFC, and OPWM should not be paralleled and should be close to each other to avoid introducing noise. Connections of IC’s GND, RCS.PWM ground, HV IC’s GND, and auxiliary winding of PWM XFMR: RCS.PWM should be connected to CBulk’s ground directly. Keep it short and wide. Current loop constructed by the CBulk, XFMR, PWM MOSFET, clamp diode, and RCS.PWM should be as short as possible. Ground of photo-coupler should be connected to IC’s GND. On the secondary side, current loop constructed by XFMR, Schottky, and output capacitor should be as short as possible. Connections of Y Capacitor: Approach Approach Auxiliary winding’s ground è IC’s GND è RCS.PWM’s ground (2è1è4) HV IC’s GND è RCS.PWM’s ground (3è4) Approach Ground Loop: System Side PFC Stage Y CAP’s primary ground è C1’s ground (10è9) Auxiliary winding of PFC choke is connected to IC’s GND. RCS.PFC should be connected to C2’s ground singly (6 & 8). 7&2è1è4 3è4 4è5è8 6è8 8 & 10 è 9 VB 10 C1 C2 HO 7 9 VS + 8 + HV IC MMBT2907 5 LL4148 52 GND IN 15 14 13 12 11 10 9 HV N.C. ZCD VIN RANGE COMP INV CSPFC RT CSPWM FB OPFC DET VDD GND OPWM RCS.PWM 6 FAN6920MR 16 LO VDD RCS.PFC 100 1 4 3 2 3 4 5 6 7 + 8 2 1 AC IN Figure 22. Layout Considerations © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 www.fairchildsemi.com 15 AN-6920 APPLICATION NOTE Related Documents FAN6920MR — Highly Integrated Quasi-Resonant Current PWM Controller FAN6204MY — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification FAN7382 — High- and Low-Side Gate Driver AN-6076 — Design and Application Guide of Bootstrap Circuit for High-Voltage Gate –Driver IC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2010 Fairchild Semiconductor Corporation Rev. 1.0.1 • 2/22/13 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 16

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