REI Datasheet MM74C901, MM74C902 Hex Inverting TTL Buffer, Hex Non-Inverting TTL Buffer The MM74C901 and MM74C902 hex buffers employ complementary MOS to achieve wide supply operating range, low power consumption, and high noise immunity. These buffers provide direct interface from PMOS into CMOS or TTL and direct interface from CMOS to TTL or CMOS operating at a reduced VCC supply. Rochester Electronics Manufactured Components Rochester branded components are manufactured using either die/wafers purchased from the original suppliers or Rochester wafers recreated from the original IP. All recreations are done with the approval of the OCM. Parts are tested using original factory test programs or Rochester developed test solutions to guarantee product meets or exceeds the OCM data sheet. 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All Rights Reserved 01202014 To learn more, please visit www.rocelec.com Revised January 1999 MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer General Description Features The MM74C901 and MM74C902 hex buffers employ complementary MOS to achieve wide supply operating range, low power consumption, and high noise immunity. These buffers provide direct interface from PMOS into CMOS or TTL and direct interface from CMOS to TTL or CMOS operating at a reduced VCC supply. ■ Wide supply voltage range: ■ Guaranteed noise margin: ■ High noise immunity: 3.0V to 15V 1.0V 0.45 VCC (typ.) ■ TTL compatibility: Fan out of 2 driving standard TTL Ordering Code: Order Number MM74C901M Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C901N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide MM74C902M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C902N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP and SOIC MM74C901 MM74C902 Top View Top View Logic Diagrams MM74C901 CMOS to TTL Inverting Buffer © 1999 Fairchild Semiconductor Corporation DS005909.prf MM74C902 CMOS to TTL Buffer www.fairchildsemi.com MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer October 1987 MM74C901 • MM74C902 Absolute Maximum Ratings(Note 1) Operating VCC Range −0.3V to VCC + 0.3V Voltage at Any Pin −0.3V to +15V MM74C902 −0.3V to +15V Storage Temperature Range (TS) (Soldering, 10 seconds) 260°C −65°C to +150°C Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Operating Temperature Range (TA) MM74C901, MM74C902, 18V Lead Temperature (TL) Voltage at Any Input Pin MM74C901 3.0V to 15V Absolute Maximum VCC −40°C to +85°C DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS V IN(1) Logical “1” Input Voltage V IN(0) Logical “0” Input Voltage V OUT(1) Logical “1” Output Voltage V CC = 5.0V 3.5 V CC = 10V 8.0 V V V CC = 5.0V V CC = 10V V OUT(0) Logical “0” Output Voltage 1.5 V 2.0 V V CC = 5.0V, IO = −10 µA 4.5 V V CC = 10V, IO = −10 µA 9.0 V V CC = 5.0V 0.5 V V CC = 10V 1.0 V 1.0 µA I IN(1) Logical “1” Input Current V CC = 15V, VIN = 15V I IN(0) Logical “0” Input Current V CC = 15V, VIN = 0V I CC Supply Current V CC = 15V 0.005 −1.0 −0.005 0.05 µA 15 µA 0.8 V TTL TO CMOS V IN(1) Logical “1” Input Voltage V CC = 4.75V V IN(0) Logical “0” Input Voltage V CC = 4.75V V CC − 1.5 V CMOS TO TTL V IN(1) V IN(0) Logical “1” Input Voltage MM74C901 V CC = 4.75V 4.25 V MM74C902 V CC = 4.75V V CC − 1.5 V Logical “0” Input Voltage MM74C901 V CC = 4.75V 1.0 V MM74C902 V CC = 4.75V 1.5 V V OUT(1) Logical “1” Output Voltage V OUT(0) Logical “0” Output Voltage V CC = 4.75V, IO = −800 µA 2.4 V MM74C901 V CC = 4.75V, IO = 2.6 mA 0.4 V MM74C902 V CC = 4.75V, IO = 3.2 mA 0.4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) (MM74C901) I SOURCE I SOURCE I SINK I SINK Output Source Current V CC = 5.0V, VOUT = 0V (P-Channel) T A = 25°C, VIN = 0V Output Source Current V CC = 10V, VOUT = 0V (P-Channel) T A = 25°C, VIN = 0V Output Sink Current V CC = 5.0V, VOUT = VCC (N-Channel) T A = 25°C, VIN = VCC Output Sink Current V CC = 5.0V, VOUT = 0.4V (N-Channel) T A = 25°C, VIN = VCC (MM74C902) www.fairchildsemi.com 2 −5.0 mA −20 mA 9.0 mA 3.8 mA Symbol I SOURCE I SOURCE I SINK I SINK (Continued) Parameter Conditions Output Source Current V CC = 5.0V, VOUT = 0V (P-Channel) T A = 25°C, VIN = VCC Output Source Current V CC = 10V, VOUT = 0V (P-Channel) T A = 25°C, VIN = VCC Output Sink Current V CC = 5.0V, VOUT = VCC (N-Channel) T A = 25°C, VIN = 0V Output Sink Current V CC = 5.0V, VOUT = 0.4V (N-Channel) T A = 25°C, VIN = 0V AC Electrical Characteristics Min Typ Max Units −5.0 mA −20 mA 9.0 mA 3.8 mA (Note 2) TA = 25°C, CL = 50 pF, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units MM74C901 t pd1 t pd0 Propagation Delay Time V CC = 5.0V 38 70 ns to a Logical “1” V CC = 10V 22 30 ns Propagation Delay Time V CC = 5.0V 21 35 ns to a Logical “0” V CC = 10V 13 20 ns C IN Input Capacitance Any Input (Note 3) 14 pF C PD Power Dissipation Capacity Per Buffer (Note 4) 30 pF MM74C902 t pd1 t pd0 Propagation Delay Time V CC = 5.0V 57 90 ns to a Logical “1” V CC = 10V 27 40 ns Propagation Delay Time V CC = 5.0V 54 90 ns to a Logical “0” V CC = 10V 25 40 ns C IN Input Capacitance Any Input (Note 3) 5.0 pF C PD Power Dissipation Capacity Per Buffer (Note 4) 50 pF Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. Typical Application CMOS to TTL or CMOS at a Lower VCC Note: V CC1 = VCC2 3 www.fairchildsemi.com MM74C901 • MM74C902 DC Electrical Characteristics MM74C901 • MM74C902 AC Test Circuit and Switching Time Waveforms CMOS to CMOS Note: Delays measured with input tr, tf = 20 ns. Typical Performance Characteristics Typical Propagation Delay to a Logical “0” for the MM74C901 Typical Propagation Delay to a Logical “1” for the MM74C901 Typical Propagation Delay to a Logical “0” for the MM74C902 Typical Propagation Delay to a Logical “1” for the MM74C902 www.fairchildsemi.com 4 MM74C901 • MM74C902 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-120, 0.150” Narrow Package Number M14A 5 www.fairchildsemi.com MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. 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