REI Datasheet SN54LS224A, SN74LS224A 16x4 Synchronous First-In, First-Out Memories With 3-State Outputs The SN54LS224A and SN74LS224A 64-bit, low-power Schottky memories are organized as 16 words by 4 bits each. They can be expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and m is the number of packages in the horizontal array); however, some external gating is required. For longer words, the input-ready (IR) signals of the first-rank packages and output-ready (OR) signals of the last-rank packages must be ANDed for proper synchronization. A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array at independent data rates. These FIFOs are designed to process data at rates up to 10 MHz in a bit-parallel format, word by word. Rochester Electronics Manufactured Components Rochester branded components are manufactured using either die/wafers purchased from the original suppliers or Rochester wafers recreated from the original IP. All recreations are done with the approval of the OCM. Parts are tested using original factory test programs or Rochester developed test solutions to guarantee product meets or exceeds the OCM data sheet. Quality Overview • • • • ISO-9001 AS9120 certification Qualified Manufacturers List (QML) MIL-PRF-38535 • Class Q Military • Class V Space Level Qualified Suppliers List of Distributors (QSLD) • Rochester is a critical supplier to DLA and meets all industry and DLA standards. Rochester Electronics, LLC is committed to supplying products that satisfy customer expectations for quality and are equal to those originally supplied by industry manufacturers. The original manufacturer’s datasheet accompanying this document reflects the performance and specifications of the Rochester manufactured version of this device. Rochester Electronics guarantees the performance of its semiconductor products to the original OEM specifications. ‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. © 2013 Rochester Electronics, LLC. All Rights Reserved 07112013 To learn more, please visit www.rocelec.com SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array at independent data rates. These FIFOs are designed to process data at rates up to 10 MHz in a bit-parallel format, word by word. 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC UNCK OR Q0 Q1 Q2 Q3 CLR 2 1 UNCK 3 VCC NC SN54LS224A . . . FK PACKAGE (TOP VIEW) 5 17 Q0 NC 6 16 NC D1 7 15 Q1 D2 8 14 9 10 11 12 13 Q2 D0 Q3 OR 4 NC 20 19 18 LDCK CLR The SN54LS224A and SN74LS224A 64-bit, low-power Schottky memories are organized as 16 words by 4 bits each. They can be expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and m is the number of packages in the horizontal array); however, some external gating is required. For longer words, the input-ready (IR) signals of the first-rank packages and output-ready (OR) signals of the last-rank packages must be ANDed for proper synchronization. 1 OE description OE IR LDCK D0 D1 D2 D3 GND IR D D SN54LS224A . . . J PACKAGE SN74LS224A . . . N PACKAGE (TOP VIEW) D3 D D D D D Independent Synchronous Inputs and Outputs 16 Words by 4 Bits Each 3-State Outputs Drive Bus Lines Directly Data Rates up to 10 MHz Fall-Through Time 50 ns Typical Data Terminals Arranged for Printed Circuit Board Layout Expandable Using External Gating Packaged in Standard Plastic (N) and Ceramic (J) 300-mil DIPs, and Ceramic Chip Carriers (FK) GND D NC – No internal connection The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions. IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty and UNCK is high. A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR and OR outputs. The SN74LS224A is characterized for operation from 0°C to 70°C. The SN54LS224A is characterized over the full military temperature range of –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 logic symbol† FIFO 16 × 4 OE CLR 1 9 EN5 CT = 0 CT < 16 LDCK CTR 2 & 3 Z2 CT > 0 & 15 D1 D2 D3 OR Z3 2 4 14 – CT = 0 D0 IR + /C1 3 UNCK 2 1D & V4 4, 5 13 5 12 6 11 7 10 Q0 Q1 Q2 Q3 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. This symbol is functionally accurate but does not show the details of implementation; for these details, see the logic diagram. The symbol represents the memory as if it were controlled by a single counter whose content is the number of words stored at the time. Output data is invalid when the counter content (CT) is 0. Pin numbers shown are for the J and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 logic diagram (positive logic) OE CLR LDCK 1 9 3 S 1D C1 S 2D C2 Ring Counter CTR 1 DIV 16 2 COMP 3 4 + 5 6 Write 7 Address 8 9 10 11 12 CT = 1 13 14 15 16 Q=P+1 16 P P=Q+1 Q P=Q EMPTY 2 14 UNCK 15 R 3D C3 R 4D C4 Ring Counter CTR 1 2 DIV 16 3 4 5 + 6 Read 7 8 Address 9 10 11 12 13 CT = 1 14 15 16 IR OR 16 16 RAM 16 × 4 1 1A 16 16 2A 1 16 EN C5 4 D0 5 D1 6 D2 D3 7 1A,5D 2A ≥1 13 12 11 10 Q0 Q1 Q2 Q3 Pin numbers shown are for the J and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 schematics of inputs and outputs EQUIVALENT OF CLR INPUT EQUIVALENT OF OTHER INPUTS VCC VCC 13 kΩ NOM 19 kΩ NOM Input Input TYPICAL OF IR AND OR OUTPUTS TYPICAL OF Q OUTPUTS VCC VCC 120 Ω NOM 100 Ω NOM Output Output 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 timing diagram CLR LDCK UNCK D0–D3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1 W2 W1 W2 W15 W16 IR OR Q0–Q3 ÎÎÎÎ ÎÎÎÎ Invalid Word 1 Word 2 ÎÎÎ ÎÎÎ Invalid Word 1 Word 2 Initialize Load Two Words Unload Two Words Load Until Full Unload absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Off-state output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA: N package (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W N package (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-3. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 recommended operating conditions (see Note 4) SN54LS224A VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage IOH High level output current High-level IOL Low level output current Low-level SN74LS224A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 2 2 Q outputs IR, OR Q outputs IR, OR UNIT V V 0.7 0.8 –1 –2.6 –0.4 –0.4 12 24 4 8 V mA mA TA Operating free-air temperature –55 125 0 70 °C NOTE 4: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock or improper operation of the internal read and write pointers. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIK VOH SN54LS224A TYP‡ MAX TEST CONDITIONS† PARAMETER VCC = MIN, Q outputs VCC = MIN IR, OR VCC = MIN, MIN II = –18 mA IOH = –2.6 mA IOH = –1 µA IOH = –0.4 mA SN74LS224A TYP‡ MAX MIN –1.5 –1.5 2.4 2.4 2.5 V 3.4 2.7 Q outputs VCC = MIN IR OR IR, VCC = MIN IOL = 4 mA IOL = 8 mA Q outputs VCC = MAX, VCC = MAX, VO = 2.7 V VO = 0.4 V II IIH VCC = MAX, VCC = MAX, VI = 7 V VI = 2.7 V 20 20 µA IIL VCC = MAX, VI = 0.4 V –0.4 –0.4 mA IOZH IOZL IOS§ Q outputs Q outputs IR, OR VCC = MAX 0.4 3.4 IOL = 12 mA IOL = 24 mA VOL 0.25 0.4 0.25 0.4 0.35 0.5 0.25 0.4 0.35 0.5 –20 –20 µA 0.1 0.1 mA –30 –130 –30 –130 –20 –100 –20 –100 84 135 84 135 87 155 87 155 Outputs disabled 89 155 89 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. 155 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 µA 20 Outputs low VCC = MAX V 20 Outputs high ICC 6 V 3.4 3.3 0.25 UNIT mA mA SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 timing requirements over recommended operating conditions (see Note 4 and Figure 1) SN54LS224A MIN tw tsu Pulse duration Setup time MAX SN74LS224A MIN LDCK high 60 60 LDCK low 15 15 UNCK low 30 30 UNCK high 30 30 CLR low 20 20 Data to LDCK↓ 50 50 LDCK↓ before UNCK↓ 50 50 UNCK↑ before LDCK↑ 50 50 MAX UNIT ns ns th Hold time Data from LDCK↓ 0 10 ns NOTE 4: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCK and UNCK clock inputs. Any excessive noise or glitching on the clock inputs that violates the VIL, VIH, or minimum pulse-duration limits can cause a false clock or improper operation of the internal read and write pointers. switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH tPHL tPLH tPLH tPHL tPLH tPLH tPHL tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ FROM (INPUT) LDCK↓ LDCK↑ LDCK↓ UNCK↑ UNCK↓ UNCK↑ TO (OUTPUT) IR RL = 2 kΩ, kΩ CL = 15 pF OR RL = 2 kΩ, CL = 15 pF OR kΩ RL = 2 kΩ, CL = 15 pF IR RL = 2 kΩ, CL = 15 pF RL = 2 kΩ, kΩ CL = 15 pF IR CLR↓ TEST CONDITIONS OR LDCK↓ Q RL = 667 Ω, CL = 45 pF UNCK↑ Q RL = 667 Ω Ω, CL = 45 pF OE↑ Q RL = 667 Ω Ω, CL = 45 pF OE↓ Q RL = 667 Ω Ω, CL = 5 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX 25 40 36 50 48 70 29 45 28 45 49 70 36 55 25 40 34 50 54 80 45 70 22 35 21 35 16 30 18 30 UNIT ns ns ns ns ns ns ns ns ns 7 SN54LS224A, SN74LS224A 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS SDLS023D – JANUARY 1991 – REVISED MARCH 2002 PARAMETER MEASUREMENT INFORMATION VCC RL S1 From Output Under Test (see Note B) CL (see Note A) 5 kΩ TEST S1 S2 tPZL tPZH tPLZ/tPHZ tPLH/tPHL Closed Open Closed Closed Open Closed Closed Closed 1.3 V 1.3 V S2 LOAD CIRCUIT 3V Timing Input High-Level Pulse 1.3 V 0V th tsu Data Input tw 3V 1.3 V Low-Level Pulse 1.3 V 0V 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enabling) 1.3 V 1.3 V 0V tPLZ tPZL Waveform 1 (see Note B) [1.5 V tPHZ VOL 0.5 V 0.5 V 1.3 V 1.3 V 0.3 V tPLH In-Phase Output 1.3 V tPHL VOH 1.3 V 3V Output Control 1.3 V tPZH Waveform 2 (see Note B) 1.3 V [1.5 V tPLH VOH Out-of-Phase Output (see Note C) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS tPHL VOH 1.3 V VOL 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr < 15 ns, tf < 6 ns, ZO ≈ 50 Ω. D. All diodes are 1N916 or 1N3064. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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