RENESAS R2J20602NP-G3

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April 1st, 2010
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R2J20602NP
Integrated Driver – MOS FET (DrMOS)
REJ03G1480-0500
Rev.5.00
Mar 12, 2010
Description
The R2J20602NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier
diode (SBD), eliminating the need for an external SBD for this purpose.
Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the
package standard “Integrated Driver – MOS FET (DrMOS)” proposed by Intel Corporation.
Features












Built-in power MOS FET suitable for applications with 12 V input and low output voltage
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
VIN operating-voltage range: 16 V max
High-frequency operation (above 1 MHz) possible
Large average output current (Max. 40 A)
Achieve low power dissipation (About 4.4 W at 1 MHz, 25 A)
Controllable driver: Remote on/off
Built-in Schottky diode for bootstrapping
Low-side drive voltage can be independently set
Small package: QFN56 (8 mm  8 mm  0.95 mm)
Terminal Pb-free/Halogen-free
Outline
VCIN
BOOT
GH
1
VIN
14
15
56
Driver
Tab
High-side MOS
Tab
Reg5V
DISBL#
VSWH
MOS FET Driver
Low-side MOS Tab
PWM
43
CGND VLDRV
GL
PGND
28
42
29
(Bottom view)
QFN56 package 8 mm × 8 mm
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 1 of 14
R2J20602NP
Block Diagram
VCIN
Reg5V
UVL
BOOT
GH
Driver chip
SBD
5 V Gen.
DISBL#
VIN
2 µA
High-side
MOS FET
CGND
Level shifter
VSWH
VCIN
PWM
Input logic
(TTL level)
(3 state in)
Overlap
protection
Low-side
MOS FET
PGND
CGND
VLDRV
Notes: 1. Truth table for the DISBL# pin.
DISBL# Input
“L”
“Open”
“H”
Driver Chip Status
Shutdown (GL, GH = “L”)
Shutdown (GL, GH = “L”)
Enable (GL, GH = “Active”)
2. Output signal from the UVL block
"H"
For activation
UVL Output
Logic Level
For shutdown
"L"
VL
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 2 of 14
VH
VCIN
GL
R2J20602NP
VIN
VIN
VIN
VIN
VIN
VIN
VIN
GH
CGND
BOOT
VCIN
VLDRV
NC
CGND
Pin Arrangement
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VIN
15
56
PWM
VIN
16
55
DISBL#
VIN
17
54
Reg5V
VIN
18
53
NC
VIN
19
52
GL
VIN
20
51
CGND
VSWH
21
50
VSWH
PGND
22
49
VSWH
PGND
23
48
VSWH
PGND
24
47
VSWH
PGND
25
46
VSWH
PGND
26
45
VSWH
PGND
27
44
VSWH
PGND
28
43
VSWH
VIN
CGND
32
33
34
35
36
37
38
39
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
40
41
42
VSWH
31
VSWH
30
VSWH
29
PGND
VSWH
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
CGND
NC
VLDRV
Pin No.
1, 6, 51, Tab
2, 53
3
Description
Control signal ground
No connect
Low side gate supply voltage
VCIN
BOOT
GH
VIN
VSWH
4
5
7
8 to 20, Tab
21, 40 to 50, Tab
Control input voltage (+12 V input)
Bootstrap voltage pin
High side gate signal
Input voltage
Phase output/Switch output
PGND
GL
Reg5V
DISBL#
PWM
22 to 39
52
54
55
56
Power ground
Low side gate signal
+5 V logic power supply output
Signal disable
PWM drive logic input
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 3 of 14
Remarks
Should be connected to PGND externally
For 5 V to 12 V gate drive voltage for Low side
gate driver
Driver Vcc input
To be supplied +5 V through internal SBD
Pin for Monitor
Pin for Monitor
Disabled when DISBL# is “L”
R2J20602NP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Power dissipation
DISBL# voltage
PWM voltage
Symbol
Pt(25)
Pt(110)
Iout
VIN (DC)
VIN (AC)
VCIN (DC)
VCIN (AC)
VLDRV (DC)
VLDRV (AC)
VSWH (DC)
VSWH (AC)
VBOOT (DC)
VBOOT (AC)
Vdisble
Vpwm
Reg5V current
Ireg5V
Rating
25
8
40
–0.3 to +16
20
–0.3 to +16
20
–0.3 to +16
20
16
20
22
25
–0.3 to VCIN
–0.3 to +5.5
–0.3 to +0.3
–10 to +0.1
Operating junction temperature
Storage temperature
Tj-opr
Tstg
–40 to +150
–55 to +150
Average output current
Input voltage
Supply voltage
Low side driver voltage
Switch node voltage
BOOT voltage
Notes: 1.
2.
3.
4.
5.
6.
Units
W
W
A
V
°C
°C
V
V
V
V
V
V
V
mA
Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.
Rated voltages are relative to voltages on the CGND and PGND pins.
For rated current, (+) indicates inflow to the chip and (–) indicates outflow.
This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode).
This rating is when UVL (Under Voltage Lock out) is effective (lock out mode).
The specification values indicated “AC” are limited within 100 ns.
Safe Operating Area
45
Condition
VOUT = 1.3 V
VIN = 12 V
VLDRV = 5 V
VCIN = 12 V
L = 0.45 µH
fPWM = 1 MHz
Average Output Current (A)
40
35
30
25
20
15
10
5
0
0
20
40
60
80
100
PCB Temperature (°C)
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 4 of 14
120
140
160
Note
1
1
2
2, 6
2
2, 6
2
2, 6
2
2, 6
2
2, 6
2
2, 4
2, 5
3
R2J20602NP
Electrical Characteristics
(Ta = 25C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Supply
PWM
Input
5V
Regulator
DISBL#
Input
Note:
Item
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VCIN bias current
Symbol
VH
VL
dUVL
ICIN
Min
7.0
6.6
—
10.5
Typ
7.4
7.0
0.4 *1
14.0
Max
7.8
7.4
—
18.5
Units
V
V
V
mA
VLDRV bias current
ILDRV
35.5
44.0
52.5
mA
PWM rising threshold
PWM falling threshold
PWM input resistance
VH-PWM
VL-PWM
RIN-PWM
3.7
0.9
12.5
4.0
1.2
25
4.3
1.5
37.5
V
V
k
VH – VL
fPWM = 1 MHz,
ton-PWM = 125 ns
fPWM = 1 MHz,
ton-PWM = 125 ns
4V–1V
IPWM (VPWM = 4 V) – IPWM (VPWM = 1 V)
Tri-state shutdown window
Shutdown hold-off time
Output voltage
Line regulation
VIN-SD
tHOLD-OFF
Vreg
Vreg-line
VL-PWM
—
4.95
–10
—
240 *1
5.2
0
VH-PWM
—
5.45
10
V
ns
V
mV
Load regulation
Disable threshold
Vreg-load
VDISBL
–10
0.9
0
1.2
10
1.5
mV
V
Enable threshold
VENBL
Input current
IDISBL
1.9
0.5
2.4
2.0
2.9
5.0
V
A
1. Reference values for design. Not 100% tested in production.
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 5 of 14
Test Conditions
VCIN = 12 V to 16 V
Ireg = 0 to 10 mA
DISBL# = 1 V
R2J20602NP
Typical Application
+12 V
+5 V to 12 V
+12 V
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20602NP
PWM
PGND
CGND
GH
GL
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20602NP
PGND
PWM
PWM1
PWM
control
circuit
CGND
GH
GL
PWM2
+1.3 V
PWM3
PWM4
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20602NP
PWM
PGND
CGND
GH
GL
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20602NP
PGND
PWM
CGND
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 6 of 14
GH
GL
Signal Power
GND GND
R2J20602NP
Test Circuit
VB
VLDRV
VCIN
A
A
A
IIN
ILDRV
V VIN
ICIN
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V
VSWH
R2J20602NP
5 V pulse
PGND
PWM
CGND
GH
Electric
load
IO
GL
Averaging
Average Output Voltage
V
VO
circuit
Note: PIN = IIN × VIN + ILDRV × VLDRV + ICIN × VCIN
POUT = IO × VO
Efficiency = POUT / PIN
PLOSS(DrMOS) = PIN – POUT
Ta = 27°C
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 7 of 14
R2J20602NP
Typical Data
Power Loss vs. Input Voltage
1.3
VIN = 12 V
VCIN = 12 V
VLDRV = 5 V
VOUT = 1.3 V
fPWM = 1 MHz
L = 0.45 µH
0
5
10
Normalized Power Loss
@ VIN = 12 V
Power Loss (W)
Power Loss vs. Output Current
12
11
10
9
8
7
6
5
4
3
2
1
0
15
20
25
30
35
VCIN = 12 V
VLDRV = 5 V
VOUT = 1.3 V
1.2 fPWM = 1 MHz
L = 0.45 µH
Iout = 25 A
1.1
1.0
0.9
0.8
40
5
6
7
Input Voltage (V)
Output Current (A)
Power Loss vs. Switching Frequency
Power Loss vs. Output Voltage
1.4
1.5
1.3
VIN = 12 V
VCIN = 12 V
VLDRV = 5 V
fPWM = 1 MHz
L = 0.45 µH
Iout = 25 A
VLDRV = 5 V
1.2
1.1
1.0
0.9
0.8
0.8
VIN = 12 V
1.3 VCIN = 12 V
Normalized Power Loss
@ fpwm = 1 MHz
Normalized Power Loss
@ VOUT = 1.3 V
1.4
9 10 11 12 13 14 15 16
8
1.2 VOUT = 1.3 V
L = 0.45 µH
1.1 Iout = 25 A
1.0
0.9
0.8
0.7
0.6
1.6
2.4
3.2
4.0
Output Voltage Vout (V)
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 8 of 14
4.8
0.5
250
500
750
1000
1250
Switching Frequency (kHz)
1500
R2J20602NP
Typical Data (cont.)
Power Loss vs. VLDRV
Power Loss vs. Output Inductance
1.20
1.6
1.15
1.5 VCIN = 12 V
Normalized Power Loss
@ VLDRV = 5 V
Normalized Power Loss
@ L = 0.45 µH
VIN = 12 V
1.10
1.05
1.00
0.95 VIN = 12 V
VCIN = 12 V
0.90 VLDRV = 5 V
VOUT = 1.3 V
0.85 fPWM = 1 MHz
Iout = 25 A
VOUT = 1.3 V
= 1 MHz
f
1.4 LPWM
= 0.45 µH
Iout = 25 A
1.3
1.2
1.1
1.0
0.9
0.80
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.8
5
6
7
8
Output Inductance (µH)
VLDRV (V)
Average ICIN vs. Switching Frequency
30
VIN = 12 V
VCIN = 12 V
VOUT = 1.3 V
200 L = 0.45 µH
Iout = 0 A
VIN = 12 V
VCIN = 12 V
25 VOUT = 1.3 V
L = 0.45 µH
Iout = 0 A
Average ICIN (mA)
Average ILDRV (mA)
Average ILDRV vs. Switching Frequency
250
150
100
50
0
250
VLDRV = 5 V
VLDRV = 12 V
VLDRV = 16 V
500
750
1000
1250
Switching Frequency (kHz)
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 9 of 14
9 10 11 12 13 14 15 16
1500
20
15
10
5
0
250
VLDRV = 5 V
VLDRV = 12 V
VLDRV = 16 V
500
750
1000
1250
Switching Frequency (kHz)
1500
R2J20602NP
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET,
low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
Driver
The driver has two types of power-supply voltage input pin, VCIN and VLDRV. VCIN supplies the operating voltage
to the internal logic circuit. The low-side driving voltage is applied to VLDRV, so setting of the gate-driving voltage for
the low-side MOS FET is independent of the voltage on VCIN. The VLDRV setting voltage is from 5 V to 16 V.
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN
is 7.4 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 7.0 V or less. The
signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator
does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and
the 5 V regulator is not disabled.
VCIN
L
H
H
H
VLDRV
>5V
>5V
>5V
>5V
DISBL#

L
H
Open
Reg5V
0
5V
5V
5V
Driver State
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
Disable (GL, GH = L)
Voltages from –0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor,
etc., to pull the DISBL# line up to VCIN are both possible.
The built-in 5 V regulator is a series regulator with temperature compensation. The voltage output by this regulator
determines the operating voltage of the internal logic and gate-voltage swing for the high-side MOS FET. A ceramic
capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V pin.
The PWM pin is the signal input pin for the driver chip. The input-voltage range is –0.3 V to (Reg5V + 3 V). When
the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is
low.
PWM
L
H
GH
L
H
GL
H
L
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 10 of 14
R2J20602NP
The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route
from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function
operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has
been entered and GH and GL have become low, a PWM input voltage of 4.0 V or more is required to make the circuit
return to normal operation.
240 ns(tHOLD-OFF)
PWM
240 ns(tHOLD-OFF)
4.0 V
1.2 V
GH
GL
240 ns(tHOLD-OFF)
PWM
240 ns(tHOLD-OFF)
4.0 V
1.2 V
GH
GL
Figure 1
For the high-side driver, the BOOT pin is the power-supply voltage pin and voltage VSWH provides a standard for
operation of the high-side driving circuit. Consequently, the difference between the voltage on the BOOT and VSWH
pins becomes the gate swing for the high-side MOS FET. Connect a bootstrap capacitor between the BOOT pin and the
VSWH pin. Since the Schottky barrier diode (SBD) is connected between the BOOT and Reg5V pins, this bootstrap
capacitor is charged up to 5 V. When the high-side MOS FET is turned on, voltage VSWH becomes equal to VIN, so
VBOOT is boosted to VSWH + 5 V.
The GH and GL pins are the gate-monitor pins for each MOS FET.
MOS FETs
The MOS FETs incorporated in R2J20602NP are highly suitable for synchronous-rectification buck conversion. For
the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the
low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 11 of 14
R2J20602NP
PCB Layout Example
Figure 2 shows an example of a PCB layout for the R2J20602NP in application. The several ceramic capacitors (e.g. 10
F) close to VIN and PGND can be expected to decrease switching noise and improve efficiency. In that case, all
sections of the GND pattern must be connected with other PCB layers via low impedances. Moreover, the wide VSWH
pattern can be expected to have the effect of dissipating heat from the low-side MOS FET.
When R2J20602NP is mounted on small circuit boards, such as those for point-of-load (POL) applications, heating of
the device can be alleviated by adding thermal via-holes under the VIN and VSWH pads.
10 µF
Vin
10 µF
10 µF
GND
10 µF
GND
BOOT
1 µF
VCIN
1 µF
VSWH
Reg. 5 V
VLDRV
PWM
1 µF
DISBL#
GND
0.1 µF
To inductor
GND
To
BOOT
Via hole
Figure 2 R2J20602NP PCB Layout Example (Top View)
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 12 of 14
R2J20602NP
Footprint Example
(Unit: mm)
4.30
3.60
3.10
0.45
0.90
0.3
3.10
56
Figure 3 Footprint Example
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 13 of 14
4.30
3.60
3.10
0.5
0.85
0.50
3.10
1
R2J20602NP
Package Dimensions
JEITA Package Code
P-HVQFN56-8x8-0.50
RENESAS Code
PVQN0056KA-A
Previous Code
—
MASS[Typ.]
0.2g
HD
D
42
29
29
43
28
28
3.0
0.0
E
HE
e
43
42
0.3
1.0
C
4
0.
Reference
Symbol
Lp
14
14
ZD
A1
A
c1
c
3.0
Index mark
56
y
1
b
b1
0.0
0.4
1.0
1
15
3.0
15
ZE
56
3.0
Dimension in Millimeters
Min Nom Max
D 7.95 8.00 8.05
E
7.95 8.00 8.05
A2
A
0.95
A1 0.005
b
0.20 0.25 0.30
b1
0.23
e
0.50
Lp 0.40 0.50 0.60
x
y
0.05
y1
t
HD 8.10 8.20 8.30
HE 8.10 8.20 8.30
ZD
0.75
ZE
0.75
c
0.17 0.22 0.27
c1
0.20
Ordering Information
Part Name
R2J20602NP#G3
Quantity
2500 pcs
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
Page 14 of 14
Shipping Container
Taping Reel
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