RT8058 1MHz, 2A, High Efficiency PWM Step-Down DC/DC Converter General Description Features The RT8058 is a current mode PWM step-down converter. The chip is ideal for fixed frequency and low ripple applications over full range of load conditions. Its input z 0.6V Reference Allows Low Output Voltage z voltage range is from 2.6V to 5.5V with a constant 1MHz switching frequency that allows it to adopt tiny, low cost capacitors and inductors with 2mm or less in height making it ideal for single-cell Li-lon/polymer battery applications. The low on resistance internal MOSFET can achieve high efficiency without the need of external schottky diodes in wide operating ranges and the output voltage is adjustable from 0.6V to 5V that can provide up to 2A load current. The RT8058 operates at 100% duty cycle for low dropout operation that extends battery life in portable devices. z The RT8058 is available in a WQFN-16L 3x3 package. z Low Dropout Operation : 100% Duty Cycle 2A Load Current <2μ μA Shutdown Current Up to 95% Efficiency No Schottky Diode Required 1MHZ Constant Switching Frequency Low RDS(ON) Internal Switches Internally Compensated Internal Soft-Start Over temperature Protection Short Circuit Protection Small 16-Lead WQFN Package RoHS Compliant and 100% Lead (Pb)-Free Ordering Information RT8058 z z z z z z z z z z Applications z Package Type QW : WQFN-16L 3x3 (W-Type) z Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) z z z z Portable Instruments Microprocessors and DSP Core supplies Cellular Telephones Wireless and DSL Modems Digital Cameras PC Cards Note : Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. DS8058-05 April 2011 NC LX ments of IPC/JEDEC J-STD-020. LX LX ` (TOP VIEW) 16 15 14 13 PGND PGND PGND FB 1 12 PVDD 2 11 PVDD PVDD VDD PGND 3 10 17 4 5 6 7 9 8 EN NC RoHS compliant and compatible with the current require- NC ` Pin Configurations GND Richtek products are : WQFN-16L 3x3 www.richtek.com 1 RT8058 Typical Application Circuit RT8058 10,11,12 VIN 2.6V to 5.5V 7 9 CIN 10µF PVDD LX 13,14,15 L1 3.3µH EN VDD GND 5 VOUT 1.2V/2A R1 100k FB 4 COUT1 22µF COUT2 22µF R2 100k PGND 1, 2, 3, Exposed Pad (17) Functional Pin Description Pin No. Pin Name 1, 2, 3 PGND 17 (Exposed Pad) 4 FB 5 GND 6, 8, 16 NC 7 EN 9 VDD 10, 11, 12 PVDD 13, 14, 15 LX Pin Function Power Ground. Connect this pin close to the (–) terminal of CIN and COUT. The exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. Feedback Input Pin. Receives the feedback voltage from a resistive divider connected across the output. Signal Ground. Return the feedback resistive dividers to this ground, which in turn connects to PGND at one point. No Internal Connection. Enable pin. A logical high level at this pin enables the converter, while a logical low level causes the converter to shut down. Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD is equal to PVDD. Keep the voltage difference between VDD and PVDD less than 0.5V. Power Input Supply of converter power stage. Decouple this pin to PGND with a capacitor. Internal Power MOSFET Switches Output of converter. Connect this pin to the inductor. Function Block Diagram PVDD ISEN Slope Com OSC 0.6V FB EA Output Clamp OC Limit Driver Int-SS 0.3V LX Control Logic OT PGND VREF POR Temp-SEN GND VDD www.richtek.com 2 EN DS8058-05 April 2011 RT8058 Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Input Voltage VDD, PVDD ------------------------------------------------------------------------------------LX Pin Switch Voltage ---------------------------------------------------------------------------------------------------Other I/O Pin Voltage ----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-6L 3x3 -------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA ------------------------------------------------------------------------------------------------------WQFN-16L 3x3, θJC -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z −0.3V to 6V −0.3V to 6V −0.3V to 6V 1.471W 68°C/W 7°C/W 260°C −65°C to 150°C 150°C 2kV 200V (Note 4) Supply Input Voltage ------------------------------------------------------------------------------------------------------ 2.6V to 5.5V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = VPVDD = 3.6V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VIN 2.6 -- 5.5 V Feedback Voltage VFB 0.582 0.6 0.618 V Active, No Load -- 3.4 -- mA Active, Not Switching, VFB = 0.5V -- 340 -- μA Shutdown, EN = 0 -- -- 2 μA 2.3 2.43 2.55 V -- 150 -- mV 0.75 1.0 1.25 MHz DC Bias Current (PVDD, VDD total) Under voltage Lockout Threshold UVLO VDD Rising VDD Hysteresis Switching Frequency Oscillator Frequency fOSC EN High-Level Input Voltage VEN_H 1.4 -- -- V EN Low-Level Input Voltage VEN_L -- -- 0.4 V Switch On Resistance, High RDS(ON)_P IOUT = 200mA -- 142 210 mΩ Switch On Resistance, Low RDS(ON)_N IOUT = 200mA -- 96 160 mΩ Peak Current Limit ILIM 2.2 3 -- A Output Voltage Line Regulation VIN = 2.6V to 5.5V -- 0.05 -- %/V Output Voltage Load Regulation ILOAD = 0AÆ2A -- 0.15 -- %/A DS8058-05 April 2011 www.richtek.com 3 RT8058 Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 4 DS8058-05 April 2011 RT8058 Typical Operating Characteristics Efficiency vs. Output Current Efficiency vs. Output Current 100 100 VIN = 5V 90 VIN = 3.3V 70 VIN = 5V 80 Efficiency (%) Efficiency (%) 80 90 60 50 40 30 20 VIN = 3.3V 70 60 50 40 30 20 10 10 VOUT = 1.8V, L = 3.3μH, COUT = 22μFx2 0 0 500 1000 1500 VOUT = 1.2V, L = 3.3μH, COUT = 22μFx2 0 2000 0 500 Output Current (mA) 0.6010 1.1998 0.6008 Reference Voltage (V) Output Voltage (V) 1.1996 VIN = 5V 1.1992 1.1990 VIN = 3.3V 1.1986 2000 Reference Voltage vs. Input Voltage Output Voltage vs. Outout Current 1.1988 1500 Output Current (mA) 1.2000 1.1994 1000 1.1984 0.6006 0.6004 0.6002 0.6000 0.5998 0.5996 0.5994 0.5992 1.1982 0.5990 1.1980 0 250 500 750 2.7 1000 1250 1500 1750 2000 3.1 3.5 3.9 4.3 4.7 5.1 5.5 Input Voltage (V) Outout Current (mA) Frequency vs. Temperature Output Voltage vs. Temperature 1100 1.205 1.203 1050 Frequency (kHz) Output Voltage (V) 1.201 1.199 1.197 1.195 1.193 1.191 1000 950 900 1.189 1.187 VIN = 3.6V 1.185 -50 -25 0 25 50 Temperature (°C) DS8058-05 April 2011 75 100 125 VIN = 3.6V, VOUT = 1.2V, IOUT = 0A 850 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 5 RT8058 Quiescent Current vs. Input Voltage Quiescent Current vs. Temperature 450 Quiescent Current (uA) Quiescent Current (uA) 450 400 350 300 250 400 350 300 VIN = 3.6V 250 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -50 -25 3.2 3.3 Peak Current limit (A) Peak Current limit (A) 3.5 3.1 3.0 2.9 VOUT = 1.2V 2.8 3.5 3.9 4.3 75 100 4.7 5.1 2.9 2.7 VIN = 3.6V, VOUT = 1.2V 2.5 -50 5.5 -25 0 25 50 75 100 Input Voltage (V) Temperature (°C) Load Transient Response Load Transient Response 125 VIN = 3.3V, VOUT = 1.2V, IOUT = 0A to 2A VOUT (50mV/Div) VOUT (50mV/Div) IOUT (1A/Div) IOUT (1A/Div) Time (25μs/Div) 125 3.1 VIN = 3.3V, VOUT = 1.2V, IOUT = 0A to 1A www.richtek.com 6 50 Peak Current limit vs. Temperature Peak Current limit vs. Input Voltage 3.3 3.1 25 Temperature (°C) Input Voltage(V) 2.7 0 Time (25μs/Div) DS8058-05 April 2011 RT8058 Load Transient Response Load Transient Response VIN = 3.3V, VOUT = 1.2V, IOUT = 0.5A to 1.5A VIN = 3.3V, VOUT = 1.2V, IOUT = 1A to 2A VOUT (50mV/Div) VOUT (50mV/Div) IOUT (1A/Div) IOUT (1A/Div) Time (25μs/Div) Time (25μs/Div) Load Transient Response Load Transient Response VIN = 5V, VOUT = 1.2V, IOUT = 0A to 1A VIN = 5V, VOUT = 1.2V, IOUT = 0A to 2A VOUT (50mV/Div) VOUT (50mV/Div) IOUT (1A/Div) IOUT (1A/Div) Time (25μs/Div) Time (25μs/Div) Load Transient Response Load Transient Response VIN = 5, VOUT = 1.2V, IOUT = 1A to 2A VIN = 5V, VOUT = 1.2V, IOUT = 0.5A to 1.5A VOUT (50mV/Div) VOUT (50mV/Div) IOUT (1A/Div) IOUT (1A/Div) Time (25μs/Div) DS8058-05 April 2011 Time (25μs/Div) www.richtek.com 7 RT8058 Output Ripple Noise Output Ripple Noise VIN = 3.3V, VOUT = 1.2V, IOUT = 1.5A VIN = 3.3V, VOUT = 1.2V, IOUT = 2A VOUT (5mV/Div) VOUT (5mV/Div) VLX (5V/Div) VLX (5V/Div) IOUT (1A/Div) IOUT (1A/Div) Time (500ns/Div) Time (500ns/Div) Output Ripple Noise Output Ripple Noise VIN = 5V, VOUT = 1.2V, IOUT = 2A VIN = 5V, VOUT = 1.2V, IOUT = 1.5A VOUT (5mV/Div) VOUT (5mV/Div) VLX (5V/Div) VLX (5V/Div) IOUT (1A/Div) IOUT (1A/Div) Time (500ns/Div) Time (500ns/Div) Power On from EN Power On from EN VIN = 3.3V, VOUT = 1.2V, RLOAD = 0.6Ω VIN = 5V, VOUT = 1.2V, RLOAD = 0.6Ω VEN (2V/Div) VEN (2V/Div) VOUT (1V/Div) VOUT (1V/Div) IOUT (2A/Div) IOUT (2A/Div) Time (500μs/Div) www.richtek.com 8 Time (500μs/Div) DS8058-05 April 2011 RT8058 Soft-Start & Inrush Current Soft-Start & Inrush Current VIN = 5V, VOUT = 1.2V, IOUT = 1.5A VIN = 3.3V, VOUT = 1.2V, IOUT = 1.5A VIN (2V/Div) VIN (2V/Div) VOUT (1V/Div) VOUT (1V/Div) I IN (1A/Div) I IN (1A/Div) Time (2.5ms/Div) DS8058-05 April 2011 Time (2.5ms/Div) www.richtek.com 9 RT8058 Application Information Function Description The RT8058 is a 1MHz constant frequency, current mode PWM step-down converter. High switching frequency and high efficiency make it suitable for applications where high efficiency and small size are critical. Frequency compensation is done internally. The output voltages are set by external dividers returned to the FB pin. The output voltage can be set from 0.8V to 5V. The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1. V OUT R1 FB RT8058 R2 GND Figure 1. Setting the Output Voltage Main Control Loop During normal operation, the internal top power switch (P-MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the peak inductor current reach the value defined by the output voltage of the error amplifier. The error amplifier adjusts its output voltage by comparing the feedback signal from a resistor divider on the FB pin with an internal 0.6V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises its output voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-MOSFET) turns on until the beginning of the next clock cycle. Soft-Start / Enable For convenience of power up sequence control, RT8058 has an enable pin. Logic high at EN pin will enable the converter. When the converter is enabled, the clamped error amplifier output ramps up during 1024-clock period to increase the current provided by converter until the output voltage reach the target voltage. If EN is kept at high during Vin applying, RT8058 will be enabled when VDD surpass Under Voltage Lockout threshold. Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation : VOUT = VREF x (1+ R1/R2) where VREF equals to 0.6V typical. www.richtek.com 10 Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In RT8058, however, separated inductor current signal is used to monitor over current condition and this keeps the maximum output current relatively constant regardless of duty cycle. Dropout Operation When input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-MOSFET and the inductor. Low Supply Operation The RT8058 is designed to operate down to an input supply voltage of 2.7V. One important consideration at low input supply voltages is that the RDS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8058 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. DS8058-05 April 2011 RT8058 Short Circuit Protection At overload condition, current mode operation provides cycle-by-cycle current limit to protect the internal power switches. When the output is shorted to ground, the inductor current will decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. If the FB voltage is smaller than 0.3V after the completion of soft-start period, under voltage protection (UVP) will lock the output to high-z to protect the converter. UVP lock can only be cleared by recycling the input power. Thermal Protection If the junction temperature of RT8058 reaches certain temperature (150°C), both converters will be disabled. The RT8058 will be re-enabled and automatically initializes internal soft start when the junction temperature drops below 110 °C. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. ⎡V ⎤ ⎡ V ⎤ ΔIL = ⎢ OUT ⎥ × ⎢1 − OUT ⎥ × f L V IN ⎦ ⎣ ⎦ ⎣ Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔIL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ VOUT ⎤ L=⎢ ⎥ × ⎢1 − V ⎥ × Δ f I L(MAX) ⎦ ⎣ IN(MAX) ⎦ ⎣ Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, DS8058-05 April 2011 forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This result in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don' t radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs. size requirements and any radiated field/EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : IRMS = IOUT(MAX) VOUT VIN VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. www.richtek.com 11 RT8058 The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎡ 1 ⎤ ΔVOUT ≤ ΔIL ⎢ESR + 8fCOUT ⎥⎦ ⎣ The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. www.richtek.com 12 Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : VDD quiescent current and I2R losses. The VDD quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VDD quiescent current is due to two components : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from VDD to ground. The resulting ΔQ/Δt is the current out of VDD that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VDD and thus their effects will be more pronounced at higher supply voltages. DS8058-05 April 2011 RT8058 derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 1.6 Maximum Power Dissipation (W) 2. I2R losses are calculated from the resistances of the internal switches, R SW and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows : RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1−D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Four Layers PCB 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 Ambient Temperature (°C) Thermal Considerations For continuous operation, do not exceed the maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : Figure 2. Derating Curves for RT8058 Package Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8058. ` A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND. PD(MAX) = ( TJ(MAX) - TA ) / θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8058, where T J(MAX) is the maximum junction temperature of the die and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-16L 3x3 packages, the thermal resistance θJA is 68°C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : ` ` LX node is with high frequency voltage swing and should be kept small area. Keep all sensitive small-signal nodes away from LX node to prevent stray capacitive noise pickup. ` Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVDD, VDD, VOUT, PGND, GND, or any other DC rail in your system). PD(MAX) = ( 125°C − 25°C ) / 68°C/W = 1.471 W for WQFN-16L 3x3 packages The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8058 packages, the Figure 2 of DS8058-05 April 2011 Connect the terminal of the input capacitor(s), CIN, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs. ` Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and GND. www.richtek.com 13 RT8058 Figure 3. Top Layer Table 1. Recommended Inductors Component Series Supplier T AIYO YUDEN NR 4018 Murata LQH66S TDK SLF7045T Sumida CDRH5D16 GOTREND GTSD53 Figure 4. Bottom Layer Inductance (µH) 3.3 3.3 3.3 3.3 3.3 DCR (mΩ) 70 22 20 36 34 Current Rating (m A) 2000 2600 2500 2600 2360 Dimensions (mm) 4 x 4 x 1.8 6.3 x 6.3 x 4.7 7 x 7 x 4.5 5.8 x 5.8 x 1.8 5 x 5 x 2.8 Table 2. Recommended Capacitors for CIN and COUT Component Supplier Part No. Capacitance (µF) Case Size TDK C3225X5R0J226M 22 1210 TDK C2012X5R0J106M 10 0805 Panasonic ECJ4YB1A226M 22 1210 Panasonic ECJ4YB1A106M 10 1210 TAIYO YUDEN LMK325BJ226ML 22 1210 TAIYO YUDEN JMK316BJ226ML 22 1206 TAIYO YUDEN JMK212BJ106ML 10 0805 www.richtek.com 14 DS8058-05 April 2011 RT8058 Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8058-05 April 2011 www.richtek.com 15