RT9173B 2A Bus Termination Regulator General Description The RT9173B regulator is designed to convert voltage supplies ranging from 1.7V to 6V into a desired output voltage of which adjusted by two external voltage divider resistors. The regulator is capable of sourcing or sinking up to 2A of current while regulating an output voltage to within 40mV. The RT9173B, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for DDR SDRAM. Current limits in both sourcing and sinking mode, plus onchip thermal shutdown make the circuit tolerant of the output fault conditions. The RT9173B are available in the popular 5-lead TO-252 and fused SOP-8 (the multiple VCNTL pins on the SOP-8 package are internally connected but lowest thermal resistance) surface mount packages. Ordering Information RT9173B Package Type S : SOP-8 L5 : TO-252-5 Note : Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. Features z z z z z z z z z z z z Support Both DDR I (1.25VTT) and DDR II (0.9VTT) Requirements SOP-8 and TO-252-5 Packages Capable of Sourcing and Sinking Current Current-limiting Protection Thermal Protection Integrated Power MOSFETs Generates Termination Voltages for SSTL-2 High Accuracy Output Voltage at Full-Load Adjustable VOUT by External Resistors Minimum External Components Shutdown for Standby or Suspend Mode Operation with High-impedance Output RoHS Compliant and 100% Lead (Pb)-Free Applications z z z z z DDR Memory Termination Supply Active Termination Buses Desktop PC/AGP Graphics Set Top Box/IPC Supply Splitter Pin Configurations (TOP VIEW) VIN 8 VCNTL GND 2 7 VCNTL REFEN 3 6 VCNTL VOUT 4 5 VCNTL SOP-8 5 VOUT 4 REFEN 3 VCNTL (TAB) 2 GND 1 VIN TO-252-5 DS9173B-10 April 2011 www.richtek.com 1 RT9173B Typical Application Circuit VCNTL = 3.3V VIN = 2.5V RTT CCNTL R1 VCNTL CIN VIN RT9173B REFEN VOUT 2N7002 EN GND R2 COUT RDUMMY R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing condition RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present CIN = 470μF (Low ESR), CCNTL = 47μF Test Circuit 3.3V 2.5V VCNTL VIN RT9173B REFEN VOUT 1.25V VOUT GND COUT V IL Figure 1. Output Voltage Tolerance, ΔVOUT 3.3V 1.25V A 2.5V VCNTL VIN RT9173B REFEN VOUT VOUT 1.25V 0V 0.2V GND RL COUT V RL and COUT Time deleay Figure 2. Current in Shutdown Mode, ΙSHDN www.richtek.com 2 DS9173B-10 April 2011 RT9173B 1.25V 3.3V 2.5V VCNTL VIN RT9173B REFEN VOUT VOUT A GND COUT V IL Figure 3. Current Limit for High Side, ΙCLHIGH Power Supply with Current Limit 2.5V 3.3V VCNTL 1.25V A VIN RT9173B REFEN VOUT IL GND VOUT COUT V Figure 4. Current Limit for Low Side, ΙCLLOW 2.5V VCNTL VIN RT9173B REFEN VOUT 1.25V VREFEN 3.3V GND 0.2V VOUT RL COUT V 1.25V VOUT 0V VOUT would be low if VREFEN < 0.2V VOUT would be high if VREFEN > 0.6V RL and COUT Time deleay Figure 5. REFEN Pin Shutdown Threshold, VTRIGGER DS9173B-10 April 2011 www.richtek.com 3 RT9173B Functional Pin Description Pin Name Pin Function VIN Power Input GND Ground VCNTL Gate Drive Voltage REFEN Reference Voltage Input and Chip Enable VOUT Output Voltage Function Block Diagram VCNTL VIN Current Limiting Sensor REFEN CNTL VOUT Thermal GND www.richtek.com 4 DS9173B-10 April 2011 RT9173B Absolute Maximum Ratings z z z z z z z (Note 1) Input Voltage ---------------------------------------------------------------------------------------------------------- 7V Power Dissipation, PD @ TA = 25°C SOP-8 ------------------------------------------------------------------------------------------------------------------ 0.625W TO-252 ----------------------------------------------------------------------------------------------------------------- 1.471W Package Thermal Resistance (Note 2) SOP-8, θJA ------------------------------------------------------------------------------------------------------------ 160°C/W SOP-8, θJC ------------------------------------------------------------------------------------------------------------ 23°C/W TO-252, θJA ------------------------------------------------------------------------------------------------------------ 68°C/W TO-252, θJC ----------------------------------------------------------------------------------------------------------- 8°C/W Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C Junction Temperature ----------------------------------------------------------------------------------------------- 150°C Storage Temperature Range --------------------------------------------------------------------------------------- –65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V Recommended Operating Conditions z (Note 4) Junction Temperature Range -------------------------------------------------------------------------------------- –40°C to 125°C Electrical Characteristics (VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10μF (Ceramic), TA = 25°C unless otherwise specified) Parameter Symbol Output Offset Voltage VOS Load Regulation ΔV LOAD Test Conditions Min Typ Max Unit IOUT = 0A, Figure 1 (Note 5) −20 0 20 mV −20 0 20 mV 1.7 2.5/1.8 -- IL : 0A → 2A, Figure 1 IL : 0A → -2A VIN Keep VCNTL ≥ V IN on operation power VCNTL on and power off sequences 3 3.3/5 6 Operating Current of VCNTL ICNTL No Load -- 1 2.5 mA Current In Shutdown Mode ISHDN V REFEN < 0.2V, RL = 180Ω, Figure 2 -- 50 90 μA ILIM Figure 3,4 2.2 2.6 -- A Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V 125 170 -- °C Thermal Shutdown Hysteresis ΔT SD 3.3V ≤ VCNTL ≤ 5V -- 35 -- °C Output = High, Figure 5 0.6 -- -- Output = Low, Figure 5 -- -- 0.2 Input Voltage Range (DDR I/II) V Short Circuit Protection Current limit Over Temperature Protection Shutdown Function Shutdown Threshold Trigger DS9173B-10 April 2011 V www.richtek.com 5 RT9173B Note 1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. θ JA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the center of VCTRL pins (Lead 6 & 7) for SOP-8 packages. Note 3. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. www.richtek.com 6 DS9173B-10 April 2011 RT9173B Typical Operating Characteristics Source Current Limit vs. Temperature Source Current Limit vs. Temperature 3.8 3.8 3.4 VIN = 1.8V, VCNTL = 5V 3 2.6 VIN = 2.5V, VCNTL = 5V Source current (A) Source current (A) 3.4 VIN = 1.8V, VCNTL = 3.3V 3 2.6 VIN = 2.5V, VCNTL = 3.3V 2.2 2.2 1.8 1.8 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 95 110 125 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Sink Current Limit vs. Temperature Sink Current Limit vs. Temperature 3.8 3.8 VIN = 1.8V, VCNTL = 5V 3.4 3 VIN = 2.5V, VCNTL = 5V 2.6 Sink current (A) Sink current (A) 3.4 3 VIN = 1.8V, VCNTL = 3.3V 2.6 VIN = 2.5V, VCNTL = 3.3V 2.2 2.2 1.8 1.8 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 95 110 125 5 Turn-On Threshold vs. Temperature 35 50 65 80 95 110 125 Turn-Off Threshold vs. Temperature 0.5 0.5 0.45 VIN = 2.5V, VCNTL = 5V 0.4 VIN = 2.5V, VCNTL = 3.3V 0.35 0.3 Threshold Voltage (V) Threshold Voltage (V) 20 Temperature (°C) Temperature (°C) 0.45 0.4 0.35 VIN = 2.5V, VCNTL = 5V VIN = 2.5V, VCNTL = 3.3V 0.3 -40 -25 -10 5 20 35 50 65 80 Temperature (°C) DS9173B-10 April 2011 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.richtek.com 7 RT9173B Output Voltage vs. Temperature Output Voltage vs. Temperature 1.26 VIN = 1.8V VCNTL = 3.3V 0.905 Output Voltage (V) Output Voltage (V) 0.91 0.9 0.895 VIN = 2.5V VCNTL = 3.3V 1.255 1.25 1.245 1.24 0.89 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 95 110 125 5 Output Current (A) -100 Output Transient Voltage (mV) 0 2 0 -2 65 80 95 110 125 VREFEN = 0.9V 100 Swing Frequency : 1kHz VIN = 1.8V VCNTL = 5V 0 -100 2 0 -2 Time (250us/Div) 1.25VTT @ 2A Transient Response 1.25VTT @ 2A Transient Response VREFEN = 1.25V 100 Swing Frequency : 1kHz 0 -100 2 0 -2 Time (250us/Div) www.richtek.com 8 VIN = 2.5V VCNTL = 3.3V Output Transient Voltage (mV) Time (250us/Div) Output Current (A) Output Transient Voltage (mV) Output Current (A) Output Transient Voltage (mV) Output Current (A) VIN = 1.8V VCNTL = 3.3V 50 0.9VTT @ 2A Transient Response 0.9VTT @ 2A Transient Response VREFEN = 0.9V 35 Temperature (°C) Temperature (°C) 100 Swing Frequency : 1kHz 20 VREFEN= 1.25V 100 Swing Frequency : 1kHz VIN = 2.5V VCNTL = 5V 0 -100 2 0 -2 Time (250us/Div) DS9173B-10 April 2011 RT9173B Output Short-Circuit Protection Source 4 3 2 1 VIN = 2.5V VCNTL = 3.3V 12 Output Short Circuit (A) Output Short Circuit (A) 5 10 8 6 4 2 0 Force the output shorted to ground Time (1ms/DIV) DS9173B-10 April 2011 Sink VIN = 2.5V VCNTL = 3.3V 6 0 Output Short-Circuit Protection Force the output shorted to VDDQ Time (1ms/DIV) www.richtek.com 9 RT9173B Application Information Internal parasitic diode VREFEN Avoid forward-bias internal parasitic diode, VOUT to VCNTL, and VOUT to VIN, the VOUT should not be forced some voltage respect to ground on this pin while the VCNTL or VIN is disappeared. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? Make sure that VCNTL >= VIN in all conditions including power on and off. As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure 6 and 7 show the RDS(ON) over temperature of RT9173B in SOP-8 and TO-252 packages respectively. The minimum dropout voltage could be obtained by the product of RDS(ON) and output current. For thermal consideration, please refer to the relative sections. RDS(ON) vs. Temperature 0.45 R0 BUS(0) R1 BUS(1) RT9173B VOUT R2 R3 R4 REFEN R5 0.43 SOP-8 VCNTL = 3.3V 0.41 0.39 R DS(ON) (Ω) Terminator Resistor GND Figure 6 In notebook application, using RichTek’ s Patent “ Distributed Bus Terminator Topology” with choosing RichTek’ s product is encouraged. Distributed Bus Terminating Topology 0.37 0.35 0.33 0.31 0.29 BUS(2) 0.27 BUS(3) 0.25 BUS(4) 0.23 -50 BUS(5) -25 0 BUS(6) VOUT R7 R8 R9 25 50 75 100 125 Temperature (°C) R6 RT9173B VIN RT9173B REFEN VOUT R2 Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. VCNTL R1 RDS(ON) vs. Temperature BUS(7) 0.48 BUS(8) 0.45 BUS(9) TO-252 VCNTL = 3.3V RN R(N+1) BUS(N) BUS(N+1) General Regulator The RT9173B could also serves as a general linear regulator. The RT9173B accepts an external reference voltage at REFEN pin and provides output voltage regulated to this reference voltage as shown in Figure 6, where VOUT = VREF x R1/(R1+R2) www.richtek.com 10 R DS(ON) (Ω) 0.42 0.39 0.36 0.33 0.30 0.27 0.24 -50 -25 0 25 50 75 100 125 Temperature (°C) DS9173B-10 April 2011 RT9173B Place the input bypass capacitor as close as possible to the RT9173B. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between RT9173B and the preceding power converter. Thermal Consideration An internal thermal limiting circuitry shuts down the RT9173B when junction temperature is over 170°C. This protects the device during overload conditions. It is noted that the thermal limiting circuitry is not intended for normal operation. For maximum reliability, the junction temperature should not exceed absolute maximum operation temperature 125°C during normal operation. The power dissipation should be well considered to keep the junction temperature within the specification. The power dissipation in RT9173B is calculated as: Since the multiple VCTRL pins of the SOP-8 package are internally shorted and connected to lead frame, it is efficient to dissipate the heat by adding cooper area on VCTRL footprint. Figure 7 shows the relation about thermal resistance θJA vs. copper area on a standard JEDEC 51-7 (4 layer, 2S2P) thermal test board at TA = 25°C. The corresponding maximum power dissipation is shown in Figure 8. For example, with 10mm x 10mm cooper area, we can obtain the lower thermal resistance about 45°C/W. The power maximum dissipation can be calculated as: PD(MAX) = (125 − 25°C) / 45 = 2.22W (SOP-8) θJA vs. Copper Area 100 90 80 θ JA (°C/W) Input Capacitor and Layout Consideration 70 60 50 PD = (VIN − VOUT) x IOUT + VIN x IQ 40 The maximum power dissipation can be calculated by following formula: SOP-8 30 0 PD(MAX) = ( TJ(MAX) -TA ) /θJA PD(MAX) = (125 − 25°C) / 68 = 1.471W (TO-252) 30 40 50 60 70 80 90 100 Copper Area (mm ) Figure 7 Power Dissipation vs. Copper Area 100 TJ = 125°C 90 80 2 Copper Area (mm 2 )) PD(MAX) = (125 − 25°C) / 160 = 0.625W (SOP-8) 20 2 Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance θJA highly depends on IC package, PCB layout , the rate of surroundings airflow. θJA for SOP-8 package is 160°C/W and TO-252 package is 68°C/W on standard JEDEC 51-3 (single layer, 1S) thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula: 10 70 TA = 65°C 60 TA = 55°C 50 TA = 25°C 40 30 20 10 SOP-8 0 0 0.5 1 1.5 2 2.5 3 Power Dissipation (W) Figure 8 DS9173B-10 April 2011 www.richtek.com 11 RT9173B Outline Information E C2 R b3 L3 T V S D H L b P L2 A Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 2.184 2.388 0.086 0.094 b 0.381 0.889 0.015 0.035 b3 4.953 5.461 0.195 0.215 C2 0.457 0.889 0.018 0.035 D 5.334 6.223 0.210 0.245 E 6.350 6.731 0.250 0.265 H 9.000 10.414 0.354 0.410 L 0.508 1.780 0.020 0.070 L2 L3 0.508 Ref. 0.889 2.032 0.020 Ref. 0.035 0.080 P 1.270 Ref. 0.050 Ref. V 5.200 Ref. 0.205 Ref. R 0.200 1.500 0.008 0.059 S 2.500 3.400 0.098 0.134 T 0.500 0.850 0.020 0.033 5-Lead TO-252 Surface Mount Package www.richtek.com 12 DS9173B-10 April 2011 RT9173B H A M J B F C I D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9173B-10 April 2011 www.richtek.com 13