Technical Data Sheet

®
RT9059
3A, Ultra-Low Dropout Voltage Regulator
General Description
Features
The RT9059 is a high performance positive voltage regulator
designed for use in applications requiring very low input
voltage and very low dropout voltage at up to 3A. It operates
with a VIN as low as 1V and VDD voltage 3V with
programmable output voltage as low as 0.8V. The RT9059
features ultra low dropout, ideal for applications where
VOUT is very close to VIN. Additionally, it has an enable
pin to further reduce power dissipation while shutdown.
The RT9059 provides excellent regulation over variations
in line, load and temperature. The RT9059 provides a power
good signal to indicate if the voltage level of VO reaches

Output Current up to 3A

High Accuracy ADJ Voltage 1.5%
Dropout Voltage 350mV @ 3A Typically
VOUT Power Good Signal
VOUT Pull Low Resistance when Disable
Current Limiting Protection
Thermal Shutdown Protection
RoHS Compliant and Halogen Free
90% of its rating value.

Ordering Information
Pin Configurations
RT9059(-






Applications

Notebook PC Applications
Motherboard Applications
)
(TOP VIEW)
Package Type
SP: SOP-8 (Exposed Pad-Option 1)
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
PGOOD
EN
2
VIN
3
VDD
4
GND
8
GND
7
ADJ/NC
6
VOUT
5
NC
9
Note :
Richtek products are :

RoHS compliant and compatible with the current require-
VOUT
VOUT
VOUT
ADJ/NC
PGOOD
1
2
3
4
5
GND
SOP-8 (Exposed Pad)
None : Adjustable Output
Fixed Output Voltage Code
15 : 1.5V
18 : 1.8V
25 : 2.5V
11
10
9
8
7
6
VDD
VIN
VIN
VIN
EN
WDFN-10L 3x3
ments of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9059-08 April 2014
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT9059
Typical Application Circuit
RT9059
Chip Enable
PGOOD
EN
VDD
CVDD
1µF
VOUT
VIN
COUT
10µF
R1
RPGOOD
VIN
CIN
10µF
ADJ
GND
PGOOD
EN
RPGOOD
VDD
CVDD
1µF
CIN
10µF
RT9059
Chip Enable
R2
VOUT = 0.8 x (R1+R2)/R2
Figure 1. Adjustable Voltage Regulator
VOUT
COUT
10µF
GND
Figure 2. Fixed Voltage Regulator
Functional Pin Description
Pin No.
SOP-8 (Exposed Pad)
Adjustable
Output Voltage
WDFN-10L 3x3
Pin Name
Pin Function
Fixed Output
Adjustable Fixed Output
Voltage
Output Voltage
Voltage
1
1
5
5
PGOOD
2
2
6
6
EN
Enable Control Input.
3
3
7, 8. 9
7, 8. 9
VIN
Supply Input Voltage.
4
4
10
10
VDD
Supply Voltage of Control Circuit.
5
5, 7
--
4
NC
No Internal Connection.
6
6
1, 2, 3
1, 2, 3
VOUT
Output Voltage.
7
--
4
--
ADJ
Output Voltage Setting.
VOUT = V REF x (R1+R2)/R2.
8,
8,
11
11
GND
9 (Exposed Pad) 9 (Exposed Pad) (Exposed Pad) (Exposed Pad)
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2
Power Good Open Drain Output.
Ground. The exposed pad must be
soldered to a large PCB and
connected to GND for maximum
power dissipation.
is a registered trademark of Richtek Technology Corporation.
DS9059-08 April 2014
RT9059
Function Block Diagram
EN
VDD
VIN
VOUT
ADJ
VREF
EN
UVLO
OCP
RSENSE
MOS
Driver
+
EA
-
VOUT
150
Thermal
Protection
Soft-Start
PGOOD
+
PGOOD
Comparator
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DS9059-08 April 2014
DELAY
GND
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RT9059
Absolute Maximum Ratings












(Note 1)
Supply Input Voltage, VIN to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 10ms ----------------------------------------------------------------------------------------------------------------------Control Voltage, VDD to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 10ms ----------------------------------------------------------------------------------------------------------------------Output Voltage, VOUT --------------------------------------------------------------------------------------------------Chip Enable Voltage, EN -----------------------------------------------------------------------------------------------Adjust Voltage, ADJ -----------------------------------------------------------------------------------------------------Power Good Voltage, VPGOOD -----------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------------WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------------SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------------WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) -----------------------------------------------------------------------------------------------------
Recommended Operating Conditions




−0.3V to 6V
−0.3V to 7V
−0.3V to 6V
−0.3V to 7V
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
2.96W
2.95W
33.7°C/W
5.4°C/W
33.8°C/W
8.9°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------Control Voltage, VDD (VDD > VOUT + 1.5V) -------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------
1V to 5V
3V to 5.5V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VDD = 5V, CIN = COUT = 10μF, CVDD = 1μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
3
--
5.5
V
VDD Operation Range
VDD
VDD POR Threshold
VPOR_VDD
VDD Rising
2.4
2.7
3
V
VDD POR Falling Hysteresis
VPOR_VDD
VDD Falling
0.15
0.2
--
V
Input Voltage Range
VIN
1
--
5.5
V
VIN POR Threshold
VPOR_VIN
VIN Rising
0.7
0.8
0.9
V
VIN POR Falling Hysteresis
VPOR_VIN
VIN Falling
0.15
0.2
0.25
V
Quiescent Current
IQ
EN On, No Load
--
0.6
1.2
mA
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DS9059-08 April 2014
RT9059
Parameter
Reference Voltage
Symbol
Test Conditions
VREF
Fixed Output Voltage
Accuracy
Min
Typ
Max
Unit
0.788
0.8
0.812
V
1.5
--
1.5
%
VOUT Load Regulation
VLOAD
IOUT = 1mA to 3A,
VIN = VOUT+1V
--
0.5
1
%
OUT Line Regulation
VLINE
VDD = 3.6V to 5.5V,
VIN = VOUT+1V to 5V, IOUT = 1mA
--
0.2
0.6
%
Dropout Voltage
VDROP
IOUT = 2A
--
250
350
IOUT = 3A
--
350
450
3.1
3.6
4.2
A
mV
Current Limit
ILIM
VIN = 3.6V
Short Circuit Current
ISC
VOUT < 0.2V
1
1.4
1.8
A
VOUT Pull Low Resistance
RPULL
VEN = 0V
--
150
--

Thermal Shutdown
Temperature
TSD
--
160
--
ºC
--
90
--
ºC
Thermal Shutdown Recovery
TSDR
Temperature
PGOOD Rising Threshold
VTH_PGOOD
VOUT Rising
--
90
--
%
PGOOD Hysteresis
VTH_PGOOD VOUT Falling
--
10
--
%
PGOOD Delay Time

--
1
1.5
ms
PGOOD Sink Capability
VPGOOD
--
0.2
0.4
V
EN Input
Voltage
ISINK = 10mA
Logic-High
VIH
1.2
--
--
Logic-Low
VIL
--
--
0.4
0.3
0.85
1.4
ms
EN Delay Time
V
EN Pin Bias Current
IEN
VEN = 5V
--
12
--
A
VDD Pin Shutdown Current
ISHDN_VDD
VEN = 0V
--
--
1
A
VIN Pin Shutdown Current
ISHDN_VIN
VEN = 0V, VIN = 5V
--
--
1
A
Inrush Current
IINRUSH
VOUT = 1.8V, COUT = 10F,
ILoad = 1A
--
0.5
--
A
Soft-Start Time
tSS
1.9
2.8
3.75
ms
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS9059-08 April 2014
is a registered trademark of Richtek Technology Corporation.
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RT9059
Typical Operating Characteristics
Current Limit vs. Temperature
4.2
0.5
4.0
Current Limit (A)
Quiescent Current (mA)
Quiescent Current vs. Temperature
0.6
0.4
0.3
0.2
3.8
3.6
3.4
3.2
0.1
VDD = 5V, VIN = 3V
VDD = 5V, VIN = 3V
3.0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
Temperature (°C)
75
100
125
VREF Voltage vs. Temperature
500
0.90
450
0.85
400
0.80
VREF Voltage (V)
Dropout Voltage (mV)
50
Temperature (°C)
Dropout Voltage vs. Temperature
350
300
250
200
0.75
0.70
0.65
0.60
150
VOUT = 1.2V, VDD = 5V, IOUT = 3A
100
0.55
VDD = 5V, VIN = 3V
0.50
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
EN Threshold Voltage vs. Temperature
PGOOD Delay Time vs. Temperature
900
1.2
800
1.1
700
1.0
EN Voltage (V)
PGOOD Delay Time (µs)
25
600
500
400
300
200
Rising
0.9
Falling
0.8
0.7
0.6
0.5
0.4
100
VDD = 5V, VIN = 2V
0.3
0.2
0
-50
-25
0
25
50
75
100
Temperature (°C)
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125
-50
-25
0
25
50
75
100
125
Temperature (°C)
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DS9059-08 April 2014
RT9059
Dropout Voltage vs. Load Current
VDD POR Threshold Voltage vs. Temperature
400
3.0
Rising
2.8
350
2.4
Dropout Voltage (mV)
VDD Voltage (V)
2.6
Falling
2.2
2.0
1.8
1.6
1.4
300
250
200
150
100
50
1.2
0
1.0
-50
-25
0
25
50
75
100
0
125
1
1.5
2
2.5
Load Current (A)
PSRR vs. Frequency
Load Transient Response
20
3
VIN = 2.2V, VDD = 5V
VOUT = 1.2V, COUT = 10μF
0
PSRR (dB)
0.5
Temperature (°C)
VOUT
(20mV/Div)
-20
-40
-60
IOUT
(1A/Div)
-80
-100
10
100
1000
10000
100000
Time (1ms/Div)
1000000
Frequency (Hz)
VIN Line Transient Response
VDD Line Transient Response
VIN
(1V/Div)
VOUT
(20mV/Div)
VOUT
(20mV/Div)
VDD = 5V, COUT = 10μF
Time (200μs/Div)
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DS9059-08 April 2014
VDD
(1V/Div)
VIN = 2V, COUT = 10μF
Time (200μs/Div)
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7
RT9059
Start Up from VDD
VDD
(2V/Div)
Start Up from VIN
VIN
(1V/Div)
PGOOD
(1V/Div)
PGOOD
(1V/Div)
VOUT
(1V/Div)
VIN = 3V, IOUT = 0A
COUT = 10μF
Time (2ms/Div)
VOUT
(1V/Div)
VDD = 5V, IOUT = 0A
COUT = 10μF
Time (2ms/Div)
Start Up from Enable and PGOOD Delay
EN
(2V/Div)
PGOOD
(1V/Div)
VOUT
(1V/Div)
IOUT
(1A/Div)
VIN = 3V, VDD = 5V,
IOUT = 1.5A, COUT = 10μF
Time (1ms/Div)
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RT9059
Applications Information
Adjustable Mode Operation
where VREF is the reference voltage (0.8V typical).
Enable
The RT9059 goes into shutdown mode when the EN pin
is in the logic low condition. During this condition, the
pass transistor, error amplifier, and band gap are turned
off, reducing the supply current to 1μA typical. The RT9059
goes into operation mode when the EN pin is in the logic
high condition. If the EN pin is floating, please notice the
RT9059 internal initial logic level. For RT9059, the EN pin
function pulls low level internally. So the regulator will be
turned off when EN pin is floating.
Input Capacitor
Good bypassing is recommended from input to ground to
improve AC performance. A 10μF input capacitor or greater
located as close as possible to the IC is recommended.
Output Capacitor
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDOs
application. The RT9059 is designed specifically to work
with low ESR ceramic output capacitor in space-saving
and performance consideration. Using a ceramic capacitor
which value is at least 10μF on the RT9059 output ensures
stability. The RT9059 still works well with output capacitor
of other types due to the wide stable ESR range. Figure 3
shows the curves of allowable ESR range as a function of
load current for various output capacitor values. Output
capacitor of larger capacitance can reduce noise and
improve load transient response, stability, and PSRR. The
output capacitor should be located not more than 0.5 inch
from the VOUT pin of the RT9059 and returned to a clean
analog ground.
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Region of Stable COUT ESR vs. Output Current
10
Region of Stable COUT ESR (Ω)
The output voltage of RT9059 is adjustable from 0.8V to
VIN by external voltage divider resisters as shown in Typical
Application Circuit (Figure 1). The value of resisters R1
and R2 should be more than 10kΩ to reduce the power
loss. The output voltage can be calculated by the following
equation :
R1 

VOUT  VREF  1 

 R2 
Unstable Region
1
stable Region
0.1
0.01
Unstable Region
0.001
VDD = 5V, VIN = 2.2V, VOUT = 1.2V
R1 = 12kΩ, R2 = 24kΩ, CIN = COUT = 10μF, X5R
0.0001
0
0.5
1
1.5
2
2.5
3
Output Current (A)
Figure 3. Region of Stable COUT ESR vs. Output Current
Current Limit
The RT9059 contains an independent current limit and
the short circuit current protection to prevent unexpected
applications. The current limit monitors and controls the
pass transistor's gate voltage, minimum limiting the output
current to 3.1A typical. When the output voltage is less
than 0.2V, the short circuit current protection starts the
current fold back function and maintains the loading
current at maximum 1.8A. The output can be shorted to
ground indefinitely without damaging the part.
Power Good
The power good function is an open-drain output. Connect
100kΩ pull up resistor to VOUT to obtain an output voltage.
The PGOOD pin will output high immediately after the
output voltage arrives 90% of normal output voltage.
Thermal Shutdown Protection
Thermal protection limits power dissipation to prevent IC
over temperature in RT9059. When the operation junction
temperature exceeds 160°C, the over temperature
protection circuit starts the thermal shutdown function
and turns the pass transistor off. The pass transistor turns
on again after the junction temperature cools by 70°C.
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RT9059
Thermal Considerations
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance,
θJA, is 33.7°C/W on a standard JEDEC 51-7 four-layer
Maximum Power Dissipation (W)1
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
3.6
Four-Layer PCB
SOP-8 (Exposed Pad)
3.0
2.4
WDFN-10L 3x3
1.8
1.2
0.6
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 4. Derating Curve of Maximum Power Dissipation
thermal test board. For WDFN-10L 3x3 package, the
thermal resistance, θJA, is 33.8°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formula :
PD(MAX) = (125°C − 25°C) / (33.7°C/W) = 2.96W for
SOP-8 (Exposed Pad) package
PD(MAX) = (125°C − 25°C) / (33.8°C/W) = 2.95W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 4 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
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RT9059
Outline Dimension
H
A
M
EXPOSED THERMAL PAD
(Bottom of Package)
Y
J
X
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
4.000
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.000
0.152
0.000
0.006
J
5.791
6.200
0.228
0.244
M
0.406
1.270
0.016
0.050
X
2.000
2.300
0.079
0.091
Y
2.000
2.300
0.079
0.091
X
2.100
2.500
0.083
0.098
Y
3.000
3.500
0.118
0.138
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
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11
RT9059
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS9059-08 April 2014