RT8204L Single Synchronous Buck Controller General Description Features The RT8204L PWM controller provides high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. z A built in LDO controller can drive an external N-MOSFET to provide a second output voltage from PWM output or other power source. The RT8204L can provide adjustable voltage down to 0.75V and maximum output voltage is dependen on the selected MOSFET. The internal 0.75V reference voltage with ±1.5% accuracy provides tight regulation of the output voltage. Other features such as independent enable control, open drain power good indicator, under voltage protection, and soft start make the RT8204L a system friendly power management solution for various applications. Ultra High Efficiency ` Resistor Programmable Current Limit by Low Side RDS(ON) Sense (Lossless Limit) ` 4700ppm/° °C RDS(ON) Current Sensing ` Quick Load Step Response within 100ns ` 1% VFB Accuracy Over Line and Load ` Adjustable 0.75V to 3.3V Output Range ` 4.5V to 26V Battery Input Range ` Resistor Programmable Frequency ` Integrated Bootstrap Switch ` Over/Under Voltage Protection ` Voltage Ramp Soft-Start ` Power Good Indicator LDO Controller ` 1.5% accuracy Over Line and Load ` Independent Enable and Power Good Indicator ` Drive N-MOSFETs within Rail to Rail Controller Voltage ` MLCC and POSCAP Stable RoHS Compliant and Halogen Free ` The constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The RT8204L achieves high efficiency at a reduced cost by eliminating the current sense resistor found in traditional current mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs. The buck conversion allows this device to directly step down high voltage batteries for the highest possible efficiency. The RT8204L is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as 0.75V. The RT8204L is available in a WQFN-16L 3x3 package. PWM Controller z z Applications z z z Notebook Computers CPU Core Supply Chipset/RAM Supply as Low as 0.75V Ordering Information RT8204L Package Type QW : WQFN-16L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` DS8204L-04 April 2011 Suitable for use in SnPb or Pb-free soldering processes. www.richtek.com 1 RT8204L Marking Information Pin Configurations (TOP VIEW) RT8204LGQW TON EN/DEM LEN BOOT J8= : Product Code YMDNN : Data Code J8=YM DNN 16 15 14 13 VOUT VDD FB PGOOD 1 12 2 11 10 17 4 5 6 7 9 8 LPGOOD LFB LDRV LGATE RT8204LZQW J8 : Product Code YMDNN : Data Code J8 YM DNN GND 3 UGATE PHASE OC VDDP WQFN-16L 3x3 Typical Application Circuit VIN 4.5V to 26V RTON 16 VDDP 5V RT8204L TON 9 VDDP C1 R1 R2 2 VDD C2 15 EN/DEM 14 LEN CCM/DEM LDO Enable 5 LPGOOD LDO PGOOD R4 12 R5 UGATE PHASE 11 LGATE 8 OC 10 4 PGOOD PGOOD BOOT 13 C4 VOUT1 C3 Q1 R6* Q2 RILIM L1 C8 R7 C5* C6* FB 3 C7* R8 VOUT 1 R3 VDDP LDRV 17 (Exposed Pad) 7 R9 GND LFB C14 Q3 VOUT2 R10 R11 C10 6 C9 C11* C12 C13 R12 * : Optional www.richtek.com 2 DS8204L-04 April 2011 RT8204L Function Block Diagram TRIG On-time Compute 1-SHOT VOUT TON SS (Internal) + + GM - - - R Comp S + BOOT Q DRV UGATE PHASE Q OV + 115% VREF FB UV DRV Latch S1 Q PGND - SS Ramp LGATE Diode Emulation - 90% VREF VDD VDDP 1-SHOT Latch S1 Q + 70% VREF Min. TOFF TRIG + 20µA Thermal Shutdown + GND OC - PGOOD EN/DEM SS LEN 0.75V VREF SS Ramp + - X1 LDRV LPGOOD LFB - 90% VREF + - 50% VREF + LDO Controller DS8204L-04 April 2011 www.richtek.com 3 RT8204L Functional Pin Description Pin No. Pin Name Pin Function 1 VOUT Output Voltage Sense Pin. Connect this pin to the output of the PWM converter. VOUT is an input of the PWM controller. 2 VDD Analog Supply Voltage Input for Internal Analog Integrated Circuit. Bypass this pin to GND with a 1μF ceramic capacitor. 3 FB 4 PGOOD 5 LPGOOD Power Good Signal Open-Drain Output of the LDO Regulator. This pin will be pulled high when the output voltage is within the target range. 6 LFB Feedback Input of LDO Regulator. This pin will be pulled high when the output voltage is within the target range. 7 LDRV Drive Signal for LDO’s Path MOSFET. 8 LGATE Low Side N-MOSFET Gate-Drive Output for the PWM Controller. This pin swings between GND to VDDP. 9 VDDP Gate Driver Supply for external MOSFETs. Bypass this pin to GND with a 1μF ceramic capacitor. 10 OC 11 PHASE 12 UGATE 13 BOOT 14 LEN 15 EN/DEM 16 TON 17 (Exposed Pad) GND www.richtek.com 4 Feedback Input of PWM Controller. Connect FB to a resistive voltage divider from VOUT to GND to adjust the output voltage from 0.75V to 3.3V. Power Good Signal Open-Drain Output of PWM Controller. This pin will be pulled high when the output voltage is within the target range. PWM Current Limit Setting and Sense. Connect a resistor between OC to PHASE for current limit setting. Inductor Connection. This pin is not only the zero current sense input for the PWM converter, but also the UGATE high side gate driver return. High Side N-MOSFET Floating Gate-Driver Output for PWM Controller. This pin swings between PHASE and BOOT. Boost Capacitor Connection for PWM Controller. Connect an external ceramic capacitor from this pin to PHASE. LDO Enable Input with Internal Pull Low Resistor. LDO is enabled if LEN voltage is greater than the Logic High voltage level and disabled if LEN voltage is less than the Logic Low voltage level. PWM Enable and Operation Mode Selection Input. Connect to VDD for diode emulation mode, connect GND for shutdown mode, and float the pin for CCM mode. On Time/Frequency Adjustment Pin. Connect this pin to VIN through a resistor. TON is an input of the PWM controller. Analog Ground and Power Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. DS8204L-04 April 2011 RT8204L Absolute Maximum Ratings (Note 1) Input Voltage, TON to GND ------------------------------------------------------------------------------------------------ –0.3V to 32V z BOOT to PHASE ------------------------------------------------------------------------------------------------------------ –0.3V to 6V z UGATE to PHASE DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −5V to 7.5V z LGATE to GND DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 6V < 20ns ------------------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V z PHASE to GND DC ------------------------------------------------------------------------------------------------------------------------------- –0.3V to 32V < 20ns ------------------------------------------------------------------------------------------------------------------------- −8V to 38V z VDD, VDDP, VOUT, EN/DEM, LEN, LFB, FB, PGOOD, LPGOOD, LDRV to GND ------------------------- –0.3V to 6V z OC to GND -------------------------------------------------------------------------------------------------------------------- –0.3V to 28V z Power Dissipation, PD @ TA = 25°C WQFN-16L 3x3 -------------------------------------------------------------------------------------------------------------- 1.471W z Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA --------------------------------------------------------------------------------------------------------- 68°C/W WQFN-16L 3x3, θJC -------------------------------------------------------------------------------------------------------- 7.5°C/W z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------- 260°C z Junction Temperature ------------------------------------------------------------------------------------------------------- 150°C z Storage Temperature Range ---------------------------------------------------------------------------------------------- –65°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------------- 200V z Recommended Operating Conditions z z z z (Note 4) Input Voltage, VIN ------------------------------------------------------------------------------------------------------------ 4.5V to 26V Supply Voltage, VDD, VDDP ------------------------------------------------------------------------------------------------ 4.5V to 5.5V Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = VDDP = 5V, VIN = 15V, VEN/DEM = VDD, RTON = 1MΩ, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- -- 1250 μA -- 15 -- μA VDD + VDDP -- 1 10 TON -- 1 5 −10 −1 -- 0.742 0.75 0.758 PWM Controller Quiescent Current IQ VDD + VDDP, VFB = 0.8V, forced above the regulation point TON Operating Current Shutdown Current I SHDN VEN/DEM = 0V FB Reference Voltage VFB VDD = 4.5V to 5.5V μA V To be continued DS8204L-04 April 2011 www.richtek.com 5 RT8204L Parameter Symbol FB Input Bias Current Output Voltage Range Test Conditions Min Typ Max Unit −1 0.1 1 μA 0.75 -- 3.3 V 267 334 401 ns 250 400 550 ns EN/DEM = GND -- 20 -- Ω LGATE = High 18 20 22 μA On the basis of 25°C -- 4700 -- ppm/°C GND to OC −10 -- 10 mV PHASE to GND, V EN/DEM = 5V −10 -- 5 mV GND − PHASE, RILIM = 10kΩ 170 200 230 mV 60 70 80 % 110 115 120 % -- 20 -- μs 3.7 3.9 4.1 V -- 150 -- mV From EN high to internal VREF reaches 0.71V (0Æ95%) -- 1.5 -- ms From EN signal going high -- 4.5 -- ms V FB = 0.75V VOUT V IN = 15V, V OUT = 1.25V, RTON = 1MΩ On-Time Minimum Off-Time VOUT Shutdown Discharge Resistance Current Sensing Current Limit Source Current Current Limiter Temperature Coefficient Current Comparator Offset Voltage TC ICS Zero Crossing Threshold Voltage Fault Protection Current Limit Sense Voltage Output Under Voltage Threshold VUVP Over Voltage Protection Threshold Over Voltage Fault Delay Under Voltage Lockout Threshold Under Voltage Lockout Hysteresis Soft-Start Ramp Time VOVP tSS Under Voltage Blank Time With respect to error comparator threshold FB forced above OV threshold Falling edge, PWM disabled below this level Thermal Shutdown TSD_PWM -- 155 -- °C Thermal Shutdown Hysteresis ΔT SD_PWM -- 10 -- °C Driver On-Resistance UGATE Driver Source RUGATEsr BOOT to PHASE forced to 5V -- 2 -- Ω UGATE Driver Sink RUGATEsk BOOT to PHASE forced to 5V -- 1.5 -- Ω LGATE Driver Source RLGATEsr LGATE, High State -- 1.5 -- Ω LGATE Driver Sink RLGATEsk LGATE, Low State -- 0.7 -- Ω LGATE Rising (VPHASE = 1.5V) -- 30 -- UGATE Rising -- 30 -- VDDP to BOOT, 10mA -- -- 90 Ω -2.9 -- --2 0.8 --- V Dead Time Internal BOOT Charging Switch On Resistance Logic I/O Logic-Low EN/DEM Input Threshold Voltage Logic-High VIL VIH EN/DEM Low EN/DEM High EN/DEM Float ns To be continued www.richtek.com 6 DS8204L-04 April 2011 RT8204L Parameter Symbol Test Conditions EN/DEM = VDD Logic Input Current EN/DEM = 0 PGOOD (upper side threshold decide by OV threshold) Measured at FB, with respect to Trip Threshold (falling) reference, no load. Hysteresis = 3% Falling edge, FB forced below Fault Propagation Delay PGOOD trip threshold Output Low Voltage ISINK = 1mA Leakage Current Min Typ Max Unit -- 1 10 −10 1 -- 87 90 93 % -- 2.5 -- μs μA -- -- 0.4 V High state, forced to 5V -- -- 1 μA PWM Off, LDO On, ILOAD = 0A -- -- 400 μA LDO Controller Quiescent Current IQ_LDO LEN Threshold Logic-High Voltage Logic-Low V IH_LDO 1.2 -- -- V IL_LDO -- -- 0.8 LEN Input Current IIN_LEN -- -- 10 μA LFB Reference Voltage V REF_LFB 0.739 0.75 0.761 V LFB Input Current IIN_LFB −1 -- 1 μA LDRV Output Current IOUT_LDRV Sourcing, LFB = 0.72 1.4 2 -- Sinking, LFB = 0.78 1.4 2 -- VLFB = 0.75V -- 2 -- ms Measured at LFB pin 40 50 60 % -- 4 -- ms 87 90 93 % -- 2.5 -- μs -- -- 0.4 V VLEN = 5V, (internal pull low) V mA Soft-Start Time Output Under Voltage Protection Threshold LDO Under Voltage Blanking Time Power Good Threshold (falling) LDO Power Good Propagation Delay LPGOOD Low Voltage Falling edge, LFB forced below LPGOOD trip threshold ISINK = 1mA Leakage Current High state, forced to 5V -- -- 1 μA Hysteresis = 10°C -- 155 -- °C -- 10 -- °C Thermal shutdown Thermal shutdown Hysteresis Measured at LFB pin T SD_LDO ΔTSD_LDO Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high-effective thermal conductivity four- layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS8204L-04 April 2011 www.richtek.com 7 RT8204L Typical Operating Characteristics Switching Frequency vs. Output Current VOUT1 Efficiency vs. Output Current 100 DEM 80 Efficiency (%) Switching Frequency (kHz)1 90 70 60 50 40 PWM 30 20 10 VIN = 8V, VOUT1 = 1.05V 0 0.001 0.01 0.1 1 10 100 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0.001 PWM DEM VIN = 8V, VOUT1 = 1.05V 0.01 Output Current (A) Efficiency (%) Switching Frequency (kHz)1 90 DEM 70 60 50 PWM 40 30 20 10 VIN = 12V, VOUT1 = 1.05V 0 0.001 0.01 0.1 1 10 100 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0.001 VOUT1 Efficiency vs. Output Current DEM VIN = 12V, VOUT1 = 1.05V 0.01 Switching Frequency (kHz)1 DEM Efficiency (%) 70 60 50 PWM 30 20 0 0.001 VIN = 20V, VOUT1 = 1.05V 0.01 0.1 1 Output Current (A) www.richtek.com 8 0.1 1 10 100 Switching Frequency vs. Output Current 90 10 100 Output Current (A) 100 40 10 PWM Output Current (A) 80 1 Switching Frequency vs. Output Current VOUT1 Efficiency vs. Output Current 100 80 0.1 Output Current (A) 10 100 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 0.001 PWM DEM VIN = 20V, VOUT1 = 1.05V 0.01 0.1 1 10 100 Output Current (A) DS8204L-04 April 2011 RT8204L LDO Output Voltage vs. Output Current Standby Current vs. Input Voltage 520 1.0640 Standby Current (µA) 1 Output Voltage (V) 1.0632 1.0624 1.0616 1.0608 500 480 460 440 420 VIN_LDO = 1.5V VEN/DEM = 5V, No Load 400 1.0600 0 1 2 3 4 7 5 10 13 16 19 22 Output Current (A) Input Voltage (V) Shutdown Current vs. Input Voltage Power On from EN_PWM Mode 25 Shutdown Current (µA) 1 10 VOUT1 (1V/Div) 8 6 VPHASE (10V/Div) 4 2 EN/DEM = GND, No Load VEN/DEM (2V/Div) VPGOOD (5V/Div) VIN = 12V, EN/DEM = Floating, No Load 0 7 10 13 16 19 22 Time (1ms/Div) 25 Input Voltage (V) Power On from EN_DEM Mode Power Off from EN VOUT1 (1V/Div) VOUT1 (1V/Div) VPHASE (10V/Div) VEN/DEM (2V/Div) VUGATE (20V/Div) VEN/DEM (5V/Div) VPGOOD (5V/Div) VIN = 12V, VEN_DEM = 5V, No Load Time (1ms/Div) DS8204L-04 April 2011 VLGATE (5V/Div) VIN = 12V, EN/DEM = Floating, No Load Time (10ms/Div) www.richtek.com 9 RT8204L VOUT1 Load Transient Response VOUT1 (50mV/Div) VOUT1 (1V/Div) IL (20A/Div) VPGOOD (5V/Div) VUGATE (20V/Div) VLGATE (5V/Div) Over Voltage Protection VLGATE (5V/Div) VIN = 12V, VEN/DEM = 5V, No Load VIN = 12V, EN/DEM = Floating, IOUT1 = 0A to 20A Time (40μs/Div) Time (40μs/Div) Under Voltage Protection LDO Load Transient Response VIN_LDO = 1.5V, COUT = 10μF x2, IOUT2 = 0A to 5A VOUT1 (1V/Div) VOUT2 (100mV/Div) VPGOOD (5V/Div) VUGATE (20V/Div) VLDRV (2V/Div) VLGATE (5V/Div) I LOAD (5A/Div) VIN = 12V, EN/DEM = Floating, No Load Time (40μs/Div) Time (100μs/Div) LDO Power On from LEN LDO Short-Circuit Protection No Load on OUT_PWM and OUT_LDO VOUT2 (1V/Div) VOUT2 (1V/Div) VLDRV (2V/Div) VLEN (5V/Div) VLPGOOD (5V/Div) VLDRV (2V/Div) VIN = 12V, VIN_LDO = 1.5V CIN = 10μF, COUT = 10μF x 2 Time (2ms/Div) www.richtek.com 10 VLPGOOD (5V/Div) VIN_LDO = 1.5V, COUT = 10μF x 2, VOUT2 Short Time (100μs/Div) DS8204L-04 April 2011 RT8204L Applications Information The RT8204L PWM controller provides the high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. RichTek's Mach ResponseTM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load transient timing problems of fixed frequency current mode PWMs while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant- off-time PWM schemes. The DRVTM mode PWM modulator is specifically designed to have better noise immunity for such a single output application. PWM Operation The Mach ResponseTM, DRVTM mode controller relies on the output filter capacitor's effective series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. Referring to the function diagrams of the RT8204L, the synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one shot timer expires, the MOSFET is turned off. The pulse width of this one shot is determined by the converter’s input and output voltages to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (400ns typ.). On-Time Control (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator. DS8204L-04 April 2011 tON = 3.85p x RTON x VOUT (VIN − 0.5) And then the switching frequency is : Frequency = VOUT (VIN x t ON ) RTON is a resistor connected from the input supply (VIN) to the TON pin. Mode Selection (EN/DEM) Operation The EN/DEM pin enables the supply. When EN/DEM is tied to VDD, the controller is enabled and operates in diode-emulation mode. When the EN/DEM pin is floating, the RT8204L will operate in forced-CCM mode. Diode-Emulation Mode (EN/DEM = High) In diode-emulation mode, the RT8204L automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increasing VOUT ripple or load regulation. As the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point when its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low side MOSFET allows only partial negative current when the inductor freewheeling current becomes negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The transition load point to the light load operation can be calculated as follows (Figure 1) : (VIN − VOUT ) x tON 2L where tON is the On-time. ILOAD ≈ www.richtek.com 11 RT8204L IL IL Slope = (VIN -VOUT) / L IL, PEAK IL, PEAK ILOAD ILOAD = IL, PEAK / 2 0 tON t ILIM t 0 Figure 1. Boundary Condition of CCM/DEM Figure 2. Valley Current Limit The switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, however, this is a normal operating condition that results in high light load efficiency. Trade-offs in DEM noise vs. light load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. The disadvantages for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). Current sensing of the RT8204L can be accomplished in two ways. Users can either use a current-sense resistor or the on-state of the low side MOSFET (RDS(ON)). For resistor sensing, a sense resistor is placed between the source of low side MOSFET and PGND (Figure 3(a)). RDS(ON) sensing is more efficient and less expensive (Figure 3(b)). However, there is a compromise between current limit accuracy and sense resistor power dissipation. Forced-CCM Mode (EN/DEM = floating) The low noise, forced-CCM mode (EN/DEM = floating) disables the zero crossing comparator, which controls the low side switch on-time. This causes the low side gate-drive waveform to become the complement of the high-side gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop to maintain a duty ratio VOUT/VIN. The benefit of forcedCCM mode is to keep the switching frequency fairly constant, but it comes at a cost. The no-load battery current can be as high as 10mA to 40mA, depending on the external MOSFETs. Current Limit Setting (OCP) The RT8204L has a cycle-by-cycle current limiting control. The current limit circuit employs a unique“valley” current sensing algorithm. If the magnitude of the current-sense signal at OC is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 2). www.richtek.com 12 PHASE LGATE OC RILIM (a) PHASE LGATE OC RILIM (b) Figure 3. Current Sense Methods In both cases, the RILIM resistor between the OC pin and PHASE pin sets the over current threshold. This resistor RILIM is connected to a 20μA current source within the RT8204L which is turned on when the low side MOSFET turns on. When the voltage drop across the sense resistor or low side MOSFET equals the voltage across the RILIM resistor, positive current limit will activate. The high side DS8204L-04 April 2011 RT8204L MOSFET will not be turned on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. Choose a current limit resistor by the following equation : I x RSENSE RILIM = LIMIT 20μA Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current sense signal seen by OC and PGND. Mount the IC close to the low-side MOSFET and sense resistor with short, direct traces, making a Kelvin sense connection to the sense resistor. MOSFET Gate Driver (UGATE, LGATE) The high side driver is designed to drive high current, low RDS(ON) N-MOSFET(s). When configured as a floating driver, 5V bias voltage is delivered from VDDP supply. The average drive current is proportional to the gate charge at VGS = 5V times the switching frequency. The instantaneous drive current is supplied by the flying capacitor between BOOT and PHASE pins. A dead time to prevent shoot through is internally generated between high side MOSFET off to low side MOSFET on, and low side MOSFET off to high side MOSFET on. The low side driver is designed to drive high current, low RDS(ON) N-MOSFET(s). The internal pull down transistor that drives LGATE low is robust, with a 0.6Ω typical on resistance. A 5V bias voltage is delivered form VDDP supply. The instantaneous drive current is supplied by the flying capacitor between VDDP and PGND. For high current applications, some combinations of high and low side MOSFETs might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI producing shoot through currents. This is often remedied by adding a resistor in series with BOOT, which increases the turn-on time of the high side MOSFET without degrading the turn-off time (Figure 4). +5V BOOT VIN R UGATE PHASE Figure 4. Reducing the UGATE Rise Time Power Good Output (PGOOD) The power good output is an open-drain output and requires a pull up resistor. When the output voltage is 15% above or 10% below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within these tolerances once more. In soft start, PGOOD is actively held low and is allowed to transition high until soft start is over and the output reaches 93% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false transition. POR, UVLO and Soft-Start Power on reset (POR) occurs when VDD rises above to approximately 4.1V. The RT8204L will reset the fault latch and prepare the PWM for operation. At below 3.7V (min), the VDD under voltage lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low. A built in soft-start is used to prevent surge current from power supply input after EN/DEM is enabled. It clamps the ramping of internal reference voltage which is compared with the FB signal. The typical soft-start duration is 1.5ms. Output Over Voltage Protection (OVP) The output voltage can be continuously monitored for over voltage protection. When the output voltage exceeds 15% of its set voltage threshold, over voltage protection is triggered and the low side MOSFET is latched on. This activates the low side MOSFET to discharge the output capacitor. The RT8204L is latched once OVP is triggered and can only be released by VDD or EN/DEM power-on reset. There is a 20μs delay built into the over voltage protection circuit to prevent false transitions. DS8204L-04 April 2011 www.richtek.com 13 RT8204L Output Under Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. When the output voltage is less than 70% of its set voltage threshold, under voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. In order to remove the residual charge on the output capacitor during the under voltage period, if PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. There is 2.5μs delay built into the under voltage protection circuit to prevent false transitions. During soft-start, the UVP will be blanked around 4.5ms. Output Voltage Setting (FB) The output voltage can be adjusted from 0.75V to 3.3V by setting the feedback resistors R7 and R8 (Figure 5). Choose R8 to be approximately 10kΩ, and solve for R7 using the equation : R7 ⎞ ⎛ VOUT = VFB x ⎜ 1 + ⎟ R8 ⎠ ⎝ where VFB is 0.75V. VIN VOUT UGATE PHASE LGATE VOUT R7 Find a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK) : ⎛ LIR ⎞ IPEAK = ILOAD(MAX) + ⎜ x ILOAD(MAX) ⎟ ⎝ 2 ⎠ Output Capacitor Selection The output filter capacitor must have ESR low enough to meet output ripple and load transient requirement, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transient, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance : VP − P ESR ≤ ILOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain at an acceptable level of output voltage ripple : VP − P ESR ≤ LIR x ILOAD(MAX) Organic semiconductor capacitor(s) or special polymer capacitor(s) are recommended. FB R8 GND Figure 5. Setting The Output Voltage Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows : t x (VIN − VOUT ) L = ON LIR x ILOAD(MAX) www.richtek.com 14 Output Capacitor Stability Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation : f 1 f= < SW 2 x π x ESR x COUT 4 Do not put high value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic and unstable operation. However, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting VOUT or the FB divider close to the inductor. DS8204L-04 April 2011 RT8204L There are two related but distinct ways, double pulsing and feedback loop instability to identify the unstable operation. Double pulsing occurs due to noise on the output or because the ESR is too low such that there is not enough voltage ramp in the output voltage signal. This“fools” the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it may indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillation at the output after line or load perturbations and trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with an AC probe. Do not allow more than one ringing cycle after the initial step response under shoot or over shoot. LDO Normal Operation The RT8204L LDO controls an N-MOSFET to produce a tightly regulated output voltage from higher supply voltage. It takes 5V power supply for controller and draws maximally 400μA while operating. The feedback voltage is regulated to compare with the internal 0.75V reference voltage. To set the output voltage, feedback the conjunction of a resistive voltage divider from output node to ground for the LFB pin. Depending upon the input voltage used for the device, the LDRV pin can pull up near to VDD. Thus, the device can be used to regulate a large range of output voltage by careful selection of the external MOSFETs. The RT8204L LDO includes an active high enable control (LEN pin) used to turn on RT8204L LDO. If this pin is pulled low, the LDRV pin is pulled low, turning off the N-MOSFET. If this pin is pulled higher than 1.2V, the LDRV pin is enabled. DS8204L-04 April 2011 The RT8204L LDO contains a power good output pin (LPGOOD pin), which is an open drain output that pulled low if the output is below the power good threshold (typically 90% of the programmed output voltage, or 93% at start up). The power good detection is active if the RT8204L LDO is enabled. Also included is an under voltage protection circuit that monitors the output voltage. If the output voltage drops below 50% (typical) of nominal, as would occur during over current or short condition, the RT8204L LDO will pull the LDRV pin low and latch off. The RT8204L LDO is latched once UVP is triggered and can only be relieved by VDD or LEN power on reset. LDO Driver and Stability Design The drive output (LDRV pin) is sink/source capable. The sink current is typically 2mA, while the source current is typically 2mA in normal operation. The drive output is also used for stabilizing the loop of the system using different types of output capacitors. The components listed in the table below are used. Table 1. LDO Configuration and Compensation LDO Configuration Input Output Voltage Voltage 1.25V 1.05V 1.5V 1.05V 1.5V 1.25V 1.8V 1.5V Compensator C9 C10 R9 33nF 33nF 33nF 33nF 39pF 47pF 47pF 39pF 82Ω 43Ω 30Ω 100Ω Note : test condition is output capacitor 220μF (ESR : 9 to 25mΩ) or 100μF (ESR : 9 to 15mΩ) +MLCC 10μF output current is from 0.1A to 5A LDO Output Voltage Protection(UVP) The RT8204L LDO has output under voltage protection that monitors at the output to check if RT8204L : (a) LDO output voltage is less than 50% (typical) of its nominal value and (b) VLDRV is within 900mV (typical) of its maximum. This provides inherent immunity to under voltage shut down at start up since VLDRV has a slow rate of rising at this moment. If both of these criteria are met, the output is shut down by means of pulling V LDRV to ground immediately. www.richtek.com 15 RT8204L If the VDDP input is supplied prior to the LDO_VIN, it could accidentally meet the UVP fault protection. To avoid entering UVP latch off, use the enable control (LEN pin) to turn the system on after all power supplies are ready. Refer to the power sequencing example below (Figure 6). VDDP VTH(UV) = 0.88V LDO_VIN VTH(LEN) = 1.2V LEN VTH(LEN) occurs after VTH(UV) is reached RT8204L Supply Comes Up Before MOSFET Drain Supply VDDP VTH(UV) = 0.88V LDO_VIN VTH(LEN) = 1.2V LEN VTH(LEN) occurs after VTH(UV) is reached LEN rising with VDDP shown MOSFET Drain Supply Comes Up Before RT8204L Supply Figure 6. Power Supply Sequencing LDO Output Voltage Setting LDO Input Capacitor Selection The LFB pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistors R11 and R12 (Figure 7). The following equation is for adjusting the output voltage : Low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for the input capacitors to provide better load transient response. If the LDO input is connected from the output of buck converter (VOUT1), a 0.1μF ceramic capacitor will be sufficient. R11 ⎞ ⎛ VOUT = VLFB x ⎜ 1 + ⎟ R12 ⎠ ⎝ where VLFB is 0.75V (typ.). LDO_VIN (VOUT1) LDRV LDO Output Capacitor Selection Low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for bulk capacitance, and ceramic bypass capacitors are recommended for decoupling high frequency transients. LDO_VOUT (VOUT2) R11 LFB R12 Figure 7. LDO Output Voltage Setting www.richtek.com 16 DS8204L-04 April 2011 Maximum Power Dissipation (W)1 RT8204L LDO MOSFET Selection Low threshold N-MOSFETs are required. For the device to work under all operating conditions, a maximum RDS(ON) must be met to ensure that the output will not go into dropout : VIN(MIN) − VOUT(MAX) RDS(ON)(MAX) = (Ω ) IOUT(PEAK) Note that RDS(ON) must be met for operating temperature range at the minimum VGS condition. Power consumptions of the N-MOSFETs should be taken into consideration for the selection of various package types. 1.60 Four-Layer PCB 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 0 25 50 75 100 125 Ambient Temperature (°C) Figure 8. Derating Curve for the RT8204L Package Thermal Considerations Layout Consideration For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to converter instability. Certain points must be considered before starting a layout for the RT8204L. ` Connect RC low-pass filter from VDDP to VDD, 1μF and 20Ω are recommended. Place the filter capacitor close to the IC. PD(MAX) = (TJ(MAX) − TA) /θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT8204L, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN16L 3x3 packages, the thermal resistance, θJA, is 68°C/ W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : ` Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high-voltage switching node. ` Connections from the drivers to the respective gate of the high side or low side MOSFET should be as short as possible to reduce stray inductance. ` All sensitive analog traces and components such as VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and TON should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. PD(MAX) = (125°C − 25°C ) / (68°C/W) = 1.471W for WQFN16L 3x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT8204L package, the derating curve in Figure 8 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. DS8204L-04 April 2011 ` Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` Power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. www.richtek.com 17 RT8204L Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 18 DS8204L-04 April 2011