RT8159A 12V Synchronous Buck PWM DC/DC and Linear Regulator Controller General Description Features The RT8159A is a DC/DC regulator controller specifically designed for dual outputs application in which 12V power source is available. This part consists of a synchronous rectified buck PWM controller and a low dropout linear regulator (LDO) controller. The buck PWM controller utilizes voltage mode control with external compensation. The MOSFET gate drivers and bootstrap diode are all integrated in the controller to minimize external component count. The MOSFET gate drivers provide 12V driving voltage for high side and low side MOSFETs to achieve high efficiency power conversion. The LDO controller drives an external N-MOSFET for low power application. Other features include adjustable oscillator frequency, internal soft start, fast transient response, under voltage protection, enable/disable control, and adjustable over current protection for PWM output. With the above functions, RT8159A provides customers a compact, high efficiency, and cost-effective solution. z z z z z z z z z z z z Applications Ordering Information z RT8159A z Package Type S : SOP-14 Lead Plating System G : Green (Halogen Free and Pb Free) Note : Single 12V Bias Supply Support Dual Channel Power Conversion ` Synchronous Rectified Buck PWM Controller ` Linear Regulator Controller Both Controllers Drive Low Cost N-MOSFETs Adjustable Oscillator Frequency up to 1MHz with 230kHz Free Running Frequency Enable/ Disable Control Integrated MOSFET Drivers and Bootstrap Diode Internal Reference Voltage Accuracy ` PWM Controller : ±1% ` LDO Controller : ±2% External Compensation for PWM Controller Under Voltage Protection for Both Outputs Low Side MOSFET RDS(ON) Current Sense Adjustable Over Current Protection RoHS Compliant and Halogen Free z z z z Graphic Card GPU, Memory Core Power Graphic Card Interface Power Motherboard, Desktop and Servers Chipset and Memory Core Power IA Equipments Telecomm Equipments High Power DC/DC Regulators Richtek products are : ` RoHS compliant and compatible with the current require- Pin Configurations ments of IPC/JEDEC J-STD-020. ` (TOP VIEW) Suitable for use in SnPb or Pb-free soldering processes. Marking Information RT8159A GSYMDNN RT8159AGS : Product Number YMDNN : Date Code BOOT RT_DIS COMP FB DRV FBL GND 14 2 13 3 12 4 11 5 10 6 9 7 8 UGATE PHASE PGND LGATE OCSET NC VCC12 SOP-14 DS8159A-02 April 2011 www.richtek.com 1 RT8159A Typical Application Circuit RBOOT R6 12V CVCC CBOOT RT8159A VIN2 3.3V to 12V CIN2 Q3 ILOAD2 R4 VOUT2 COUT2 1 BOOT 8 VCC12 5 DRV 6 PHASE LGATE FBL R5 RRT UGATE PGND 2 RT_DIS 7 GND VIN1 3.3V/5V/12V 14 CIN1 RG Q1 LOUT ILOAD1 13 VOUT1 11 RSNB Q2 CSNB 12 FB 4 3 COMP C3 R3 COUT1 R1 C2 10 OCSET EN C1 Q4 Optional R2 RF ROCSET Functional Pin Description Pin No. Pin Name Pin Function Bootstrap Supply for the High Side MOSFET Gate Driver. Connect a bootstrap capacitor from BOOT pin to PHASE pin. The bootstrap capacitor provides the charge to turn on the high side MOSFET. This pin provides two functions : oscillator frequency setting and enable/disable control. Connect a resistor from this pin to GND to set the internal oscillator frequency for PWM switching regulator. The voltage at this pin is monitored for enable/disable control. If this pin is externally pulled down below 0.4V, both switching regulator output and LDO output will be disabled until it is released. Error Amplifier Output Pin. Connect an R-C network between COMP pin and FB pin to compensate the control loop of the buck converter. This pin is the inverting input of the error amplifier of PWM controller. Connect this pin to the buck converter output via resistor divider for output voltage sensing. The voltage at FB pin is also monitored for under voltage protection. If FB voltage falls below 0.4V (50% of VREF), under voltage protection will be tripped to shutdown the controller. Linear Regulator Controller Driver Output Pin. Connect this pin to the gate of an external N-MOSFET. This pin is the inverting input of the error amplifier of LDO controller. Connect this pin to the LDO output via resistor divider for output voltage sensing. The voltage at FBL pin is also monitored for under voltage protection. If FBL voltage falls below 0.4V (50% of VREF), under voltage protection will be tripped to shutdown the controller. Ground of the PWM and LDO Controller. Output voltage is regulated with respect to this pin. Controller Power Supply Pin. Connect this pin to a well decoupled 12V bias supply. This pin is also the power supply for the low side MOSFET gate driver. 1 BOOT 2 RT_DIS 3 COMP 4 FB 5 DRV 6 FBL 7 GND 8 VCC12 9 NC No Internal Connection. OCSET Connect a resistor (ROCSET) from this pin the source of the upper MOSFET and the drain of the lower MOSFET to set the over current trip point, ROCSET. The internal 40μA current source, and the lower MOSFET on resistance, RDS(ON) sets the converter over current trip point (IOCSET ). 10 To be continued www.richtek.com 2 DS8159A-02 April 2011 RT8159A Pin No. Pin Name Pin Function 11 LGATE Low Side MOSFET Gate Driver Output. Connect this pin to the gate of low-side N-MOSFET. The voltage at this pin is monitored by the shoot through protection circuitry to prevent cross conduction. 12 PGND Power Ground of the Low Side MOSFET Gate Driver. 13 PHASE 14 UGATE Connect this pin to the switching node of the buck converter. This pin is also the return of the high side MOSFET gate driver. The voltage at this pin is monitored by the shoot-through protection circuitry to prevent cross-conduction. High Side MOSFET Gate Driver Output. Connect this pin to the gate of high side N-MOSFET. Function Block Diagram 5VDD Regulator VCC12 Voltage Reference 5VDD Power On Reset 0.4V VREF2 40µA POR - FBL OC + VCC12 - + + + DRV Inhibit + 0.4V OCSET - Soft-Start & Fault Logic PH_M + SSE 1.5V BOOT UGATE Shutdown Inhibit SSE + + EA - VREF1 RT_DIS + - PWM LGATE Oscillator PGND GND FB DS8159A-02 April 2011 PHASE Driver Logic COMP www.richtek.com 3 RT8159A Absolute Maximum Ratings (Note 1) Supply Voltage, VCC12 ------------------------------------------------------------------------------- 15V PHASE to GND DC -------------------------------------------------------------------------------------------------------- −5V to 15V < 20ns -------------------------------------------------------------------------------------------------- −10V to 30V z BOOT to PHASE ------------------------------------------------------------------------------------- 15V z UGATE -------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) z LGATE -------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC12 + 0.3V) z DRV ----------------------------------------------------------------------------------------------------- GND − 0.3V to VCC12 + 0.3V z Input, Output or I/O Voltage ------------------------------------------------------------------------ GND − 0.3V to 7V z Power Dissipation, PD @ TA = 25°C SOP-14 ------------------------------------------------------------------------------------------------- 1.000W z Package Thermal Resistance (Note 2) SOP-14, θJA -------------------------------------------------------------------------------------------- 100°C/W z Junction Temperature -------------------------------------------------------------------------------- 150°C z Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C z Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------- 2kV MM (Machine Mode) --------------------------------------------------------------------------------- 200V z z Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC12 ------------------------------------------------------------------------------- 12V ± 10% Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC12 = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 8.8 9.6 10.4 V 0.4 0.78 1.2 V -- 3 -- mA -250 230 300 -350 kHz kHz -- 1.6 -- V V REF1 0.792 0.8 0.808 V V REF2 0.784 0.8 0.816 V 70 88 -- dB 6 15 Supply Input Power On Reset V VCC12_rth Power On Reset Hysteresis V VCC12_hys Power Supply Current IVCC12 UGATE, LGATE Open Oscillator Free Running Frequency Switching Frequency fOSC, fr fOSC R RT = NC R RT = 110kΩ Ramp Amplitude Reference Voltage PWM Error Amplifier Reference Linear Driver Reference Error Amplifier DC Gain (Note 5) Gain-Bandwidth Product www.richtek.com 4 ΔV OSC VCC12 Rising GBW -MHz To be continued DS8159A-02 April 2011 RT8159A Parameter Slew Rate Symbol Test Conditions Min Typ Max Unit SR CLOAD = 5pF 3 6 -- V/μs Upper Drive Source RUGATEsr VBOOT − VPHASE = 12V, VBOOT − VUGATE = 1V -- 4 8 Ω Upper Drive Sink RUGATEsr VUGATE = 1V -- 4 8 Ω Lower Drive Source RLGATEsr VCC12 – VLGATE = 1V -- 4 6 Ω Lower Drive Sink RLGATEsr VLGATE = 1V -- 2 4 Ω Under Voltage Protection V UVP Measure FB Voltage 0.36 0.4 0.45 V Soft-Start Time Interval tSS 10% to 90% FB Voltage 2 3 4 ms Over Current Threshold V OC ROCSET = 20kΩ -- −400 -- mV RT_DIS Shutdown Threshold V SHDN_RT 0.35 0.4 -- V Output High Voltage V DRVH 9.5 10.3 -- V Output Low Voltage V DRVL -- 0.1 1 V Source Current IDRVSR 2 -- -- mA Sink Current IDRVSC 0.5 -- -- mA Gate Driver Protection Linear Regulator Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. DS8159A-02 April 2011 www.richtek.com 5 RT8159A Typical Operating Characteristics Power On Power Off ILOAD1 = 1A, ILOAD2 = 0.1A ILOAD1 = ILOAD2 = 0.1A VCC12 (10V/Div) VCC12 (10V/Div) VOUT1 (1V/Div) VOUT2 (2V/Div) VOUT1 (1V/Div) VOUT2 (2V/Div) UGATE (20V/Div) UGATE (20V/Div) Time (2ms/Div) Time (4ms/Div) Enable from RT_DIS Disable from RT_DIS ILOAD1 = ILOAD2 = 0.1A ILOAD1 = 0.2A, ILOAD2 = 0.3A RT_DIS (2V/Div) RT_DIS (2V/Div) VOUT1 (1V/Div) VOUT2 (2V/Div) VOUT1 (1V/Div) UGATE (20V/Div) UGATE (20V/Div) VOUT2 (2V/Div) Time (1ms/Div) Time (4ms/Div) LDO UVP VOUT1 OCP VOUT2 (100mV/Div) inductor current (20A/Div) VOUT1 (1V/Div) VOUT1 (2V/Div) UGATE (20V/Div) UGATE (50V/Div) LGATE (10V/Div) LGATE (20V/Div) VIN2 = 0V, ILOAD1 = 0.1A, power up Time (10ms/Div) www.richtek.com 6 Time (2ms/Div) DS8159A-02 April 2011 RT8159A LDO Behavior while VOUT1 OCP VOUT1 Short Circuit Protection DRV (5V/Div) inductor current (20A/Div) VOUT2 (2V/Div) UGATE (20V/Div) inductor current (20A/Div) LGATE (20V/Div) VOUT1 (200mV/Div) VOUT1 (2V/Div) short output then power up Time (2ms/Div) Time (2ms/Div) LDO Behavior while VOUT1 Short Circuit UGATE Rising Edge Dead Time UGATE inductor current (20A/Div) LGATE UGATE (20V/Div) PHASE UGATE−PHASE DRV (2V/Div) VOUT2 (100mV/Div) (5V/Div) ILOAD = 0A, RG = 0Ω HSFET = LSFET = IPD09N03L x 1 short output then power up Time (2ms/Div) Time (20ns/Div) UGATE Falling Edge Dead Time PWM Regulator Transient Response VIN1 = 12V, VOUT1 = 1.1V L = 1μH, COUT1 = 820μF, ILOAD 1A to 20A UGATE I LOAD (50A/Div) PHASE LGATE VOUT1 (50mV/Div) UGATE−PHASE (5V/Div) ILOAD = 0A, RG = 0Ω HSFET = LSFET = IPD09N03L x 1 Time (20ns/Div) DS8159A-02 April 2011 UGATE (20V/Div) LGATE (20V/Div) Time (10μs/Div) www.richtek.com 7 RT8159A LDO Regulator Transient Response PWM Regulator Transient Response VIN1 = 12V, VOUT1 = 1.1V, L = 1μH, COUT1 = 820μF, ILOAD = 1A to 20A I LOAD (50A/Div) I LOAD (0.5A/Div) VOUT1 (50mV/Div) VOUT2 (5mV/Div) UGATE (20V/Div) LGATE (20V/Div) VIN2 = 3.3V, VOUT2 = 1.8V COUT2 = 100μF, ILOAD = 0.1A to 1A Time (100μs/Div) Time (10μs/Div) VREF1 vs. Temperature 0.808 VCC12 = 12V, No Load 0.806 VREF1 (V) 0.804 0.802 0.800 0.798 0.796 0.794 0.792 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 8 DS8159A-02 April 2011 RT8159A Application Information The RT8159A is a DC/DC regulator controller specifically designed for dual outputs application in which 12V power source is available. This part consists of a synchronous rectified buck PWM controller and a low dropout linear regulator (LDO) controller. The buck PWM controller utilizes voltage mode control with external compensation. The MOSFET gate drivers and bootstrap diode are all integrated in the controller to minimize external component count. The MOSFET gate drivers provide 12V driving voltage for high side and low side MOSFETs to achieve high efficiency power conversion. The LDO controller drives an external N-MOSFET for low power application. Other features include adjustable switching frequency, internal soft start, fast transient response, under voltage protection, enable/disable control, and low side MOSFET RDS(ON) current sense. If the RT_DIS pin is left open without any resistor connected, the switching regulator will operate at the free-running frequency, which is typically 230kHz. Figure 1 shows the curve of the operating frequency vs. RRT value for quick reference. FSW vs. RRT FSW (kHz) Introduction 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 1 Frequency Setting and Enable/ Disable Control The oscillator frequency of the switching regulator is determined by the resistor RRT connected from RT_DIS pin to GND pin. The oscillator frequency can be approximately expressed as the function of RRT as follows: fSW ≅ 230 + 6750 (kHz), RRT is in kΩ RRT DS8159A-02 April 2011 100 1000 (kΩ) RRRT RT(kohm) VCC12, MOSFET Gate Driver and Bootstrap Diode Connect a well-decoupled 12V power source to VCC12 pin to power the RT8159A. VCC12 also powers the low side MOSFET gate driver and the bootstrap circuit for the high side MOSFET gate driver. An internal linear regulator regulates this 12V input to a 5VDD voltage as the power supply of the internal control logic circuit. No external decoupling capacitor is required for filtering this 5VDD voltage. The RT8159A integrates the MOSFET gate driver and bootstrap diode into the PWM controller. No external bootstrap diode is required. This integration minimizes the external component count for driving MOSFETs. The driving voltage for both the high side and low side MOSFET is 12V to provide high efficiency at heavy load in low output voltage application. 10 Figure 1. RRT vs. fSW The voltage at RT_DIS pin is monitored for enable/disable function, which provides the flexibility in power sequence control. If RT_DIS pin is externally pulled down below 0.4V, the RT8159A will be disabled with UGATE, LGATE and DRV going low. When RT_DIS pin is released, the RT8159A initiates the VIN1 detection followed by the soft start operation.Connect a small-signal MOSFET from RT_DIS pin to GND to implement the enable/disable control. Power On Reset The input voltage of the RT8159A at VCC12 pin is continuously monitored by the Power On Reset (POR) function. The RT8159A begins to operate if VCC12 rises higher than the POR threshold voltage. If VCC12 falls below the POR threshold, the RT8159A shuts down. There is a hysteresis for the POR threshold to avoid unintentional shutdown. PWM Switching Regulator Input Detection The RT8159A has input voltage detection function for the PWM switching regulator. After the RT8159A is enabled and VCC12 exceeds the POR threshold, a train of 10kHz www.richtek.com 9 RT8159A pulse with 1μs width is generated at UGATE to detect the existence of input voltage gor the buck regulator. As shown in Figure 2, the voltage at PHASE pin is monitored during the detection. If the PHASE voltage crosses 1.5V (rising and falling) for four times, the existence of V IN1 is recognized as ready. Once VIN1 is ready, the RT8159A then initializes the soft start operation as described in the next section. Otherwise, the 10kHz pulse at UGATE will continue to be generated. VIN1 POR_H PHASE_M VIN1 (1V/Div) VOUT1 (1V/Div) DRV (5V/Div) UGATE (20V/Div) PHASE + - ILOAD1 = ILOAD2 = 0.1A, power off VIN1 UGATE 1.5V 1st 2nd 3rd 4th PHASE waveform Internal Counter will count (VPHASE > 1.5V) four times (rising & falling) to recognize that VIN1 is ready. Figure 2. Switching Regulator's Input Voltage Detection Soft Start A built-in soft-start function is used to prevent surge current from power supply input during start up (referring to the Functional Block Diagram). The error amplifier EA is a three-input device. SSE (internal soft start voltage) or VREF1 (whichever is smaller) dominates the non-inverting input. The SSE linearly ramps up to about 4V after VIN1 existence is recognized with about 2ms delay. Accordingly, the output voltage ramps up smoothly to its target level. The rise time of output voltage is about 3ms. VREF1 takes over the non-inverting input of EA when SSE > VREF1. SSE is also used for LDO soft start. LDO input voltage VIN2 must be ready before SSE starts to ramp up. Otherwise, the UVP function of LDO will be triggered to shut down the RT8159A. Under Voltage Protection The voltages at FB and FBL pin are monitored for Under V oltage Protection (UVP) after the soft start is completed. UVP is triggered if one of the feedback voltages is under (50% x VREFx) with a 30μs delay. As shown in Figure 3, the RT8159A PWM controller shuts down followed by Vin detection pulses when VIN1 is powered off. In Figure 4, the RT8159A shuts down after 4 times of UVP hiccups triggered by FBL. Time (2ms/Div) Figure 3. Power off VIN1 to Trip UVP ILOAD1 = ILOAD2 = 0.1A, power off VIN2 VIN2 (5V/Div) VOUT2 (1V/Div) DRV (10V/Div) UGATE (50V/Div) Time (20ms/Div) Figure 4. LDO UVP by Power off VIN2 Over Current Protection The RT8159A utilizes low side MOSFET RDS(ON) peak current sensing technique. After low side MOSFET is turned on, the PHASE voltage is sensed for Over Current Protection (OCP). As shown in the Functional Block Diagram, A 40μA internal current source flows through an external resistor, ROCSET, causing a voltage drop across ROCSET. If the PHASE voltage (drop of lower MOSFET VDS) is lower than 0.4V while low side MOSFET is conducting, OCP will be tripped and UGATE and LGATE will go low as shown in Figure 5. Once OCP is triggered, the RT8159A enters hiccup mode and soft-starts again. The RT8159A shuts down after 4 times of OCP hiccups. The inductor peak current, IOCSET, for OCP can be approximately calculated using below equation : IOCSET ≅ www.richtek.com 10 40μ A × ROCSET − 0.4V RDS(ON) DS8159A-02 April 2011 RT8159A VIN1 OSC VOUT1 (2V/Div) Driver PWM Comparator ΔVOSC inductor current (20A/Div) LOUT - Driver + VOUT1 PHASE ESR UGATE (20V/Div) LGATE (20V/Div) COUT1 ZFB COMP EA + ZIN REF Time (4μs/Div) Figure 5. Detailed Waveform of PWM OCP Feedback Loop Compensation The PWM controller in RT8159A utilizes voltage-mode control. As shown in Figure 6, the controller loop is a single voltage feedback path including a compensator and modulator. The modulator consists of the PWM comparator and power stage. The PWM comparator compares error amplifer output (COMP) with oscillator (OSC) sawtooth wave to provide a width-modulated pulse with amplitude of VIN1 at the PHASE node. The waveform at PHASE node is filtered by the output filter LOUT and COUT. The output voltage (VOUT1) is sensed and is fed to the inverting input of the error amplifer. A well-designed compensator regulates the output voltage to the reference voltage V REF with fast transient response without instability. In order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. The goal of the compensator design is to provide adequate phase margin (greater than 45 degrees) and proper 0dB crossing frequency. It is also recommended to manipulate loop frequency response such that its gain crosses over 0dB at a slope of -20dB/ dec. ZFB C2 C1 ZIN VOUT1 C3 R2 R3 R1 COMP FB EA + REF RF Figure 6. Voltage-mode Control Loop 1) Modulator Frequency Equations The modulator transfer function is the small-signal transfer function of VOUT1/VCOMP (output voltage over the error amplifier output. This transfer function is dominated by a DC gain, a double pole, and a zero as shown in Figure 6. The DC gain of the modulator is the input voltage (VIN1) divided by the peak to peak oscillator voltage ΔVOSC. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degree. The resonant frequency of the output LC filter is : 1 fLC = 2π LOUT × COUT1 The zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor is expressed as follows : 1 fESR = 2π × COUT1 × ESR 2) Compensation Frequency Equations Figure 7 shows the type II compensator, which consists of the error amplifier and the impedance networks ZC and ZF. DS8159A-02 April 2011 www.richtek.com 11 RT8159A Thermal Considerations ZF C1 R2 ZC C2 R1 VOUT1 FB EA + COMP VREF RF For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surroundings airflow and difference between junction and ambient temperature. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) − TA ) / θJA The type II compensator has two poles and one zero. The first pole is located at low frequency. The location of the second pole and the zero are : fZ1 = 1 2π x R2 x C2 fP1 = 1 2π x R2 x C1 x C2 C1 + C2 Figure 8 shows the Bode plot of buck converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop response. High crossover frequency can achieve fast transient response, but often jeopardize the system stability. In order to cancel one of the LC filter poles to have −20dB/decade crossover, place the zero before the LC filter resonant frequency. Locating the zero at 75% LC filter resonant frequency is a good practice. Crossover frequency should be less than 1/5 of the switching frequency. The second pole is placed at half the switching frequency. 80 80 Loop Gain 60 40 40 Compensation Gain Gain (dB) 20 0 0 Modulator -20 Gain where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8159A, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-14 package, the thermal resistance θJA is 100°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (100°C/W) = 1.000W for SOP-14 package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. Figure 9 shows the derating curve of maximum power dissipation of the RT8159A. 1.2 Maximum Power Dissipation (W)1 Figure 7. Compensator in PWM Feedback Loop. Four-Layer PCB 1.1 1.0 0.9 0.8 SOP-14 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 -40-40 -60-60 10Hz 10vdb(vo) 25 50 75 100 125 Ambient Temperature (°C) 100Hz vdb(comp2)100 vdb(lo) 1.0KHz 10KHz 1k 10k Frequency (Hz) Frequency 100KHz 100k 1.0MHz 1M Figure 9. Derating Curve for RT8159A Package Figure 8. Bode Plot of Buck Converter www.richtek.com 12 DS8159A-02 April 2011 RT8159A for low side MOSFET because this can reduce the possibility of shoot-through. Inaddition, also make the width of gate driving path as wide as possible to reduce the trace resistance. The PCB traces between the PWM controller and the gate/source of MOSFET should be sized to carry 2A peak currents. Layout Considerations PCB layout is critical to high-current high-frequency switching converter design. A good layout can help the controller to function properly and obtain better performance. On the other hand, the circuit may have more power loss, poor performance and even malfunction if without a careful layout. Figure 10 shows the connections of the critical components in the buck converter. In order to obtain better performance, the general guidelines of PCB layout listed below should be strictly followed : ` Power stage components should be placed first. Place the input bulk capacitors close to the high side power MOSFETs. Then, locate the output inductor and finally the output capacitors. ` Place the ceramic capacitors physically close to the drain of the high side MOSFET. This can reduce the input voltage drop when high side MOSFET is turned on. ` Keep the high-current loops as short as possible. The current transition between MOSFETs usually causes di/dt voltage spike due to the parasitic components on PCB trace and component lead. Therefore, keeping the trace length between power MOSFETs and inductors wide and short can reduce the voltage spike and also reduce EMI. ` Keep MOSFET gate driver path as short as possible. Since the gate driver uses high current pulses to switch on/off power MOSFET, the driver path must be short to reduce the trace inductance. This is especially important Place RRT close to IC Place compensation components close to IC. Place CIN2 close to MOSFET. VIN2 VOUT2 ` Provide enough copper area around power MOSFETs to facilitate heat dissipation. Using thick copper also reduces the trace resistance and inductance to have better performance. ` The output capacitors should be placed physically close to the load. This can minimize the trace parasitic components and improve transient response. ` All small signal components should be placed close to the controller. The small signal components include the feedback voltage divider resistors, compensator, function setting components and high frequency bypass capacitors. The feedback voltage divider resistor and the compensator must be placed close to FB pin and COMP pin, because these pins are inherently noise-sensitive. ` Voltage feedback path must be kept away from switching nodes. The switching nodes, such as the interconnection between high side MOSFET, low side MOSFET and inductor, are extremely noisy. Feedback path must be kept away from this kind of noisy node to avoid noise pick-up. ` A multi-layer PCB design is recommended. Use one single layer as the ground and have separate layers for power rail or signal. Keep voltage feedback trace away from noisy node. Place CIN close to MOSFET. VIN1 MOSFET driver trace : wide and short. BOOT RT_DIS COMP FB DRV FBL GND 14 2 13 3 12 4 11 5 10 6 9 7 8 Enough copper area to carry load current. UGATE PHASE PGND LGATE OCSET NC VCC12 LOAD 12V Place voltage divider resistors close to IC. Place noise decoupling MLCC close to IC. Enough via to inner ground layer. VOUT1 LOAD Place COUT close to load. Place snubber close to low-side FET Figure 10. PCB Layout Guide DS8159A-02 April 2011 www.richtek.com 13 RT8159A Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 8.534 8.738 0.336 0.344 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 14–Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 14 DS8159A-02 April 2011