RT9046 Low-Dropout Linear Regulator Controller with PGOOD Indication General Description Features The RT9046 is a low-dropout voltage regulator controller designed specifically for use with an external N-MOSFET for various applications. The controller features a 2% reference, a high current driver capability of driving a high current/low RDS(ON) N-MOSFET, programmable output z Programmable Output Voltage z voltage, a power monitor with a 0.6ms delay, internal softstart function, under voltage protection, and chip enable for power conservation. The device is also useful in other high current applications. The RT9046 is available in a small footprint package of SOT-23-6. z High Current Driver for High Current FET High Accuracy ±2% Voltage Reference Quick Line and Load Transient Response Power Good Monitor with Output Delay Internal Soft-Start Function to Reduce Inrush Current Enable Control and Under Voltage Protection Small Footprint Package SOT-23-6 RoHS Compliant and Halogen Free z z z z z z Applications Ordering Information z RT9046 z Package Type E : SOT-23-6 z z Lead Plating System G : Green (Halogen Free and Pb Free) Note : Large-scale, Telecom Blade Systems Large-scale, Mass Storage Blade Systems High Current Systems Requiring Sequencing High Current Systems Requiring Power Management Pin Configurations (TOP VIEW) Richtek products are : ` RoHS compliant and compatible with the current require- VCC DRI PGOOD ments of IPC/JEDEC J-STD-020. ` 6 Suitable for use in SnPb or Pb-free soldering processes. Marking Information 5 4 2 3 EN GND FB For marking information, contact our sales representative directly or through a Richtek distributor located in your area. SOT-23-6 Function Block Diagram Typical Application Circuit 1 EN 2 3 VCC RT9046 DRI GND FB PGOOD 6 5 4 PGOOD CIN CCC PGOOD 0.45V + - DRI Driver 0.6ms Delay Q1 RPGOOD Reference 0.5V Voltage VOUT - Chip Enable VCC VIN + VCC EN FB GND R1 COUT VOUT = 0.5x[(R1+R2)/R2] DS9046-01 April 2011 R2 www.richtek.com 1 RT9046 Functional Pin Description Pin No. Pin Name Pin Function 1 EN Chip Enable (Active High). 2 GND Ground. 3 FB Output Voltage Feedback. 4 PGOOD Power Good Open Drain Output. 5 DRI Driver Output. 6 VCC Power Supply Input. Test Circuit VIN VCC 12V Chip Enable VCC EN RT9046 Q1 PHD3055 DRI GND FB CIN 100µF CCC 1µF RPGOOD PGOOD VOUT 100k R1 1k PGOOD VOUT = 0.5x[(R1+R2)/R2] COUT 100µF R2 2k Figure 1. Typical Test Circuit VCC 12V CCC 1µF Chip Enable 5V EN GND VFB FB VCC RT9046 DRI A VDRI PGOOD CFB VFB = 0.7V for current sink at DRI VFB = 0.3V for current source at DRI Figure 2. DRI Source/Sink Current Test Circuit www.richtek.com 2 DS9046-01 April 2011 RT9046 Absolute Maximum Ratings z z z z z z z z (Note 1) Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 15V Enable Voltage --------------------------------------------------------------------------------------------------------- 6.5V Power Good Output Voltage ---------------------------------------------------------------------------------------- 6.5V Power Dissipation, PD @ TA = 25°C SOT-23-6 ---------------------------------------------------------------------------------------------------------------- 0.4W Package Thermal Resistance (Note 2) SOT-23-6, θJA ----------------------------------------------------------------------------------------------------------- 250°C/W Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C Junction Temperature ------------------------------------------------------------------------------------------------- 150°C Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C Recommended Operating Conditions z z z z (Note 3) Supply Input Voltage, VCC ------------------------------------------------------------------------------------------- 3.3V to 13.5V Enable Voltage --------------------------------------------------------------------------------------------------------- 0V to 5.5V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VCC = 5V/12V, TA = 25°C, unless otherwise specified) Parameter Symbol POR Threshold Test Conditions VCC Rising POR Hysteresis Min Typ Max Unit 2.6 2.85 3.2 V -- 0.2 -- V VCC Supply Current VCC = 12V -- 0.3 0.8 mA Driver Source Current VCC = 12V, V DRI = 6V 5 -- -- mA Driver Sink Current VCC = 12V, V DRI = 6V 5 -- -- mA Reference Voltage (VFB ) VCC = 12V, V DRI = 5V 0.49 0.5 0.51 V Reference Line Regulation (VFB ) VCC = 4.5V to 15V -- 3 6 mV Amplifier Voltage Gain VCC = 12V, No Load -- 70 -- dB PSRR at 100Hz VCC = 12V, No Load 50 -- -- dB Rising Threshold VCC = 12V -- 90 -- % Hysteresis VCC = 12V -- 15 -- % Sink Capability VCC = 12V @ 1mA -- 0.2 0.4 V Delay Time VCC = 12V 0.2 0.6 2 ms Falling Delay VCC = 12V -- 15 -- μs V IH VCC = 12V 1.4 -- 5.5 V IL VCC = 12V -- -- 0.4 VCC = 12V, VEN = 0V -- -- 5 Power Good Chip Enable Logic-High Voltage EN Threshold Logic-Low Voltage Standby Current V μA To be Continued DS9046-01 April 2011 www.richtek.com 3 RT9046 Parameter Symbol Test Conditions Min Typ Max Unit VCC = 12V, VOUT = 1.5V, C OUT = 800μF 0.2 0.35 -- ms VCC = 12V 40 50 60 % Soft-Start Function Output Turn-On Rise Time UV Protection Under Voltage Protection Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. The device is not guaranteed to function outside its operating conditions. www.richtek.com 4 DS9046-01 April 2011 RT9046 Typical Operating Characteristics VIN = 1.8V, VOUT = 1.5V, VCC = 12V, CIN = COUT = 100μF, R1 = 4k, R2 = 2k, TA = 25°C, unless otherwise specified. Quiescent Current vs. Temperature 0.60 0.55 0.55 Quiescent Current (mA) Quiescent Current (mA) Quiescent Current vs. VCC Supply Voltage 0.60 0.50 0.45 0.40 0.35 VEN = 5V 0.30 4.5 5.5 6.5 7.5 8.5 9.5 0.50 0.45 0.40 0.35 VEN = 5V 0.30 -50 10.5 11.5 12.5 13.5 -25 0 VCC Supply Voltage (V) Shutdown Current vs. Temperature 75 100 125 EN Threshold Voltage vs. Temperature EN Threshold Voltage (V) Shutdown Current (μA) 50 0.95 0.04 0.02 0 -0.02 VEN = 0V -0.04 -50 -25 0 25 50 75 100 0.90 Rising 0.85 Falling 0.80 0.75 0.70 0.65 -50 125 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Reference Voltage vs. Temperature Reference Voltage vs. VCC Supply Voltage 0.510 0.510 0.508 0.508 0.505 0.505 Reference Voltage (V) Reference Voltage (V) 25 Temperature (°C) 0.503 0.500 0.498 0.495 0.503 0.500 0.498 0.495 0.493 0.493 VEN = 5V 0.490 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 VCC Supply Voltage (V) DS9046-01 April 2011 VEN = 5V 0.490 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 5 RT9046 DRI Sink Current vs. Temperature DRI Source Current vs. Temperature 25.0 60 DRI Sink Current (mA) DRI Source Current (mA) 22.5 55 50 45 40 20.0 17.5 15.0 12.5 10.0 7.5 VEN = 5V, VDRI = 6V, VFB = 0.3V 35 VEN = 5V, VDRI = 6V, VFB = 0.7V 5.0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) DRI Sink Current vs. DRI Voltage PGOOD Delay Time vs. Temperature 15 600 PGOOD Delay Time (μs) DRI Sink Current (mA) 550 12 9 6 3 0 500 450 400 350 300 250 VEN = 5V 200 0 0.5 1 1.5 2 2.5 3 -50 Start Up from EN and Inrush Current VEN (5V/Div) VOUT (1V/Div) PGOOD (1V/Div) I IN (1A/Div) PGOOD (1V/Div) Time (100μs/Div) www.richtek.com 6 0 25 50 75 100 125 Start Up from EN and PGOOD Delay VEN (5V/Div) VOUT (1V/Div) VEN = 5V, ILOAD = 0A -25 Temperature (°C) DRI Voltage (V) IOUT (2A/Div) VEN = 5V, ILOAD = 3A Time (100μs/Div) DS9046-01 April 2011 RT9046 PGOOD Off Start Up from VCC VEN (5V/Div) VOUT (2V/Div) VOUT (1V/Div) V CC (10V/Div) PGOOD (2V/Div) PGOOD (2V/Div) IOUT (2A/Div) I IN (2A/Div) VEN = 5V, ILOAD = 3A VEN = 5V, ILOAD = 3A Time (50μs/Div) Time (1ms/Div) Start Up from VIN Load Transient Response VOUT (1V/Div) VFB (20mV/Div) VIN (1V/Div) PGOOD (2V/Div) I LOAD (5A/Div) I IN (2A/Div) VEN = 5V, ILOAD = 3A Time (2.5ms/Div) VEN = 5V, ILOAD = 0A to 5A Time (250μs/Div) Line Transient Response 10 VFB (mV/Div) 0 -10 2.5 VIN (V/Div) 1.5 VIN = 1.5V to 2.5V, VEN = 5V, ILOAD = 3A Time (100μs/Div) DS9046-01 April 2011 www.richtek.com 7 RT9046 Application Information Capacitor Selection Chip Enable Operation External capacitors are necessary for the proper operation of the RT9046. The power supply, requires a 1μF ceramic capacitor between VCC and ground. This capacitor shunts power supply current transients to ground and stabilizes the input voltage to the RT9046. The capacitor should be placed as close to VCC as possible. The EN pin is the chip enable input. Pull the EN pin low (<0.4V) to shutdown the device. During shutdown mode, the RT9046 quiescent current drops below 5μA. The external capacitor and load current determine the output voltage decay rate (see Accelerating VOUT Shutdown to improve shutdown speed). Drive the EN pin high (>1.4V) to turn the device on again. The power source for the pass transistor, VIN, requires an input capacitor. A larger 100μF ceramic capacitor should be placed as close to the pass transistor's (Q1's) drain as possible to ensure the best PSRR and line transient response for VOUT. Again, it is necessary to place a 100μF capacitor between VOUT and ground to reduce noise, and improve load transient response and PSRR. Output Voltage Setting The output voltage, is determined using a simple resistor divider and the internal 0.5V, 2% reference. The output can be programmed by the following equation : VOUT = 0.5 × R1 + R2 R2 In order to achieve desired output voltage regulation, resistors must be selected for the accuracy of their nominal value. For a 5% accurate output voltage, 1% resistors should be employed in the design. Power Good Function The RT9046 has the power good function with 0.6ms delay. The power good output, is an open drain output. Connect a 100kΩ pull up resistor between VOUT and PGOOD, to sample the output voltage. When the output voltage, reaches 90% of the desired value, the power good will output a logic high 0.6ms later. When the output voltage drops below 75% of the desired value, PGOOD will output a logic low 15μs later. There are two exceptions : if the chip enable is pulled low or if VCC drops below the power-on reset (POR) value (2.65V @ 25°C), PGOOD will output a logic low. Under Voltage Protection The RT9046 provides VOUT with under voltage protection, UVP. The UVP circuit begins monitoring VOUT after it achieves 90% of the desired output voltage and the PGOOD pin has output a logic high. If VOUT drops below 50% of its desired value, the PGOOD and DRI pins will be pulled low and the RT9046 will enter latch mode. The RT9046 can only be unlatched by cycling the VCC or EN pin low and then high again. This action will cause the RT9046 to exit the latch mode and restart. MOSFET Selection The RT9046 is designed to drive an external N-MOSFET. The MOSFET selection criteria include : ` Maximum continuous drain current, IDMAX ` On-resistance, RDS(ON) ` Threshold voltage, VGS_TH ` Drain-to-source voltage, VDS ` Package thermal resistance, θJA The MOSFET must be able to carry the maximum current required by the load at VOUT. MOSFET ID(MAX) should be greater than or equal to ILOAD(MAX) for VOUT. Once we know ILOAD(MAX), we can calculate the maximum allowable MOSFET RDS(ON) as follows : RDS(ON) = ILOAD(MAX) For example, if the maximum load current, ILOAD(MAX), is 2A, VIN is 1.5V, and VOUT is 1.2V, then RDS(ON) = www.richtek.com 8 ( VIN − VOUT ) (1.5V − 1.2V ) 2A = 150mΩ DS9046-01 April 2011 RT9046 Thus, the MOSFET must have an RDS(ON) equal to or lower than 150mΩ when operating with VDS of 0.3V at 2A. The MOSFET must also have a VGS_TH low enough to be turned on by the driver circuit at the driver output, VDRI. Finally, the MOSFET's junction to ambient temperature thermal resistance, θ JA , must be considered. The MOSFET's junction temperature should be kept below its recommended maximum junction temperature; TJ(MAX) = 125°C is a conservative maximum junction temperature. In the worst case example, the MOSFET will have to dissipate, 0.6W : PD = VDS x IDS(MAX). In order to keep the junction temperature below the RT9046's guaranteed maximum operating ambient temperature specification (TA(MAX)) of 85°C, we must select a MOSFET with a θJA of less than 67°C/W : θJA = (TJ(MAX) − TA(MAX))/ P D. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9046, the junction temperature is 125°Cand TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For SOT-23-6 A Philips PHD3055E N-MOSFET with a θJA of 50°C/W in the D-PAK package, maximum R DS(ON) of 150mΩ at VGS = 10V, ID(MAX) = 10.3A, and VDSS = 55V is a good choice. packages, the thermal resistance θJA is 250°C/W on the standard JEDEC 51-3 single layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : Higher current and power applications may require the use of additional layout consideration, package selections, and PCB application in order to improve thermal performance of the MOSFET. P D(MAX) = (125°C − 25°C) / (250°C/W) = 0.4W for SOT-23-6 package In order to accelerate the shutdown of VOUT, a PNP transistor can be used. Given the sink capabilities of the RT9046's DRI output the KSB772 PNP transistor is a good choice. Figure 3 shows the implementation of this circuit with Q2 as the KSB772 PNP transistor. Shutdown delay will be determined by the load current. V IN PGOOD V CC C CC Chip Enable VCC DRI RT9046 GND PGOOD EN C IN Q1 R PGOOD V OUT FB R1 Q2 C OUT 0.50 Maximum Power Dissipation (W) Accelerating VOUT Shutdown The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT9046 package, the Figure 4 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Single Layer PCB 0.45 0.40 0.35 SOT-23-6 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 R2 Figure 3 DS9046-01 April 2011 25 50 75 100 125 Ambient Temperature (°C) Figure 4. Derating Curves for RT9046 Packages www.richtek.com 9 RT9046 Layout Considerations There are three critical layout considerations. The divider resistors, R1 and R2, should be mounted as close to the RT9046 FB pin as possible to minimize noise. Capacitor, CIN, should be as close to the MOSFET's drain as possible, and output capacitor, COUT, as close to the MOSFET's source as possible. Finally, in cases where high load currents are required, designers will have to get creative. MOSFETs with mountable drains, increased copper in the layout, and fan generated air flow may be necessary to achieve workable designs. A layout example demonstrating passive placement and using increased copper area for the drain of a MOSFET pass transistor in the D-PAK package is illustrated by Figure 5. V IN + GND PGOOD V CC + V OUT FB EN + GND Figure 5 www.richtek.com 10 DS9046-01 April 2011 RT9046 Outline Dimension H D L C B b A A1 e Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.889 1.295 0.031 0.051 A1 0.000 0.152 0.000 0.006 B 1.397 1.803 0.055 0.071 b 0.250 0.560 0.010 0.022 C 2.591 2.997 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 SOT-23-6 Surface Mount Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9046-01 April 2011 www.richtek.com 11